2006-02-05 05:50:24 +00:00
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//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
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2005-12-17 07:47:01 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-12-17 07:47:01 +00:00
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//
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//===----------------------------------------------------------------------===//
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//
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2006-02-05 05:50:24 +00:00
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// This file defines an instruction selector for the SPARC target.
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2005-12-17 07:47:01 +00:00
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//
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//===----------------------------------------------------------------------===//
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2006-02-05 05:50:24 +00:00
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#include "SparcTargetMachine.h"
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2005-12-17 07:47:01 +00:00
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#include "llvm/CodeGen/SelectionDAGISel.h"
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2013-01-02 11:36:10 +00:00
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#include "llvm/IR/Intrinsics.h"
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2008-02-03 05:43:57 +00:00
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#include "llvm/Support/Compiler.h"
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2005-12-17 07:47:01 +00:00
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#include "llvm/Support/Debug.h"
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2009-07-08 20:53:28 +00:00
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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2005-12-17 07:47:01 +00:00
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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2006-02-05 05:50:24 +00:00
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/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
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2005-12-17 07:47:01 +00:00
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/// instructions for SelectionDAG operations.
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///
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namespace {
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2006-02-05 05:50:24 +00:00
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class SparcDAGToDAGISel : public SelectionDAGISel {
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First step towards V9 instructions in the V8 backend, two conditional move
patterns. This allows emission of this code:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
move %icc, %i0, %i2
or %g0, %i2, %i0
restore %g0, %g0, %g0
retl
nop
instead of this:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
be .LBBt1_2 !
nop
.LBBt1_1: !
or %g0, %i2, %i0
.LBBt1_2: !
restore %g0, %g0, %g0
retl
nop
for this:
int %t1(int %a, int %b, int %c) {
%tmp.2 = seteq int %a, %b
%tmp3 = select bool %tmp.2, int %a, int %c
ret int %tmp3
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25809 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 05:35:57 +00:00
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/// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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2006-02-05 05:50:24 +00:00
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const SparcSubtarget &Subtarget;
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2013-06-19 21:36:55 +00:00
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SparcTargetMachine &TM;
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2005-12-17 07:47:01 +00:00
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public:
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2009-09-15 17:46:24 +00:00
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explicit SparcDAGToDAGISel(SparcTargetMachine &tm)
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: SelectionDAGISel(tm),
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Subtarget(tm.getSubtarget<SparcSubtarget>()),
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TM(tm) {
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First step towards V9 instructions in the V8 backend, two conditional move
patterns. This allows emission of this code:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
move %icc, %i0, %i2
or %g0, %i2, %i0
restore %g0, %g0, %g0
retl
nop
instead of this:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
be .LBBt1_2 !
nop
.LBBt1_1: !
or %g0, %i2, %i0
.LBBt1_2: !
restore %g0, %g0, %g0
retl
nop
for this:
int %t1(int %a, int %b, int %c) {
%tmp.2 = seteq int %a, %b
%tmp3 = select bool %tmp.2, int %a, int %c
ret int %tmp3
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25809 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 05:35:57 +00:00
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}
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2005-12-17 07:47:01 +00:00
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2010-01-05 01:24:18 +00:00
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SDNode *Select(SDNode *N);
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2005-12-17 07:47:01 +00:00
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2005-12-17 20:04:49 +00:00
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// Complex Pattern Selectors.
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2010-09-21 20:31:19 +00:00
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bool SelectADDRrr(SDValue N, SDValue &R1, SDValue &R2);
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bool SelectADDRri(SDValue N, SDValue &Base, SDValue &Offset);
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2008-10-10 10:14:15 +00:00
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2008-10-10 10:14:47 +00:00
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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char ConstraintCode,
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std::vector<SDValue> &OutOps);
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2005-12-17 07:47:01 +00:00
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virtual const char *getPassName() const {
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2006-02-05 05:50:24 +00:00
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return "SPARC DAG->DAG Pattern Instruction Selection";
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2008-10-10 10:14:15 +00:00
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}
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2005-12-17 07:47:01 +00:00
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// Include the pieces autogenerated from the target description.
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2006-02-05 05:50:24 +00:00
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#include "SparcGenDAGISel.inc"
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2009-09-15 17:46:24 +00:00
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private:
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SDNode* getGlobalBaseReg();
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2005-12-17 07:47:01 +00:00
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};
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} // end anonymous namespace
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2009-09-15 17:46:24 +00:00
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SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
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unsigned GlobalBaseReg = TM.getInstrInfo()->getGlobalBaseReg(MF);
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2013-06-19 21:36:55 +00:00
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return CurDAG->getRegister(GlobalBaseReg,
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getTargetLowering()->getPointerTy()).getNode();
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2009-09-15 17:46:24 +00:00
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}
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2010-09-21 20:31:19 +00:00
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bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr,
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2008-07-27 21:46:04 +00:00
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SDValue &Base, SDValue &Offset) {
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2005-12-18 07:09:06 +00:00
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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2013-06-19 21:36:55 +00:00
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(),
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getTargetLowering()->getPointerTy());
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2009-08-11 20:47:22 +00:00
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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2005-12-18 06:59:57 +00:00
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return true;
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}
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2008-09-16 21:48:12 +00:00
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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2013-09-22 06:48:52 +00:00
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Addr.getOpcode() == ISD::TargetGlobalAddress ||
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Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
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2006-02-10 07:35:42 +00:00
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return false; // direct calls.
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2008-10-10 10:14:15 +00:00
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2005-12-17 21:25:27 +00:00
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if (Addr.getOpcode() == ISD::ADD) {
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2005-12-18 06:59:57 +00:00
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
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2010-08-17 18:17:12 +00:00
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if (isInt<13>(CN->getSExtValue())) {
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2008-10-10 10:14:15 +00:00
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if (FrameIndexSDNode *FIN =
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2005-12-18 07:09:06 +00:00
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dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
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2005-12-18 06:59:57 +00:00
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// Constant offset from frame ref.
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2013-04-13 19:02:16 +00:00
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(),
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2013-06-19 21:36:55 +00:00
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getTargetLowering()->getPointerTy());
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2005-12-18 06:59:57 +00:00
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} else {
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2006-02-05 08:35:50 +00:00
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Base = Addr.getOperand(0);
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2005-12-18 06:59:57 +00:00
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}
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2009-08-11 20:47:22 +00:00
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Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
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2005-12-17 21:25:27 +00:00
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return true;
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}
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2005-12-18 06:59:57 +00:00
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}
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2006-02-05 05:50:24 +00:00
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if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
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2006-02-05 08:35:50 +00:00
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Base = Addr.getOperand(1);
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Teach the addressing mode stuff to fold "%lo" into 'ri' addressing modes,
allowing us to compile this:
to this:
%G1 = external global int
%G2 = external global int
void %test() {
%X = load int* %G1
store int %X, int* %G2
ret void
}
test:
save -96, %sp, %sp
sethi %hi(G1), %l0
ld [%l0+%lo(G1)], %l0
sethi %hi(G2), %l1
st %l0, [%l1+%lo(G2)]
restore %g0, %g0, %g0
retl
nop
instead of this:
test:
save -96, %sp, %sp
sethi %hi(G1), %l0
or %g0, %lo(G1), %l1
ld [%l1+%l0], %l0
sethi %hi(G2), %l1
or %g0, %lo(G2), %l2
st %l0, [%l2+%l1]
restore %g0, %g0, %g0
retl
nop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24812 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-18 02:27:00 +00:00
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Offset = Addr.getOperand(0).getOperand(0);
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return true;
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}
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2006-02-05 05:50:24 +00:00
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if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
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2006-02-05 08:35:50 +00:00
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Base = Addr.getOperand(0);
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Teach the addressing mode stuff to fold "%lo" into 'ri' addressing modes,
allowing us to compile this:
to this:
%G1 = external global int
%G2 = external global int
void %test() {
%X = load int* %G1
store int %X, int* %G2
ret void
}
test:
save -96, %sp, %sp
sethi %hi(G1), %l0
ld [%l0+%lo(G1)], %l0
sethi %hi(G2), %l1
st %l0, [%l1+%lo(G2)]
restore %g0, %g0, %g0
retl
nop
instead of this:
test:
save -96, %sp, %sp
sethi %hi(G1), %l0
or %g0, %lo(G1), %l1
ld [%l1+%l0], %l0
sethi %hi(G2), %l1
or %g0, %lo(G2), %l2
st %l0, [%l2+%l1]
restore %g0, %g0, %g0
retl
nop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24812 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-18 02:27:00 +00:00
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Offset = Addr.getOperand(1).getOperand(0);
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return true;
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}
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2005-12-17 21:25:27 +00:00
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}
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2006-02-05 08:35:50 +00:00
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Base = Addr;
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2009-08-11 20:47:22 +00:00
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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2005-12-17 20:04:49 +00:00
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return true;
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}
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2010-09-21 20:31:19 +00:00
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bool SparcDAGToDAGISel::SelectADDRrr(SDValue Addr, SDValue &R1, SDValue &R2) {
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2006-02-10 07:35:42 +00:00
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if (Addr.getOpcode() == ISD::FrameIndex) return false;
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2008-09-16 21:48:12 +00:00
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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2013-09-22 06:48:52 +00:00
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Addr.getOpcode() == ISD::TargetGlobalAddress ||
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Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
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2006-02-10 07:35:42 +00:00
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return false; // direct calls.
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2008-10-10 10:14:15 +00:00
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2005-12-18 06:59:57 +00:00
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if (Addr.getOpcode() == ISD::ADD) {
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2010-08-17 18:17:12 +00:00
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
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if (isInt<13>(CN->getSExtValue()))
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return false; // Let the reg+imm pattern catch this!
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2006-02-05 05:50:24 +00:00
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if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
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Addr.getOperand(1).getOpcode() == SPISD::Lo)
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2005-12-18 06:59:57 +00:00
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return false; // Let the reg+imm pattern catch this!
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2006-02-05 08:35:50 +00:00
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R1 = Addr.getOperand(0);
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R2 = Addr.getOperand(1);
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2005-12-18 06:59:57 +00:00
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return true;
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}
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2006-02-05 08:35:50 +00:00
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R1 = Addr;
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2013-06-19 21:36:55 +00:00
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R2 = CurDAG->getRegister(SP::G0, getTargetLowering()->getPointerTy());
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2005-12-18 06:59:57 +00:00
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return true;
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}
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2005-12-17 07:47:01 +00:00
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2010-01-05 01:24:18 +00:00
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SDNode *SparcDAGToDAGISel::Select(SDNode *N) {
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2013-05-25 02:42:55 +00:00
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SDLoc dl(N);
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2013-09-22 08:21:56 +00:00
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if (N->isMachineOpcode()) {
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N->setNodeId(-1);
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2006-08-11 09:08:15 +00:00
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return NULL; // Already selected.
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2013-09-22 08:21:56 +00:00
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}
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2006-02-09 00:37:58 +00:00
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2005-12-17 07:47:01 +00:00
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switch (N->getOpcode()) {
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default: break;
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2009-09-15 17:46:24 +00:00
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case SPISD::GLOBAL_BASE_REG:
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return getGlobalBaseReg();
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2005-12-17 22:39:19 +00:00
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case ISD::SDIV:
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case ISD::UDIV: {
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2013-04-16 02:57:02 +00:00
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// sdivx / udivx handle 64-bit divides.
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if (N->getValueType(0) == MVT::i64)
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break;
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2005-12-17 22:39:19 +00:00
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// FIXME: should use a custom expander to expose the SRA to the dag.
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2008-07-27 21:46:04 +00:00
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SDValue DivLHS = N->getOperand(0);
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SDValue DivRHS = N->getOperand(1);
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2008-10-10 10:14:15 +00:00
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2005-12-17 22:39:19 +00:00
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// Set the Y register to the high-part.
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2008-07-27 21:46:04 +00:00
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SDValue TopPart;
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2005-12-17 22:39:19 +00:00
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if (N->getOpcode() == ISD::SDIV) {
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2009-09-25 18:54:59 +00:00
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TopPart = SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS,
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2009-08-11 20:47:22 +00:00
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CurDAG->getTargetConstant(31, MVT::i32)), 0);
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2005-12-17 22:39:19 +00:00
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} else {
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2009-08-11 20:47:22 +00:00
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TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
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2005-12-17 22:39:19 +00:00
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}
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2010-12-21 02:38:05 +00:00
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TopPart = SDValue(CurDAG->getMachineNode(SP::WRYrr, dl, MVT::Glue, TopPart,
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2009-08-11 20:47:22 +00:00
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CurDAG->getRegister(SP::G0, MVT::i32)), 0);
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2005-12-17 22:39:19 +00:00
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// FIXME: Handle div by immediate.
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2006-02-05 05:50:24 +00:00
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unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
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2009-08-11 20:47:22 +00:00
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return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
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2006-08-26 08:00:10 +00:00
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TopPart);
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2008-10-10 10:14:15 +00:00
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}
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2005-12-17 22:30:00 +00:00
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case ISD::MULHU:
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case ISD::MULHS: {
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2005-12-17 22:39:19 +00:00
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// FIXME: Handle mul by immediate.
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2008-07-27 21:46:04 +00:00
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SDValue MulLHS = N->getOperand(0);
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SDValue MulRHS = N->getOperand(1);
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2006-02-05 05:50:24 +00:00
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unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
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2010-12-21 02:38:05 +00:00
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SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
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2009-09-25 18:54:59 +00:00
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MulLHS, MulRHS);
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2005-12-17 22:30:00 +00:00
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// The high part is in the Y register.
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2009-08-11 20:47:22 +00:00
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return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1));
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2005-12-17 22:30:00 +00:00
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}
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2005-12-17 07:47:01 +00:00
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}
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2008-10-10 10:14:15 +00:00
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2010-01-05 01:24:18 +00:00
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return SelectCode(N);
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2005-12-17 07:47:01 +00:00
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}
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2008-10-10 10:14:47 +00:00
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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bool
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SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
|
|
|
|
char ConstraintCode,
|
|
|
|
std::vector<SDValue> &OutOps) {
|
|
|
|
SDValue Op0, Op1;
|
|
|
|
switch (ConstraintCode) {
|
|
|
|
default: return true;
|
|
|
|
case 'm': // memory
|
2010-09-21 20:31:19 +00:00
|
|
|
if (!SelectADDRrr(Op, Op0, Op1))
|
|
|
|
SelectADDRri(Op, Op0, Op1);
|
2008-10-10 10:14:47 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
OutOps.push_back(Op0);
|
|
|
|
OutOps.push_back(Op1);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2008-10-10 10:14:15 +00:00
|
|
|
/// createSparcISelDag - This pass converts a legalized DAG into a
|
2006-01-26 07:22:22 +00:00
|
|
|
/// SPARC-specific DAG, ready for instruction scheduling.
|
2005-12-17 07:47:01 +00:00
|
|
|
///
|
2008-10-03 16:55:19 +00:00
|
|
|
FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {
|
2006-02-05 05:50:24 +00:00
|
|
|
return new SparcDAGToDAGISel(TM);
|
2005-12-17 07:47:01 +00:00
|
|
|
}
|