2006-02-05 05:50:24 +00:00
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//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
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2005-12-17 07:47:01 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-12-17 07:47:01 +00:00
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//
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//===----------------------------------------------------------------------===//
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//
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2006-02-05 05:50:24 +00:00
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// This file defines an instruction selector for the SPARC target.
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2005-12-17 07:47:01 +00:00
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//
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//===----------------------------------------------------------------------===//
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2008-03-17 03:21:36 +00:00
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#include "SparcISelLowering.h"
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2006-02-05 05:50:24 +00:00
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#include "SparcTargetMachine.h"
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2006-03-25 06:47:10 +00:00
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#include "llvm/Intrinsics.h"
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2005-12-17 07:47:01 +00:00
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#include "llvm/CodeGen/SelectionDAGISel.h"
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2008-02-03 05:43:57 +00:00
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#include "llvm/Support/Compiler.h"
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2005-12-17 07:47:01 +00:00
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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2006-02-05 05:50:24 +00:00
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/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
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2005-12-17 07:47:01 +00:00
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/// instructions for SelectionDAG operations.
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///
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namespace {
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2006-02-05 05:50:24 +00:00
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class SparcDAGToDAGISel : public SelectionDAGISel {
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SparcTargetLowering Lowering;
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First step towards V9 instructions in the V8 backend, two conditional move
patterns. This allows emission of this code:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
move %icc, %i0, %i2
or %g0, %i2, %i0
restore %g0, %g0, %g0
retl
nop
instead of this:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
be .LBBt1_2 !
nop
.LBBt1_1: !
or %g0, %i2, %i0
.LBBt1_2: !
restore %g0, %g0, %g0
retl
nop
for this:
int %t1(int %a, int %b, int %c) {
%tmp.2 = seteq int %a, %b
%tmp3 = select bool %tmp.2, int %a, int %c
ret int %tmp3
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25809 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 05:35:57 +00:00
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/// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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2006-02-05 05:50:24 +00:00
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const SparcSubtarget &Subtarget;
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2005-12-17 07:47:01 +00:00
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public:
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2008-07-07 18:00:37 +00:00
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explicit SparcDAGToDAGISel(TargetMachine &TM)
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2006-02-05 05:50:24 +00:00
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: SelectionDAGISel(Lowering), Lowering(TM),
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Subtarget(TM.getSubtarget<SparcSubtarget>()) {
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First step towards V9 instructions in the V8 backend, two conditional move
patterns. This allows emission of this code:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
move %icc, %i0, %i2
or %g0, %i2, %i0
restore %g0, %g0, %g0
retl
nop
instead of this:
t1:
save -96, %o6, %o6
subcc %i0, %i1, %l0
be .LBBt1_2 !
nop
.LBBt1_1: !
or %g0, %i2, %i0
.LBBt1_2: !
restore %g0, %g0, %g0
retl
nop
for this:
int %t1(int %a, int %b, int %c) {
%tmp.2 = seteq int %a, %b
%tmp3 = select bool %tmp.2, int %a, int %c
ret int %tmp3
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25809 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-30 05:35:57 +00:00
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}
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2005-12-17 07:47:01 +00:00
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2006-08-26 05:34:46 +00:00
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SDNode *Select(SDOperand Op);
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2005-12-17 07:47:01 +00:00
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2005-12-17 20:04:49 +00:00
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// Complex Pattern Selectors.
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2006-11-08 20:34:28 +00:00
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bool SelectADDRrr(SDOperand Op, SDOperand N, SDOperand &R1, SDOperand &R2);
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bool SelectADDRri(SDOperand Op, SDOperand N, SDOperand &Base,
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SDOperand &Offset);
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2005-12-17 20:04:49 +00:00
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2008-06-30 20:45:06 +00:00
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/// InstructionSelect - This callback is invoked by
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2005-12-17 07:47:01 +00:00
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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2008-06-30 20:45:06 +00:00
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virtual void InstructionSelect(SelectionDAG &DAG);
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2005-12-17 07:47:01 +00:00
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virtual const char *getPassName() const {
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2006-02-05 05:50:24 +00:00
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return "SPARC DAG->DAG Pattern Instruction Selection";
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2005-12-17 07:47:01 +00:00
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}
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// Include the pieces autogenerated from the target description.
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2006-02-05 05:50:24 +00:00
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#include "SparcGenDAGISel.inc"
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2005-12-17 07:47:01 +00:00
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};
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} // end anonymous namespace
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2008-06-30 20:45:06 +00:00
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/// InstructionSelect - This callback is invoked by
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2005-12-17 07:47:01 +00:00
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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2008-06-30 20:45:06 +00:00
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void SparcDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
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2005-12-17 07:47:01 +00:00
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DEBUG(BB->dump());
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// Select target instructions for the DAG.
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2006-02-05 06:51:51 +00:00
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DAG.setRoot(SelectRoot(DAG.getRoot()));
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2005-12-17 07:47:01 +00:00
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DAG.RemoveDeadNodes();
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}
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2006-11-08 20:34:28 +00:00
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bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr,
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SDOperand &Base, SDOperand &Offset) {
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2005-12-18 07:09:06 +00:00
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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2005-12-18 06:59:57 +00:00
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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2006-02-10 07:35:42 +00:00
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress)
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return false; // direct calls.
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2005-12-18 06:59:57 +00:00
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2005-12-17 21:25:27 +00:00
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if (Addr.getOpcode() == ISD::ADD) {
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2005-12-18 06:59:57 +00:00
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
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2005-12-17 21:25:27 +00:00
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if (Predicate_simm13(CN)) {
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2005-12-18 07:09:06 +00:00
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if (FrameIndexSDNode *FIN =
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dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
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2005-12-18 06:59:57 +00:00
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// Constant offset from frame ref.
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2005-12-18 07:09:06 +00:00
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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2005-12-18 06:59:57 +00:00
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} else {
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2006-02-05 08:35:50 +00:00
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Base = Addr.getOperand(0);
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2005-12-18 06:59:57 +00:00
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}
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2005-12-17 21:25:27 +00:00
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Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
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return true;
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}
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2005-12-18 06:59:57 +00:00
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}
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2006-02-05 05:50:24 +00:00
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if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
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2006-02-05 08:35:50 +00:00
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Base = Addr.getOperand(1);
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Teach the addressing mode stuff to fold "%lo" into 'ri' addressing modes,
allowing us to compile this:
to this:
%G1 = external global int
%G2 = external global int
void %test() {
%X = load int* %G1
store int %X, int* %G2
ret void
}
test:
save -96, %sp, %sp
sethi %hi(G1), %l0
ld [%l0+%lo(G1)], %l0
sethi %hi(G2), %l1
st %l0, [%l1+%lo(G2)]
restore %g0, %g0, %g0
retl
nop
instead of this:
test:
save -96, %sp, %sp
sethi %hi(G1), %l0
or %g0, %lo(G1), %l1
ld [%l1+%l0], %l0
sethi %hi(G2), %l1
or %g0, %lo(G2), %l2
st %l0, [%l2+%l1]
restore %g0, %g0, %g0
retl
nop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24812 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-18 02:27:00 +00:00
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Offset = Addr.getOperand(0).getOperand(0);
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return true;
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}
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2006-02-05 05:50:24 +00:00
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if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
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2006-02-05 08:35:50 +00:00
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Base = Addr.getOperand(0);
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Teach the addressing mode stuff to fold "%lo" into 'ri' addressing modes,
allowing us to compile this:
to this:
%G1 = external global int
%G2 = external global int
void %test() {
%X = load int* %G1
store int %X, int* %G2
ret void
}
test:
save -96, %sp, %sp
sethi %hi(G1), %l0
ld [%l0+%lo(G1)], %l0
sethi %hi(G2), %l1
st %l0, [%l1+%lo(G2)]
restore %g0, %g0, %g0
retl
nop
instead of this:
test:
save -96, %sp, %sp
sethi %hi(G1), %l0
or %g0, %lo(G1), %l1
ld [%l1+%l0], %l0
sethi %hi(G2), %l1
or %g0, %lo(G2), %l2
st %l0, [%l2+%l1]
restore %g0, %g0, %g0
retl
nop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24812 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-18 02:27:00 +00:00
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Offset = Addr.getOperand(1).getOperand(0);
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return true;
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}
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2005-12-17 21:25:27 +00:00
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}
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2006-02-05 08:35:50 +00:00
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Base = Addr;
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2005-12-17 20:04:49 +00:00
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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2006-11-08 20:34:28 +00:00
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bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Op, SDOperand Addr,
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SDOperand &R1, SDOperand &R2) {
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2006-02-10 07:35:42 +00:00
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if (Addr.getOpcode() == ISD::FrameIndex) return false;
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress)
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return false; // direct calls.
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2005-12-18 06:59:57 +00:00
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if (Addr.getOpcode() == ISD::ADD) {
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if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
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Predicate_simm13(Addr.getOperand(1).Val))
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return false; // Let the reg+imm pattern catch this!
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2006-02-05 05:50:24 +00:00
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if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
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Addr.getOperand(1).getOpcode() == SPISD::Lo)
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2005-12-18 06:59:57 +00:00
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return false; // Let the reg+imm pattern catch this!
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2006-02-05 08:35:50 +00:00
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R1 = Addr.getOperand(0);
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R2 = Addr.getOperand(1);
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2005-12-18 06:59:57 +00:00
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return true;
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}
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2006-02-05 08:35:50 +00:00
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R1 = Addr;
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2006-02-05 05:50:24 +00:00
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R2 = CurDAG->getRegister(SP::G0, MVT::i32);
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2005-12-18 06:59:57 +00:00
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return true;
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}
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2005-12-17 07:47:01 +00:00
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2006-08-26 05:34:46 +00:00
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SDNode *SparcDAGToDAGISel::Select(SDOperand Op) {
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2005-12-17 07:47:01 +00:00
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SDNode *N = Op.Val;
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2008-07-17 19:10:17 +00:00
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if (N->isMachineOpcode())
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2006-08-11 09:08:15 +00:00
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return NULL; // Already selected.
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2006-02-09 00:37:58 +00:00
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2005-12-17 07:47:01 +00:00
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switch (N->getOpcode()) {
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default: break;
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2005-12-17 22:39:19 +00:00
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case ISD::SDIV:
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case ISD::UDIV: {
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// FIXME: should use a custom expander to expose the SRA to the dag.
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2006-08-26 01:07:58 +00:00
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SDOperand DivLHS = N->getOperand(0);
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SDOperand DivRHS = N->getOperand(1);
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AddToISelQueue(DivLHS);
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AddToISelQueue(DivRHS);
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2005-12-17 22:39:19 +00:00
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// Set the Y register to the high-part.
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SDOperand TopPart;
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if (N->getOpcode() == ISD::SDIV) {
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2006-02-09 07:17:49 +00:00
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TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
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CurDAG->getTargetConstant(31, MVT::i32)), 0);
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2005-12-17 22:39:19 +00:00
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} else {
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2006-02-05 05:50:24 +00:00
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TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
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2005-12-17 22:39:19 +00:00
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}
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2006-02-09 07:17:49 +00:00
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TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
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CurDAG->getRegister(SP::G0, MVT::i32)), 0);
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2005-12-17 22:39:19 +00:00
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// FIXME: Handle div by immediate.
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2006-02-05 05:50:24 +00:00
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unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
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2006-08-16 07:30:09 +00:00
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return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
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2006-08-26 08:00:10 +00:00
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TopPart);
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2005-12-17 22:39:19 +00:00
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}
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2005-12-17 22:30:00 +00:00
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case ISD::MULHU:
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case ISD::MULHS: {
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2005-12-17 22:39:19 +00:00
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// FIXME: Handle mul by immediate.
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2006-08-26 01:07:58 +00:00
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SDOperand MulLHS = N->getOperand(0);
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SDOperand MulRHS = N->getOperand(1);
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AddToISelQueue(MulLHS);
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AddToISelQueue(MulRHS);
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2006-02-05 05:50:24 +00:00
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unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
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2006-02-09 07:17:49 +00:00
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SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
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2006-02-10 07:35:42 +00:00
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MulLHS, MulRHS);
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2005-12-17 22:30:00 +00:00
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// The high part is in the Y register.
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2006-08-26 08:00:10 +00:00
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return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
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2006-08-11 09:08:15 +00:00
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return NULL;
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2005-12-17 22:30:00 +00:00
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}
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2005-12-17 07:47:01 +00:00
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}
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2006-08-26 05:34:46 +00:00
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return SelectCode(Op);
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2005-12-17 07:47:01 +00:00
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}
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2006-02-05 05:50:24 +00:00
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/// createSparcISelDag - This pass converts a legalized DAG into a
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2006-01-26 07:22:22 +00:00
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/// SPARC-specific DAG, ready for instruction scheduling.
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2005-12-17 07:47:01 +00:00
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///
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2006-02-05 05:50:24 +00:00
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FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) {
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return new SparcDAGToDAGISel(TM);
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2005-12-17 07:47:01 +00:00
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}
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