2012-02-18 12:03:15 +00:00
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//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
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//
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2005-10-14 23:37:35 +00:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2012-02-18 12:03:15 +00:00
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//
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2005-10-14 23:37:35 +00:00
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//===----------------------------------------------------------------------===//
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//
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// This is the top level entry point for the PowerPC target.
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//
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//===----------------------------------------------------------------------===//
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// Get the target-independent interfaces which we are implementing.
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//
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2008-11-24 07:34:46 +00:00
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include "llvm/Target/Target.td"
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2005-10-14 23:37:35 +00:00
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2005-10-19 19:51:16 +00:00
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//===----------------------------------------------------------------------===//
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2005-10-22 08:04:24 +00:00
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// PowerPC Subtarget features.
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2005-10-19 19:51:16 +00:00
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//
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2006-12-12 20:57:08 +00:00
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//===----------------------------------------------------------------------===//
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// CPU Directives //
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//===----------------------------------------------------------------------===//
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2011-10-17 04:03:49 +00:00
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def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
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2006-12-12 20:57:08 +00:00
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def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
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def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
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def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
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def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
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def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
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def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
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def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
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def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
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def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
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def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
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2012-04-01 19:22:40 +00:00
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def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
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2012-08-28 16:12:39 +00:00
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def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
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"PPC::DIR_E500mc", "">;
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def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective",
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"PPC::DIR_E5500", "">;
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2013-02-01 22:59:51 +00:00
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def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
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def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
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def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
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def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
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2012-06-11 15:43:08 +00:00
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def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
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2013-02-01 22:59:51 +00:00
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def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
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2012-06-11 15:43:08 +00:00
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def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
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2006-12-12 20:57:08 +00:00
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2006-06-16 17:34:12 +00:00
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def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
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2005-10-23 05:28:51 +00:00
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"Enable 64-bit instructions">;
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2006-06-16 17:34:12 +00:00
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def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
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"Enable 64-bit registers usage for ppc32 [beta]">;
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Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
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def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true",
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"Use condition-register bits individually">;
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2006-01-27 08:09:42 +00:00
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def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
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2005-10-23 05:28:51 +00:00
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"Enable Altivec instructions">;
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2012-06-11 19:57:01 +00:00
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def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
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"Enable the MFOCRF instruction">;
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2006-01-27 08:09:42 +00:00
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def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
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2011-10-14 18:54:13 +00:00
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"Enable the fsqrt instruction">;
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2013-08-19 05:01:02 +00:00
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def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
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"Enable the fcpsgn instruction">;
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2013-04-03 04:01:11 +00:00
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def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true",
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"Enable the fre instruction">;
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def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true",
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"Enable the fres instruction">;
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def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
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"Enable the frsqrte instruction">;
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def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
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"Enable the frsqrtes instruction">;
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def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
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"Assume higher precision reciprocal estimates">;
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2006-02-28 07:08:22 +00:00
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def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
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2011-10-14 18:54:13 +00:00
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"Enable the stfiwx instruction">;
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2013-03-31 10:12:51 +00:00
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def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
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"Enable the lfiwax instruction">;
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2013-03-29 08:57:48 +00:00
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def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true",
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"Enable the fri[mnpz] instructions">;
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2013-04-01 17:52:07 +00:00
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def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
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"Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
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2012-06-22 23:10:08 +00:00
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def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
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"Enable the isel instruction">;
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2013-03-28 13:29:47 +00:00
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def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
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"Enable the popcnt[dw] instructions">;
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2013-03-28 19:25:55 +00:00
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def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true",
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"Enable the ldbrx instruction">;
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2011-10-17 04:03:49 +00:00
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def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
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"Enable Book E instructions">;
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2013-01-30 21:17:42 +00:00
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def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
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"Enable QPX instructions">;
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2013-10-16 20:38:58 +00:00
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def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true",
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[PowerPC] Initial support for the VSX instruction set
VSX is an ISA extension supported on the POWER7 and later cores that enhances
floating-point vector and scalar capabilities. Among other things, this adds
<2 x double> support and generally helps to reduce register pressure.
The interesting part of this ISA feature is the register configuration: there
are 64 new 128-bit vector registers, the 32 of which are super-registers of the
existing 32 scalar floating-point registers, and the second 32 of which overlap
with the 32 Altivec vector registers. This makes things like vector insertion
and extraction tricky: this can be free but only if we force a restriction to
the right register subclass when needed. A new "minipass" PPCVSXCopy takes care
of this (although it could do a more-optimal job of it; see the comment about
unnecessary copies below).
Please note that, currently, VSX is not enabled by default when targeting
anything because it is not yet ready for that. The assembler and disassembler
are fully implemented and tested. However:
- CodeGen support causes miscompiles; test-suite runtime failures:
MultiSource/Benchmarks/FreeBench/distray/distray
MultiSource/Benchmarks/McCat/08-main/main
MultiSource/Benchmarks/Olden/voronoi/voronoi
MultiSource/Benchmarks/mafft/pairlocalalign
MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4
SingleSource/Benchmarks/CoyoteBench/almabench
SingleSource/Benchmarks/Misc/matmul_f64_4x4
- The lowering currently falls back to using Altivec instructions far more
than it should. Worse, there are some things that are scalarized through the
stack that shouldn't be.
- A lot of unnecessary copies make it past the optimizers, and this needs to
be fixed.
- Many more regression tests are needed.
Normally, I'd fix these things prior to committing, but there are some
students and other contributors who would like to work this, and so it makes
sense to move this development process upstream where it can be subject to the
regular code-review procedures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203768 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-13 07:58:58 +00:00
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"Enable VSX instructions",
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[FeatureAltivec]>;
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2005-10-19 19:51:16 +00:00
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2013-09-12 14:40:06 +00:00
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def DeprecatedMFTB : SubtargetFeature<"", "DeprecatedMFTB", "true",
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"Treat mftb as deprecated">;
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def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true",
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"Treat vector data stream cache control instructions as deprecated">;
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2013-02-01 23:10:09 +00:00
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// Note: Future features to add when support is extended to more
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// recent ISA levels:
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//
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// CMPB p6, p6x, p7 cmpb
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// DFP p6, p6x, p7 decimal floating-point instructions
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// POPCNTB p5 through p7 popcntb and related instructions
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// VSX p7 vector-scalar instruction set
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2013-04-12 02:18:09 +00:00
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//===----------------------------------------------------------------------===//
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// Classes used for relation maps.
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//===----------------------------------------------------------------------===//
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// RecFormRel - Filter class used to relate non-record-form instructions with
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// their record-form variants.
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class RecFormRel;
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2014-03-25 18:55:11 +00:00
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// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
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// FMA instruction forms with their corresponding factor-killing forms.
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class AltVSXFMARel {
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bit IsVSXFMAAlt = 0;
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}
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2013-04-12 02:18:09 +00:00
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//===----------------------------------------------------------------------===//
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// Relation Map Definitions.
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//===----------------------------------------------------------------------===//
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def getRecordFormOpcode : InstrMapping {
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let FilterClass = "RecFormRel";
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// Instructions with the same BaseName and Interpretation64Bit values
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// form a row.
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let RowFields = ["BaseName", "Interpretation64Bit"];
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// Instructions with the same RC value form a column.
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let ColFields = ["RC"];
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// The key column are the non-record-form instructions.
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let KeyCol = ["0"];
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// Value columns RC=1
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let ValueCols = [["1"]];
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}
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def getNonRecordFormOpcode : InstrMapping {
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let FilterClass = "RecFormRel";
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// Instructions with the same BaseName and Interpretation64Bit values
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// form a row.
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let RowFields = ["BaseName", "Interpretation64Bit"];
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// Instructions with the same RC value form a column.
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let ColFields = ["RC"];
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// The key column are the record-form instructions.
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let KeyCol = ["1"];
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// Value columns are RC=0
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let ValueCols = [["0"]];
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}
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2014-03-25 18:55:11 +00:00
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def getAltVSXFMAOpcode : InstrMapping {
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let FilterClass = "AltVSXFMARel";
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// Instructions with the same BaseName and Interpretation64Bit values
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// form a row.
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let RowFields = ["BaseName"];
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// Instructions with the same RC value form a column.
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let ColFields = ["IsVSXFMAAlt"];
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// The key column are the (default) addend-killing instructions.
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let KeyCol = ["0"];
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// Value columns IsVSXFMAAlt=1
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let ValueCols = [["1"]];
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}
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2005-10-19 19:51:16 +00:00
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//===----------------------------------------------------------------------===//
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2005-10-23 22:08:13 +00:00
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "PPCRegisterInfo.td"
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include "PPCSchedule.td"
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include "PPCInstrInfo.td"
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//===----------------------------------------------------------------------===//
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// PowerPC processors supported.
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2005-10-19 19:51:16 +00:00
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//
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2006-12-12 20:57:08 +00:00
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def : Processor<"generic", G3Itineraries, [Directive32]>;
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2013-11-29 06:32:17 +00:00
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def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
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FeatureFRES, FeatureFRSQRTE,
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FeatureBookE, DeprecatedMFTB]>;
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def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
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FeatureFRES, FeatureFRSQRTE,
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FeatureBookE, DeprecatedMFTB]>;
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2006-12-12 20:57:08 +00:00
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def : Processor<"601", G3Itineraries, [Directive601]>;
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def : Processor<"602", G3Itineraries, [Directive602]>;
|
2013-04-03 04:01:11 +00:00
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def : Processor<"603", G3Itineraries, [Directive603,
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FeatureFRES, FeatureFRSQRTE]>;
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def : Processor<"603e", G3Itineraries, [Directive603,
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FeatureFRES, FeatureFRSQRTE]>;
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def : Processor<"603ev", G3Itineraries, [Directive603,
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FeatureFRES, FeatureFRSQRTE]>;
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def : Processor<"604", G3Itineraries, [Directive604,
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FeatureFRES, FeatureFRSQRTE]>;
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def : Processor<"604e", G3Itineraries, [Directive604,
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FeatureFRES, FeatureFRSQRTE]>;
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def : Processor<"620", G3Itineraries, [Directive620,
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FeatureFRES, FeatureFRSQRTE]>;
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def : Processor<"750", G4Itineraries, [Directive750,
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FeatureFRES, FeatureFRSQRTE]>;
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def : Processor<"g3", G3Itineraries, [Directive750,
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FeatureFRES, FeatureFRSQRTE]>;
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def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
|
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|
|
|
FeatureFRES, FeatureFRSQRTE]>;
|
|
|
|
|
def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
|
|
|
|
|
FeatureFRES, FeatureFRSQRTE]>;
|
|
|
|
|
def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
|
|
|
|
|
FeatureFRES, FeatureFRSQRTE]>;
|
|
|
|
|
def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
|
|
|
|
|
FeatureFRES, FeatureFRSQRTE]>;
|
2013-04-05 05:49:18 +00:00
|
|
|
def : ProcessorModel<"970", G5Model,
|
2006-12-12 20:57:08 +00:00
|
|
|
[Directive970, FeatureAltivec,
|
2013-04-03 04:01:11 +00:00
|
|
|
FeatureMFOCRF, FeatureFSqrt,
|
|
|
|
|
FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
|
2005-10-22 08:04:24 +00:00
|
|
|
Feature64Bit /*, Feature64BitRegs */]>;
|
2013-04-05 05:49:18 +00:00
|
|
|
def : ProcessorModel<"g5", G5Model,
|
2006-12-12 20:57:08 +00:00
|
|
|
[Directive970, FeatureAltivec,
|
2012-06-11 19:57:01 +00:00
|
|
|
FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
|
2013-04-03 04:01:11 +00:00
|
|
|
FeatureFRES, FeatureFRSQRTE,
|
2013-09-12 14:40:06 +00:00
|
|
|
Feature64Bit /*, Feature64BitRegs */,
|
|
|
|
|
DeprecatedMFTB, DeprecatedDST]>;
|
2012-08-28 16:12:39 +00:00
|
|
|
def : ProcessorModel<"e500mc", PPCE500mcModel,
|
|
|
|
|
[DirectiveE500mc, FeatureMFOCRF,
|
2013-09-12 14:40:06 +00:00
|
|
|
FeatureSTFIWX, FeatureBookE, FeatureISEL,
|
|
|
|
|
DeprecatedMFTB]>;
|
2012-08-28 16:12:39 +00:00
|
|
|
def : ProcessorModel<"e5500", PPCE5500Model,
|
|
|
|
|
[DirectiveE5500, FeatureMFOCRF, Feature64Bit,
|
2013-09-12 14:40:06 +00:00
|
|
|
FeatureSTFIWX, FeatureBookE, FeatureISEL,
|
|
|
|
|
DeprecatedMFTB]>;
|
2013-04-05 05:34:08 +00:00
|
|
|
def : ProcessorModel<"a2", PPCA2Model,
|
2013-03-28 19:25:55 +00:00
|
|
|
[DirectiveA2, FeatureBookE, FeatureMFOCRF,
|
2013-08-19 05:01:02 +00:00
|
|
|
FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
|
2013-04-03 04:01:11 +00:00
|
|
|
FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
|
|
|
|
|
FeatureSTFIWX, FeatureLFIWAX,
|
2013-04-01 17:52:07 +00:00
|
|
|
FeatureFPRND, FeatureFPCVT, FeatureISEL,
|
|
|
|
|
FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
|
2013-09-12 14:40:06 +00:00
|
|
|
/*, Feature64BitRegs */, DeprecatedMFTB]>;
|
2013-04-05 05:34:08 +00:00
|
|
|
def : ProcessorModel<"a2q", PPCA2Model,
|
2013-03-28 19:25:55 +00:00
|
|
|
[DirectiveA2, FeatureBookE, FeatureMFOCRF,
|
2013-08-19 05:01:02 +00:00
|
|
|
FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
|
2013-04-03 04:01:11 +00:00
|
|
|
FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
|
|
|
|
|
FeatureSTFIWX, FeatureLFIWAX,
|
2013-04-01 17:52:07 +00:00
|
|
|
FeatureFPRND, FeatureFPCVT, FeatureISEL,
|
|
|
|
|
FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
|
2013-09-12 14:40:06 +00:00
|
|
|
/*, Feature64BitRegs */, FeatureQPX, DeprecatedMFTB]>;
|
2013-04-05 05:49:18 +00:00
|
|
|
def : ProcessorModel<"pwr3", G5Model,
|
2013-04-03 04:01:11 +00:00
|
|
|
[DirectivePwr3, FeatureAltivec,
|
|
|
|
|
FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
|
2013-02-01 22:59:51 +00:00
|
|
|
FeatureSTFIWX, Feature64Bit]>;
|
2013-04-05 05:49:18 +00:00
|
|
|
def : ProcessorModel<"pwr4", G5Model,
|
2013-02-01 22:59:51 +00:00
|
|
|
[DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
|
2013-04-03 04:01:11 +00:00
|
|
|
FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
|
|
|
|
|
FeatureSTFIWX, Feature64Bit]>;
|
2013-04-05 05:49:18 +00:00
|
|
|
def : ProcessorModel<"pwr5", G5Model,
|
2013-02-01 22:59:51 +00:00
|
|
|
[DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
|
2013-04-03 04:01:11 +00:00
|
|
|
FeatureFSqrt, FeatureFRE, FeatureFRES,
|
|
|
|
|
FeatureFRSQRTE, FeatureFRSQRTES,
|
2013-09-12 14:40:06 +00:00
|
|
|
FeatureSTFIWX, Feature64Bit,
|
|
|
|
|
DeprecatedMFTB, DeprecatedDST]>;
|
2013-04-05 05:49:18 +00:00
|
|
|
def : ProcessorModel<"pwr5x", G5Model,
|
2013-02-01 22:59:51 +00:00
|
|
|
[DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
|
2013-04-03 04:01:11 +00:00
|
|
|
FeatureFSqrt, FeatureFRE, FeatureFRES,
|
|
|
|
|
FeatureFRSQRTE, FeatureFRSQRTES,
|
2013-09-12 14:40:06 +00:00
|
|
|
FeatureSTFIWX, FeatureFPRND, Feature64Bit,
|
|
|
|
|
DeprecatedMFTB, DeprecatedDST]>;
|
2013-04-05 05:49:18 +00:00
|
|
|
def : ProcessorModel<"pwr6", G5Model,
|
2012-06-11 15:43:08 +00:00
|
|
|
[DirectivePwr6, FeatureAltivec,
|
2013-08-19 05:01:02 +00:00
|
|
|
FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
|
2013-04-03 04:01:11 +00:00
|
|
|
FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
|
|
|
|
|
FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
|
2013-09-12 14:40:06 +00:00
|
|
|
FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
|
|
|
|
|
DeprecatedMFTB, DeprecatedDST]>;
|
2013-04-05 05:49:18 +00:00
|
|
|
def : ProcessorModel<"pwr6x", G5Model,
|
2013-02-01 22:59:51 +00:00
|
|
|
[DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
|
2013-08-19 05:01:02 +00:00
|
|
|
FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
|
2013-04-03 04:01:11 +00:00
|
|
|
FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
|
|
|
|
|
FeatureSTFIWX, FeatureLFIWAX,
|
2013-09-12 14:40:06 +00:00
|
|
|
FeatureFPRND, Feature64Bit,
|
|
|
|
|
DeprecatedMFTB, DeprecatedDST]>;
|
Add a scheduling model (with itinerary) for the PPC POWER7
This adds a scheduling model for the POWER7 (P7) core, and enables the
machine-instruction scheduler when targeting the P7. Scheduling for the P7,
like earlier ooo PPC cores, requires considering both dispatch group hazards,
and functional unit resources and latencies. These are both modeled in a
combined itinerary. Dispatch group formation is still handled by the post-RA
scheduler (which still needs to be updated for the P7, but nevertheless does a
pretty good job).
One interesting aspect of this change is that I've also enabled to use of AA
duing CodeGen for the P7 (just as it is for the embedded cores). The benchmark
results seem to support this decision (see below), and while this is normally
useful for in-order cores, and not for ooo cores like the P7, I think that the
dispatch slot hazards are enough like in-order resources to make the AA useful.
Test suite significant performance differences (where negative is a speedup,
and positive is a regression) vs. the current situation:
MultiSource/Benchmarks/BitBench/drop3/drop3
with AA: N/A
without AA: -28.7614% +/- 19.8356%
(significantly against AA)
MultiSource/Benchmarks/FreeBench/neural/neural
with AA: -17.7406% +/- 11.2712%
without AA: N/A
(significantly in favor of AA)
MultiSource/Benchmarks/SciMark2-C/scimark2
with AA: -11.2079% +/- 1.80543%
without AA: -11.3263% +/- 2.79651%
MultiSource/Benchmarks/TSVC/Symbolics-flt/Symbolics-flt
with AA: -41.8649% +/- 17.0053%
without AA: -34.5256% +/- 23.7072%
MultiSource/Benchmarks/mafft/pairlocalalign
with AA: 25.3016% +/- 17.8614%
without AA: 38.6629% +/- 14.9391%
(significantly in favor of AA)
MultiSource/Benchmarks/sim/sim
with AA: N/A
without AA: 13.4844% +/- 7.18195%
(significantly in favor of AA)
SingleSource/Benchmarks/BenchmarkGame/Large/fasta
with AA: 15.0664% +/- 6.70216%
without AA: 12.7747% +/- 8.43043%
SingleSource/Benchmarks/BenchmarkGame/puzzle
with AA: 82.2713% +/- 26.3567%
without AA: 75.7525% +/- 41.1842%
SingleSource/Benchmarks/Misc/flops-2
with AA: -37.1621% +/- 20.7964%
without AA: -35.2342% +/- 20.2999%
(significantly in favor of AA)
These are 99.5% confidence intervals from 5 runs per configuration. Regarding
the choice to turn on AA during CodeGen, of these results, four seem
significantly in favor of using AA, and one seems significantly against. I'm
not making this decision based on these numbers alone, but these results
seem consistent with results I have from other tests, and so I think that, on
balance, using AA is a win.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195981 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-30 20:55:12 +00:00
|
|
|
def : ProcessorModel<"pwr7", P7Model,
|
2012-06-11 15:43:08 +00:00
|
|
|
[DirectivePwr7, FeatureAltivec,
|
2013-08-19 05:01:02 +00:00
|
|
|
FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
|
2013-04-03 04:01:11 +00:00
|
|
|
FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
|
|
|
|
|
FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
|
|
|
|
|
FeatureFPRND, FeatureFPCVT, FeatureISEL,
|
|
|
|
|
FeaturePOPCNTD, FeatureLDBRX,
|
2013-09-12 14:40:06 +00:00
|
|
|
Feature64Bit /*, Feature64BitRegs */,
|
|
|
|
|
DeprecatedMFTB, DeprecatedDST]>;
|
2006-12-12 20:57:08 +00:00
|
|
|
def : Processor<"ppc", G3Itineraries, [Directive32]>;
|
2013-04-05 05:49:18 +00:00
|
|
|
def : ProcessorModel<"ppc64", G5Model,
|
2006-12-12 20:57:08 +00:00
|
|
|
[Directive64, FeatureAltivec,
|
2013-04-03 14:40:18 +00:00
|
|
|
FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
|
|
|
|
|
FeatureFRSQRTE, FeatureSTFIWX,
|
2005-10-22 08:04:24 +00:00
|
|
|
Feature64Bit /*, Feature64BitRegs */]>;
|
2013-07-26 01:35:43 +00:00
|
|
|
def : ProcessorModel<"ppc64le", G5Model,
|
|
|
|
|
[Directive64, FeatureAltivec,
|
|
|
|
|
FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
|
|
|
|
|
FeatureFRSQRTE, FeatureSTFIWX,
|
|
|
|
|
Feature64Bit /*, Feature64BitRegs */]>;
|
2005-10-19 19:51:16 +00:00
|
|
|
|
2007-03-06 00:59:59 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Calling Conventions
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
|
|
include "PPCCallingConv.td"
|
|
|
|
|
|
2006-03-12 09:13:49 +00:00
|
|
|
def PPCInstrInfo : InstrInfo {
|
|
|
|
|
let isLittleEndianEncoding = 1;
|
2013-12-19 16:13:01 +00:00
|
|
|
|
|
|
|
|
// FIXME: Unset this when no longer needed!
|
|
|
|
|
let decodePositionallyEncodedOperands = 1;
|
[TableGen] Optionally forbid overlap between named and positional operands
There are currently two schemes for mapping instruction operands to
instruction-format variables for generating the instruction encoders and
decoders for the assembler and disassembler respectively: a) to map by name and
b) to map by position.
In the long run, we'd like to remove the position-based scheme and use only
name-based mapping. Unfortunately, the name-based scheme currently cannot deal
with complex operands (those with suboperands), and so we currently must use
the position-based scheme for those. On the other hand, the position-based
scheme cannot deal with (register) variables that are split into multiple
ranges. An upcoming commit to the PowerPC backend (adding VSX support) will
require this capability. While we could teach the position-based scheme to
handle that, since we'd like to move away from the position-based mapping
generally, it seems silly to teach it new tricks now. What makes more sense is
to allow for partial transitioning: use the name-based mapping when possible,
and only use the position-based scheme when necessary.
Now the problem is that mixing the two sensibly was not possible: the
position-based mapping would map based on position, but would not skip those
variables that were mapped by name. Instead, the two sets of assignments would
overlap. However, I cannot currently change the current behavior, because there
are some backends that rely on it [I think mistakenly, but I'll send a message
to llvmdev about that]. So I've added a new TableGen bit variable:
noNamedPositionallyEncodedOperands, that can be used to cause the
position-based mapping to skip variables mapped by name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203767 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-13 07:57:54 +00:00
|
|
|
|
|
|
|
|
let noNamedPositionallyEncodedOperands = 1;
|
2006-03-12 09:13:49 +00:00
|
|
|
}
|
|
|
|
|
|
2013-05-03 19:49:39 +00:00
|
|
|
def PPCAsmParser : AsmParser {
|
|
|
|
|
let ShouldEmitMatchRegisterName = 0;
|
|
|
|
|
}
|
|
|
|
|
|
2013-07-08 14:49:37 +00:00
|
|
|
def PPCAsmParserVariant : AsmParserVariant {
|
|
|
|
|
int Variant = 0;
|
|
|
|
|
|
|
|
|
|
// We do not use hard coded registers in asm strings. However, some
|
|
|
|
|
// InstAlias definitions use immediate literals. Set RegisterPrefix
|
|
|
|
|
// so that those are not misinterpreted as registers.
|
|
|
|
|
string RegisterPrefix = "%";
|
|
|
|
|
}
|
|
|
|
|
|
2005-10-14 23:37:35 +00:00
|
|
|
def PPC : Target {
|
2006-03-12 09:13:49 +00:00
|
|
|
// Information about the instructions.
|
|
|
|
|
let InstructionSet = PPCInstrInfo;
|
2013-12-02 04:55:42 +00:00
|
|
|
|
2013-05-03 19:49:39 +00:00
|
|
|
let AssemblyParsers = [PPCAsmParser];
|
2013-07-08 14:49:37 +00:00
|
|
|
let AssemblyParserVariants = [PPCAsmParserVariant];
|
2005-10-14 23:37:35 +00:00
|
|
|
}
|
