2009-10-19 20:20:46 +00:00
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//===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
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//
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2006-05-14 22:18:28 +00:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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2006-05-14 22:18:28 +00:00
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to GAS-format ARM assembly language.
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//
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//===----------------------------------------------------------------------===//
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2006-12-19 22:59:26 +00:00
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#define DEBUG_TYPE "asm-printer"
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2006-05-14 22:18:28 +00:00
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#include "ARM.h"
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2009-05-23 19:51:20 +00:00
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#include "ARMBuildAttrs.h"
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2007-01-19 07:51:42 +00:00
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#include "ARMAddressingModes.h"
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#include "ARMConstantPoolValue.h"
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2010-10-01 22:39:28 +00:00
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#include "InstPrinter/ARMInstPrinter.h"
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2009-10-19 20:20:46 +00:00
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#include "ARMMachineFunctionInfo.h"
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#include "ARMMCInstLower.h"
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#include "ARMTargetMachine.h"
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2010-10-11 23:01:44 +00:00
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#include "ARMTargetObjectFile.h"
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2010-04-26 20:07:31 +00:00
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#include "llvm/Analysis/DebugInfo.h"
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2006-05-14 22:18:28 +00:00
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#include "llvm/Constants.h"
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#include "llvm/Module.h"
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2009-12-28 12:27:56 +00:00
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#include "llvm/Type.h"
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2009-08-13 01:36:44 +00:00
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#include "llvm/Assembly/Writer.h"
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2006-05-14 22:18:28 +00:00
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#include "llvm/CodeGen/AsmPrinter.h"
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2009-10-19 18:38:33 +00:00
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#include "llvm/CodeGen/MachineModuleInfoImpls.h"
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2006-05-14 22:18:28 +00:00
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#include "llvm/CodeGen/MachineFunctionPass.h"
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2007-01-19 07:51:42 +00:00
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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2009-10-19 18:38:33 +00:00
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#include "llvm/MC/MCAsmInfo.h"
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2010-10-25 17:50:35 +00:00
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#include "llvm/MC/MCAssembler.h"
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2009-10-19 18:38:33 +00:00
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#include "llvm/MC/MCContext.h"
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2010-03-09 00:40:17 +00:00
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#include "llvm/MC/MCExpr.h"
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2009-10-19 20:20:46 +00:00
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#include "llvm/MC/MCInst.h"
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2009-08-10 18:15:01 +00:00
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#include "llvm/MC/MCSectionMachO.h"
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2010-10-25 17:50:35 +00:00
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#include "llvm/MC/MCObjectStreamer.h"
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2009-08-19 05:49:37 +00:00
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#include "llvm/MC/MCStreamer.h"
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2009-09-13 17:14:04 +00:00
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#include "llvm/MC/MCSymbol.h"
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2010-03-12 21:19:23 +00:00
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#include "llvm/Target/Mangler.h"
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2006-07-27 11:38:51 +00:00
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#include "llvm/Target/TargetData.h"
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2006-05-14 22:18:28 +00:00
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#include "llvm/Target/TargetMachine.h"
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2007-01-19 19:25:36 +00:00
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#include "llvm/Target/TargetOptions.h"
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2009-07-15 20:24:03 +00:00
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#include "llvm/Target/TargetRegistry.h"
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2009-07-24 18:19:46 +00:00
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#include "llvm/ADT/SmallPtrSet.h"
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2009-09-01 18:49:12 +00:00
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#include "llvm/ADT/SmallString.h"
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2009-11-06 23:33:28 +00:00
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#include "llvm/ADT/StringExtras.h"
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2009-10-19 20:20:46 +00:00
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#include "llvm/Support/CommandLine.h"
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2010-08-04 22:39:39 +00:00
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#include "llvm/Support/Debug.h"
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2009-07-08 20:55:50 +00:00
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#include "llvm/Support/ErrorHandling.h"
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2010-04-04 08:18:47 +00:00
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#include "llvm/Support/raw_ostream.h"
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2006-05-14 22:18:28 +00:00
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#include <cctype>
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using namespace llvm;
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2010-07-21 23:03:52 +00:00
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namespace llvm {
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namespace ARM {
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enum DW_ISA {
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DW_ISA_ARM_thumb = 1,
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DW_ISA_ARM_arm = 2
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};
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}
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}
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2006-12-19 22:59:26 +00:00
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namespace {
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2010-10-25 17:50:35 +00:00
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// Per section and per symbol attributes are not supported.
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// To implement them we would need the ability to delay this emission
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// until the assembly file is fully parsed/generated as only then do we
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// know the symbol and section numbers.
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class AttributeEmitter {
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public:
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virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
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virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
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virtual void Finish() = 0;
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2010-10-25 18:38:32 +00:00
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virtual ~AttributeEmitter() {}
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2010-10-25 17:50:35 +00:00
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};
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class AsmAttributeEmitter : public AttributeEmitter {
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MCStreamer &Streamer;
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public:
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AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
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void MaybeSwitchVendor(StringRef Vendor) { }
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void EmitAttribute(unsigned Attribute, unsigned Value) {
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Streamer.EmitRawText("\t.eabi_attribute " +
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Twine(Attribute) + ", " + Twine(Value));
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}
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void Finish() { }
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};
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class ObjectAttributeEmitter : public AttributeEmitter {
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MCObjectStreamer &Streamer;
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size_t SectionStart;
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size_t TagStart;
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StringRef CurrentVendor;
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SmallString<64> Contents;
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public:
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ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
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Streamer(Streamer_), CurrentVendor("") { }
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void MaybeSwitchVendor(StringRef Vendor) {
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assert(!Vendor.empty() && "Vendor cannot be empty.");
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if (CurrentVendor.empty())
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CurrentVendor = Vendor;
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else if (CurrentVendor == Vendor)
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return;
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else
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Finish();
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CurrentVendor = Vendor;
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SectionStart = Contents.size();
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// Length of the data for this vendor.
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Contents.append(4, (char)0);
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Contents.append(Vendor.begin(), Vendor.end());
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Contents += 0;
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Contents += ARMBuildAttrs::File;
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TagStart = Contents.size();
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// Length of the data for this tag.
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Contents.append(4, (char)0);
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}
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void EmitAttribute(unsigned Attribute, unsigned Value) {
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// FIXME: should be ULEB
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Contents += Attribute;
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Contents += Value;
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}
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void Finish() {
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size_t EndPos = Contents.size();
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// FIXME: endian.
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*((uint32_t*)&Contents[SectionStart]) = EndPos - SectionStart;
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// +1 since it includes the tag that came before it.
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*((uint32_t*)&Contents[TagStart]) = EndPos - TagStart + 1;
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Streamer.EmitBytes(Contents, 0);
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}
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};
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2009-10-19 17:59:19 +00:00
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class ARMAsmPrinter : public AsmPrinter {
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2007-01-19 07:51:42 +00:00
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/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
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/// make the right decision when printing asm code for different targets.
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const ARMSubtarget *Subtarget;
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/// AFI - Keep a pointer to ARMFunctionInfo for the current
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2008-09-18 07:27:23 +00:00
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/// MachineFunction.
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2007-01-19 07:51:42 +00:00
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ARMFunctionInfo *AFI;
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2008-09-18 07:27:23 +00:00
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/// MCP - Keep a pointer to constantpool entries of the current
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/// MachineFunction.
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const MachineConstantPool *MCP;
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2009-02-24 08:30:20 +00:00
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public:
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2010-04-04 08:18:47 +00:00
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explicit ARMAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
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: AsmPrinter(TM, Streamer), AFI(NULL), MCP(NULL) {
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2009-02-24 08:30:20 +00:00
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Subtarget = &TM.getSubtarget<ARMSubtarget>();
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}
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2006-05-14 22:18:28 +00:00
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virtual const char *getPassName() const {
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return "ARM Assembly Printer";
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}
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2010-09-02 01:02:06 +00:00
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2010-04-04 04:47:45 +00:00
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void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
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2007-01-19 07:51:42 +00:00
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const char *Modifier = 0);
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2009-11-06 23:33:28 +00:00
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2009-06-29 07:51:04 +00:00
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virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
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2010-04-04 05:29:35 +00:00
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unsigned AsmVariant, const char *ExtraCode,
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raw_ostream &O);
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2009-06-29 07:51:04 +00:00
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virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
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2009-05-19 05:53:42 +00:00
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unsigned AsmVariant,
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2010-04-04 05:29:35 +00:00
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const char *ExtraCode, raw_ostream &O);
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2006-05-14 22:18:28 +00:00
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2010-09-30 01:57:53 +00:00
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void EmitJumpTable(const MachineInstr *MI);
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void EmitJump2Table(const MachineInstr *MI);
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2010-01-28 01:10:34 +00:00
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virtual void EmitInstruction(const MachineInstr *MI);
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2006-05-14 22:18:28 +00:00
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bool runOnMachineFunction(MachineFunction &F);
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2010-09-02 01:02:06 +00:00
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2010-01-28 00:19:24 +00:00
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virtual void EmitConstantPool() {} // we emit constant pools customly!
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2010-01-27 23:58:11 +00:00
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virtual void EmitFunctionEntryLabel();
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2009-09-30 22:06:26 +00:00
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void EmitStartOfAsmFile(Module &M);
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2009-10-19 17:59:19 +00:00
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void EmitEndOfAsmFile(Module &M);
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2007-01-19 07:51:42 +00:00
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2010-10-06 22:36:46 +00:00
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private:
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// Helpers for EmitStartOfAsmFile() and EmitEndOfAsmFile()
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void emitAttributes();
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2010-10-11 23:01:44 +00:00
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// Helper for ELF .o only
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void emitARMAttributeSection();
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2010-10-06 22:36:46 +00:00
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public:
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2010-09-28 17:05:56 +00:00
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void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
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2010-08-04 22:39:39 +00:00
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MachineLocation getDebugValueLocation(const MachineInstr *MI) const {
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MachineLocation Location;
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assert (MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
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// Frame address. Currently handles register +- offset only.
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if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
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Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
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else {
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DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
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}
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return Location;
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}
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2010-07-21 23:03:52 +00:00
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virtual unsigned getISAEncoding() {
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// ARM/Darwin adds ISA to the DWARF info for each function.
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if (!Subtarget->isTargetDarwin())
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return 0;
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return Subtarget->isThumb() ?
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llvm::ARM::DW_ISA_ARM_thumb : llvm::ARM::DW_ISA_ARM_arm;
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}
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2010-01-25 19:51:38 +00:00
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MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
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const MachineBasicBlock *MBB) const;
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MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
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2010-01-25 19:39:52 +00:00
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2010-09-24 20:47:58 +00:00
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MCSymbol *GetARMSJLJEHLabel(void) const;
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2008-08-08 06:56:16 +00:00
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/// EmitMachineConstantPoolValue - Print a machine constantpool value to
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/// the .s file.
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2007-01-19 07:51:42 +00:00
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virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
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2010-04-04 07:05:53 +00:00
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SmallString<128> Str;
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raw_svector_ostream OS(Str);
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EmitMachineConstantPoolValue(MCPV, OS);
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OutStreamer.EmitRawText(OS.str());
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}
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2010-09-02 01:02:06 +00:00
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2010-04-04 07:05:53 +00:00
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void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV,
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raw_ostream &O) {
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2010-01-20 07:33:29 +00:00
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switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
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case 1: O << MAI->getData8bitsDirective(0); break;
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case 2: O << MAI->getData16bitsDirective(0); break;
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case 4: O << MAI->getData32bitsDirective(0); break;
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default: assert(0 && "Unknown CPV size");
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}
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2007-01-19 07:51:42 +00:00
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2008-08-08 06:56:16 +00:00
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ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
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2009-09-01 01:57:56 +00:00
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if (ACPV->isLSDA()) {
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2010-04-04 07:05:53 +00:00
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O << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
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2009-11-02 16:59:06 +00:00
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} else if (ACPV->isBlockAddress()) {
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2010-04-05 16:32:14 +00:00
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O << *GetBlockAddressSymbol(ACPV->getBlockAddress());
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2009-11-02 16:59:06 +00:00
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} else if (ACPV->isGlobalValue()) {
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2010-04-15 01:51:59 +00:00
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const GlobalValue *GV = ACPV->getGV();
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2009-08-28 23:18:09 +00:00
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bool isIndirect = Subtarget->isTargetDarwin() &&
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2009-09-03 07:04:02 +00:00
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Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
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2009-08-28 23:18:09 +00:00
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if (!isIndirect)
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2010-03-12 21:19:23 +00:00
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O << *Mang->getSymbol(GV);
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2009-08-28 23:18:09 +00:00
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else {
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// FIXME: Remove this when Darwin transition to @GOT like syntax.
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2010-01-16 18:37:32 +00:00
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MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
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2010-01-17 21:43:43 +00:00
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O << *Sym;
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2010-09-02 01:02:06 +00:00
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2009-10-19 18:49:14 +00:00
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MachineModuleInfoMachO &MMIMachO =
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MMI->getObjFileInfo<MachineModuleInfoMachO>();
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2010-03-10 22:34:10 +00:00
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MachineModuleInfoImpl::StubValueTy &StubSym =
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2009-10-19 18:49:14 +00:00
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GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
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MMIMachO.getGVStubEntry(Sym);
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2010-03-10 22:34:10 +00:00
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if (StubSym.getPointer() == 0)
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StubSym = MachineModuleInfoImpl::
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2010-03-12 21:19:23 +00:00
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StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
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2009-08-28 23:18:09 +00:00
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}
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2009-11-02 16:59:06 +00:00
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} else {
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assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
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2010-01-17 21:43:43 +00:00
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O << *GetExternalSymbolSymbol(ACPV->getSymbol());
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2009-11-02 16:59:06 +00:00
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}
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2009-09-04 01:38:51 +00:00
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2007-04-22 00:04:12 +00:00
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|
|
if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
|
2007-04-27 13:54:47 +00:00
|
|
|
if (ACPV->getPCAdjustment() != 0) {
|
2009-08-22 21:43:10 +00:00
|
|
|
O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
|
2009-11-06 22:24:13 +00:00
|
|
|
<< getFunctionNumber() << "_" << ACPV->getLabelId()
|
2007-04-27 13:54:47 +00:00
|
|
|
<< "+" << (unsigned)ACPV->getPCAdjustment();
|
|
|
|
if (ACPV->mustAddCurrentAddress())
|
|
|
|
O << "-.";
|
2010-01-15 23:26:49 +00:00
|
|
|
O << ')';
|
2007-04-27 13:54:47 +00:00
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
2006-05-14 22:18:28 +00:00
|
|
|
};
|
|
|
|
} // end of anonymous namespace
|
|
|
|
|
2010-01-27 23:58:11 +00:00
|
|
|
void ARMAsmPrinter::EmitFunctionEntryLabel() {
|
|
|
|
if (AFI->isThumbFunction()) {
|
2010-04-04 07:05:53 +00:00
|
|
|
OutStreamer.EmitRawText(StringRef("\t.code\t16"));
|
2010-04-05 16:32:14 +00:00
|
|
|
if (!Subtarget->isTargetDarwin())
|
2010-04-04 07:05:53 +00:00
|
|
|
OutStreamer.EmitRawText(StringRef("\t.thumb_func"));
|
2010-04-05 16:32:14 +00:00
|
|
|
else {
|
|
|
|
// This needs to emit to a temporary string to get properly quoted
|
|
|
|
// MCSymbols when they have spaces in them.
|
|
|
|
SmallString<128> Tmp;
|
|
|
|
raw_svector_ostream OS(Tmp);
|
|
|
|
OS << "\t.thumb_func\t" << *CurrentFnSym;
|
|
|
|
OutStreamer.EmitRawText(OS.str());
|
|
|
|
}
|
2010-01-27 23:58:11 +00:00
|
|
|
}
|
2010-09-02 01:02:06 +00:00
|
|
|
|
2010-01-27 23:58:11 +00:00
|
|
|
OutStreamer.EmitLabel(CurrentFnSym);
|
|
|
|
}
|
|
|
|
|
2010-09-30 01:57:53 +00:00
|
|
|
/// runOnMachineFunction - This uses the EmitInstruction()
|
2006-05-14 22:18:28 +00:00
|
|
|
/// method to print assembly for each instruction.
|
|
|
|
///
|
|
|
|
bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
|
2007-01-19 07:51:42 +00:00
|
|
|
AFI = MF.getInfo<ARMFunctionInfo>();
|
2008-09-18 07:27:23 +00:00
|
|
|
MCP = MF.getConstantPool();
|
2007-01-19 07:51:42 +00:00
|
|
|
|
2010-01-28 01:28:58 +00:00
|
|
|
return AsmPrinter::runOnMachineFunction(MF);
|
2006-10-17 18:04:53 +00:00
|
|
|
}
|
|
|
|
|
2009-06-29 07:51:04 +00:00
|
|
|
void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
|
2010-04-04 04:47:45 +00:00
|
|
|
raw_ostream &O, const char *Modifier) {
|
2009-06-29 07:51:04 +00:00
|
|
|
const MachineOperand &MO = MI->getOperand(OpNum);
|
2009-11-24 00:44:37 +00:00
|
|
|
unsigned TF = MO.getTargetFlags();
|
|
|
|
|
2006-05-25 12:57:06 +00:00
|
|
|
switch (MO.getType()) {
|
2009-10-19 20:59:55 +00:00
|
|
|
default:
|
|
|
|
assert(0 && "<unknown operand type>");
|
2009-06-22 23:27:02 +00:00
|
|
|
case MachineOperand::MO_Register: {
|
|
|
|
unsigned Reg = MO.getReg();
|
2009-10-19 20:59:55 +00:00
|
|
|
assert(TargetRegisterInfo::isPhysicalRegister(Reg));
|
2010-10-06 21:22:32 +00:00
|
|
|
assert(!MO.getSubReg() && "Subregs should be eliminated!");
|
|
|
|
O << ARMInstPrinter::getRegisterName(Reg);
|
2006-05-25 12:57:06 +00:00
|
|
|
break;
|
2009-06-22 23:27:02 +00:00
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
case MachineOperand::MO_Immediate: {
|
2009-09-28 09:14:39 +00:00
|
|
|
int64_t Imm = MO.getImm();
|
2009-10-08 20:43:22 +00:00
|
|
|
O << '#';
|
2009-11-24 00:44:37 +00:00
|
|
|
if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
|
2010-10-06 16:51:55 +00:00
|
|
|
(TF == ARMII::MO_LO16))
|
2009-11-24 00:44:37 +00:00
|
|
|
O << ":lower16:";
|
|
|
|
else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
|
2010-10-06 16:51:55 +00:00
|
|
|
(TF == ARMII::MO_HI16))
|
2009-11-24 00:44:37 +00:00
|
|
|
O << ":upper16:";
|
2009-10-08 20:43:22 +00:00
|
|
|
O << Imm;
|
2006-05-25 12:57:06 +00:00
|
|
|
break;
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
2006-05-25 12:57:06 +00:00
|
|
|
case MachineOperand::MO_MachineBasicBlock:
|
2010-03-13 21:04:28 +00:00
|
|
|
O << *MO.getMBB()->getSymbol();
|
2006-05-25 12:57:06 +00:00
|
|
|
return;
|
2006-07-16 01:02:57 +00:00
|
|
|
case MachineOperand::MO_GlobalAddress: {
|
2010-04-15 01:51:59 +00:00
|
|
|
const GlobalValue *GV = MO.getGlobal();
|
2009-11-24 00:44:37 +00:00
|
|
|
if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
|
|
|
|
(TF & ARMII::MO_LO16))
|
|
|
|
O << ":lower16:";
|
|
|
|
else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
|
|
|
|
(TF & ARMII::MO_HI16))
|
|
|
|
O << ":upper16:";
|
2010-03-12 21:19:23 +00:00
|
|
|
O << *Mang->getSymbol(GV);
|
2008-11-22 16:15:34 +00:00
|
|
|
|
2010-04-03 22:28:33 +00:00
|
|
|
printOffset(MO.getOffset(), O);
|
2010-10-06 21:36:43 +00:00
|
|
|
if (TF == ARMII::MO_PLT)
|
2007-04-22 00:04:12 +00:00
|
|
|
O << "(PLT)";
|
2006-05-25 12:57:06 +00:00
|
|
|
break;
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
case MachineOperand::MO_ExternalSymbol: {
|
2010-01-17 21:43:43 +00:00
|
|
|
O << *GetExternalSymbolSymbol(MO.getSymbolName());
|
2010-10-06 21:36:43 +00:00
|
|
|
if (TF == ARMII::MO_PLT)
|
2007-04-22 00:04:12 +00:00
|
|
|
O << "(PLT)";
|
2006-05-25 12:57:06 +00:00
|
|
|
break;
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
2006-05-25 12:57:06 +00:00
|
|
|
case MachineOperand::MO_ConstantPoolIndex:
|
2010-01-23 07:00:21 +00:00
|
|
|
O << *GetCPISymbol(MO.getIndex());
|
2006-05-25 12:57:06 +00:00
|
|
|
break;
|
2007-01-19 07:51:42 +00:00
|
|
|
case MachineOperand::MO_JumpTableIndex:
|
2010-01-23 07:00:21 +00:00
|
|
|
O << *GetJTISymbol(MO.getIndex());
|
2007-01-19 07:51:42 +00:00
|
|
|
break;
|
2006-05-25 12:57:06 +00:00
|
|
|
}
|
2006-05-14 22:18:28 +00:00
|
|
|
}
|
|
|
|
|
2009-06-29 07:51:04 +00:00
|
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
|
2010-01-25 19:51:38 +00:00
|
|
|
MCSymbol *ARMAsmPrinter::
|
|
|
|
GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
|
|
|
|
const MachineBasicBlock *MBB) const {
|
|
|
|
SmallString<60> Name;
|
|
|
|
raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
|
2010-01-25 19:39:52 +00:00
|
|
|
<< getFunctionNumber() << '_' << uid << '_' << uid2
|
2010-01-25 19:51:38 +00:00
|
|
|
<< "_set_" << MBB->getNumber();
|
2010-03-30 18:10:53 +00:00
|
|
|
return OutContext.GetOrCreateSymbol(Name.str());
|
2010-01-25 19:51:38 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
MCSymbol *ARMAsmPrinter::
|
|
|
|
GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
|
|
|
|
SmallString<60> Name;
|
|
|
|
raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
|
2010-01-25 23:28:03 +00:00
|
|
|
<< getFunctionNumber() << '_' << uid << '_' << uid2;
|
2010-03-30 18:10:53 +00:00
|
|
|
return OutContext.GetOrCreateSymbol(Name.str());
|
2010-01-25 19:39:52 +00:00
|
|
|
}
|
|
|
|
|
2010-09-24 20:47:58 +00:00
|
|
|
|
|
|
|
MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
|
|
|
|
SmallString<60> Name;
|
|
|
|
raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
|
|
|
|
<< getFunctionNumber();
|
|
|
|
return OutContext.GetOrCreateSymbol(Name.str());
|
|
|
|
}
|
|
|
|
|
2009-06-29 07:51:04 +00:00
|
|
|
bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
|
2010-04-04 05:29:35 +00:00
|
|
|
unsigned AsmVariant, const char *ExtraCode,
|
|
|
|
raw_ostream &O) {
|
2007-01-19 07:51:42 +00:00
|
|
|
// Does this asm operand have a single letter operand modifier?
|
|
|
|
if (ExtraCode && ExtraCode[0]) {
|
|
|
|
if (ExtraCode[1] != 0) return true; // Unknown modifier.
|
2009-08-08 23:10:41 +00:00
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
switch (ExtraCode[0]) {
|
|
|
|
default: return true; // Unknown modifier.
|
2009-07-09 23:54:51 +00:00
|
|
|
case 'a': // Print as a memory address.
|
|
|
|
if (MI->getOperand(OpNum).isReg()) {
|
2010-09-30 15:25:22 +00:00
|
|
|
O << "["
|
|
|
|
<< ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
|
|
|
|
<< "]";
|
2009-07-09 23:54:51 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
// Fallthrough
|
|
|
|
case 'c': // Don't print "#" before an immediate operand.
|
2009-08-21 21:58:55 +00:00
|
|
|
if (!MI->getOperand(OpNum).isImm())
|
|
|
|
return true;
|
2010-09-30 01:57:53 +00:00
|
|
|
O << MI->getOperand(OpNum).getImm();
|
2009-04-06 21:46:51 +00:00
|
|
|
return false;
|
2007-04-04 00:13:29 +00:00
|
|
|
case 'P': // Print a VFP double precision register.
|
2009-12-08 23:06:22 +00:00
|
|
|
case 'q': // Print a NEON quad precision register.
|
2010-04-04 04:47:45 +00:00
|
|
|
printOperand(MI, OpNum, O);
|
2007-03-08 22:42:46 +00:00
|
|
|
return false;
|
2007-01-19 07:51:42 +00:00
|
|
|
case 'Q':
|
|
|
|
case 'R':
|
2010-05-27 20:23:42 +00:00
|
|
|
case 'H':
|
2010-05-27 23:45:31 +00:00
|
|
|
report_fatal_error("llvm does not support 'Q', 'R', and 'H' modifiers!");
|
2010-05-27 20:23:42 +00:00
|
|
|
return true;
|
2010-05-27 22:08:38 +00:00
|
|
|
}
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
2009-09-04 01:38:51 +00:00
|
|
|
|
2010-04-04 04:47:45 +00:00
|
|
|
printOperand(MI, OpNum, O);
|
2007-01-19 07:51:42 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2009-05-19 05:53:42 +00:00
|
|
|
bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
|
2009-06-29 07:51:04 +00:00
|
|
|
unsigned OpNum, unsigned AsmVariant,
|
2010-04-04 05:29:35 +00:00
|
|
|
const char *ExtraCode,
|
|
|
|
raw_ostream &O) {
|
2009-05-19 05:53:42 +00:00
|
|
|
if (ExtraCode && ExtraCode[0])
|
|
|
|
return true; // Unknown modifier.
|
2009-10-13 20:50:28 +00:00
|
|
|
|
|
|
|
const MachineOperand &MO = MI->getOperand(OpNum);
|
|
|
|
assert(MO.isReg() && "unexpected inline asm memory operand");
|
2010-09-30 01:57:53 +00:00
|
|
|
O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
|
2009-05-19 05:53:42 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2009-09-30 22:06:26 +00:00
|
|
|
void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
|
2009-09-30 00:23:42 +00:00
|
|
|
if (Subtarget->isTargetDarwin()) {
|
|
|
|
Reloc::Model RelocM = TM.getRelocationModel();
|
|
|
|
if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
|
|
|
|
// Declare all the text sections up front (before the DWARF sections
|
|
|
|
// emitted by AsmPrinter::doInitialization) so the assembler will keep
|
|
|
|
// them together at the beginning of the object file. This helps
|
|
|
|
// avoid out-of-range branches that are due a fundamental limitation of
|
|
|
|
// the way symbol offsets are encoded with the current Darwin ARM
|
|
|
|
// relocations.
|
2010-09-02 01:02:06 +00:00
|
|
|
const TargetLoweringObjectFileMachO &TLOFMacho =
|
2010-04-17 16:44:48 +00:00
|
|
|
static_cast<const TargetLoweringObjectFileMachO &>(
|
|
|
|
getObjFileLowering());
|
2009-09-30 22:25:37 +00:00
|
|
|
OutStreamer.SwitchSection(TLOFMacho.getTextSection());
|
|
|
|
OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
|
|
|
|
OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
|
|
|
|
if (RelocM == Reloc::DynamicNoPIC) {
|
|
|
|
const MCSection *sect =
|
2010-04-08 20:40:11 +00:00
|
|
|
OutContext.getMachOSection("__TEXT", "__symbol_stub4",
|
|
|
|
MCSectionMachO::S_SYMBOL_STUBS,
|
|
|
|
12, SectionKind::getText());
|
2009-09-30 22:25:37 +00:00
|
|
|
OutStreamer.SwitchSection(sect);
|
|
|
|
} else {
|
|
|
|
const MCSection *sect =
|
2010-04-08 20:40:11 +00:00
|
|
|
OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
|
|
|
|
MCSectionMachO::S_SYMBOL_STUBS,
|
|
|
|
16, SectionKind::getText());
|
2009-09-30 22:25:37 +00:00
|
|
|
OutStreamer.SwitchSection(sect);
|
|
|
|
}
|
2010-07-30 19:55:47 +00:00
|
|
|
const MCSection *StaticInitSect =
|
|
|
|
OutContext.getMachOSection("__TEXT", "__StaticInit",
|
|
|
|
MCSectionMachO::S_REGULAR |
|
|
|
|
MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
|
|
|
|
SectionKind::getText());
|
|
|
|
OutStreamer.SwitchSection(StaticInitSect);
|
2009-09-30 00:23:42 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-11-09 00:11:35 +00:00
|
|
|
// Use unified assembler syntax.
|
2010-09-30 02:45:56 +00:00
|
|
|
OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
|
2009-06-17 23:43:18 +00:00
|
|
|
|
2009-05-23 19:51:20 +00:00
|
|
|
// Emit ARM Build Attributes
|
|
|
|
if (Subtarget->isTargetELF()) {
|
2010-09-02 01:02:06 +00:00
|
|
|
|
2010-10-06 22:36:46 +00:00
|
|
|
emitAttributes();
|
2009-05-23 19:51:20 +00:00
|
|
|
}
|
2006-05-14 22:18:28 +00:00
|
|
|
}
|
|
|
|
|
2008-08-07 09:54:23 +00:00
|
|
|
|
2009-10-19 17:59:19 +00:00
|
|
|
void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
|
2007-01-19 19:25:36 +00:00
|
|
|
if (Subtarget->isTargetDarwin()) {
|
2009-08-03 22:18:15 +00:00
|
|
|
// All darwin targets use mach-o.
|
2010-04-17 16:44:48 +00:00
|
|
|
const TargetLoweringObjectFileMachO &TLOFMacho =
|
|
|
|
static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
|
2009-10-19 18:38:33 +00:00
|
|
|
MachineModuleInfoMachO &MMIMacho =
|
|
|
|
MMI->getObjFileInfo<MachineModuleInfoMachO>();
|
2009-09-04 01:38:51 +00:00
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
// Output non-lazy-pointers for external and common global variables.
|
2009-10-19 18:38:33 +00:00
|
|
|
MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
|
2010-03-10 22:34:10 +00:00
|
|
|
|
2009-10-19 18:38:33 +00:00
|
|
|
if (!Stubs.empty()) {
|
2009-08-10 01:39:42 +00:00
|
|
|
// Switch with ".non_lazy_symbol_pointer" directive.
|
2009-08-19 05:49:37 +00:00
|
|
|
OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
|
2009-08-10 18:01:34 +00:00
|
|
|
EmitAlignment(2);
|
2009-10-19 18:38:33 +00:00
|
|
|
for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
|
2010-03-09 00:40:17 +00:00
|
|
|
// L_foo$stub:
|
|
|
|
OutStreamer.EmitLabel(Stubs[i].first);
|
|
|
|
// .indirect_symbol _foo
|
2010-03-11 01:18:13 +00:00
|
|
|
MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
|
|
|
|
OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
|
2010-03-09 00:43:34 +00:00
|
|
|
|
2010-03-11 01:18:13 +00:00
|
|
|
if (MCSym.getInt())
|
2010-03-09 00:43:34 +00:00
|
|
|
// External to current translation unit.
|
|
|
|
OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
|
|
|
|
else
|
|
|
|
// Internal to current translation unit.
|
2010-03-31 18:47:10 +00:00
|
|
|
//
|
2010-09-22 16:45:13 +00:00
|
|
|
// When we place the LSDA into the TEXT section, the type info
|
|
|
|
// pointers need to be indirect and pc-rel. We accomplish this by
|
|
|
|
// using NLPs; however, sometimes the types are local to the file.
|
|
|
|
// We need to fill in the value for the NLP in those cases.
|
2010-03-11 01:18:13 +00:00
|
|
|
OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
|
|
|
|
OutContext),
|
2010-03-09 00:43:34 +00:00
|
|
|
4/*size*/, 0/*addrspace*/);
|
2008-12-05 01:06:39 +00:00
|
|
|
}
|
2010-03-09 00:40:17 +00:00
|
|
|
|
|
|
|
Stubs.clear();
|
|
|
|
OutStreamer.AddBlankLine();
|
2007-01-19 07:51:42 +00:00
|
|
|
}
|
|
|
|
|
2009-10-19 18:44:38 +00:00
|
|
|
Stubs = MMIMacho.GetHiddenGVStubList();
|
|
|
|
if (!Stubs.empty()) {
|
2009-08-19 05:49:37 +00:00
|
|
|
OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
|
2009-08-10 18:02:16 +00:00
|
|
|
EmitAlignment(2);
|
2010-03-09 00:40:17 +00:00
|
|
|
for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
|
|
|
|
// L_foo$stub:
|
|
|
|
OutStreamer.EmitLabel(Stubs[i].first);
|
|
|
|
// .long _foo
|
2010-03-10 22:34:10 +00:00
|
|
|
OutStreamer.EmitValue(MCSymbolRefExpr::
|
|
|
|
Create(Stubs[i].second.getPointer(),
|
|
|
|
OutContext),
|
2010-03-09 00:40:17 +00:00
|
|
|
4/*size*/, 0/*addrspace*/);
|
|
|
|
}
|
2010-03-09 00:43:34 +00:00
|
|
|
|
|
|
|
Stubs.clear();
|
|
|
|
OutStreamer.AddBlankLine();
|
2008-12-05 01:06:39 +00:00
|
|
|
}
|
|
|
|
|
2007-01-19 07:51:42 +00:00
|
|
|
// Funny Darwin hack: This flag tells the linker that no global symbols
|
|
|
|
// contain code that falls through to other global symbols (e.g. the obvious
|
|
|
|
// implementation of multiple entry points). If this doesn't occur, the
|
|
|
|
// linker can safely perform dead code stripping. Since LLVM never
|
|
|
|
// generates code that does this, it is always safe to set.
|
2010-01-23 06:39:22 +00:00
|
|
|
OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
|
2006-07-27 11:38:51 +00:00
|
|
|
}
|
2006-05-14 22:18:28 +00:00
|
|
|
}
|
2008-08-17 13:55:10 +00:00
|
|
|
|
2010-10-06 22:36:46 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
|
|
|
|
// FIXME:
|
|
|
|
// The following seem like one-off assembler flags, but they actually need
|
2010-10-06 22:46:47 +00:00
|
|
|
// to appear in the .ARM.attributes section in ELF.
|
2010-10-06 22:36:46 +00:00
|
|
|
// Instead of subclassing the MCELFStreamer, we do the work here.
|
|
|
|
|
|
|
|
void ARMAsmPrinter::emitAttributes() {
|
2010-10-06 22:46:47 +00:00
|
|
|
|
2010-10-11 23:01:44 +00:00
|
|
|
emitARMAttributeSection();
|
|
|
|
|
2010-10-25 17:50:35 +00:00
|
|
|
AttributeEmitter *AttrEmitter;
|
|
|
|
if (OutStreamer.hasRawTextSupport())
|
|
|
|
AttrEmitter = new AsmAttributeEmitter(OutStreamer);
|
|
|
|
else {
|
|
|
|
MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
|
|
|
|
AttrEmitter = new ObjectAttributeEmitter(O);
|
|
|
|
}
|
|
|
|
|
|
|
|
AttrEmitter->MaybeSwitchVendor("aeabi");
|
|
|
|
|
2010-10-06 22:36:46 +00:00
|
|
|
std::string CPUString = Subtarget->getCPUString();
|
2010-10-25 17:50:35 +00:00
|
|
|
if (OutStreamer.hasRawTextSupport()) {
|
|
|
|
if (CPUString != "generic")
|
|
|
|
OutStreamer.EmitRawText(StringRef("\t.cpu ") + CPUString);
|
|
|
|
} else {
|
|
|
|
assert(CPUString == "generic" && "Unsupported .cpu attribute for ELF/.o");
|
|
|
|
// FIXME: Why these defaults?
|
|
|
|
AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
|
|
|
|
AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, 1);
|
|
|
|
AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, 1);
|
|
|
|
}
|
2010-10-06 22:36:46 +00:00
|
|
|
|
|
|
|
// FIXME: Emit FPU type
|
|
|
|
if (Subtarget->hasVFP2())
|
2010-10-25 17:50:35 +00:00
|
|
|
AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, 2);
|
2010-10-06 22:36:46 +00:00
|
|
|
|
|
|
|
// Signal various FP modes.
|
|
|
|
if (!UnsafeFPMath) {
|
2010-10-25 17:50:35 +00:00
|
|
|
AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal, 1);
|
|
|
|
AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions, 1);
|
2010-10-06 22:36:46 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (NoInfsFPMath && NoNaNsFPMath)
|
2010-10-25 17:50:35 +00:00
|
|
|
AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 1);
|
2010-10-06 22:36:46 +00:00
|
|
|
else
|
2010-10-25 17:50:35 +00:00
|
|
|
AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 3);
|
2010-10-06 22:36:46 +00:00
|
|
|
|
|
|
|
// 8-bytes alignment stuff.
|
2010-10-25 17:50:35 +00:00
|
|
|
AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
|
|
|
|
AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
|
2010-10-06 22:36:46 +00:00
|
|
|
|
|
|
|
// Hard float. Use both S and D registers and conform to AAPCS-VFP.
|
|
|
|
if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
|
2010-10-25 17:50:35 +00:00
|
|
|
AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
|
|
|
|
AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
|
2010-10-06 22:36:46 +00:00
|
|
|
}
|
|
|
|
// FIXME: Should we signal R9 usage?
|
2010-10-25 17:50:35 +00:00
|
|
|
|
|
|
|
AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
|
|
|
|
|
|
|
|
AttrEmitter->Finish();
|
|
|
|
delete AttrEmitter;
|
2010-10-06 22:36:46 +00:00
|
|
|
}
|
|
|
|
|
2010-10-11 23:01:44 +00:00
|
|
|
void ARMAsmPrinter::emitARMAttributeSection() {
|
|
|
|
// <format-version>
|
|
|
|
// [ <section-length> "vendor-name"
|
|
|
|
// [ <file-tag> <size> <attribute>*
|
|
|
|
// | <section-tag> <size> <section-number>* 0 <attribute>*
|
|
|
|
// | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
|
|
|
|
// ]+
|
|
|
|
// ]*
|
|
|
|
|
|
|
|
if (OutStreamer.hasRawTextSupport())
|
|
|
|
return;
|
|
|
|
|
|
|
|
const ARMElfTargetObjectFile &TLOFELF =
|
|
|
|
static_cast<const ARMElfTargetObjectFile &>
|
|
|
|
(getObjFileLowering());
|
|
|
|
|
|
|
|
OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
|
2010-10-06 22:36:46 +00:00
|
|
|
|
2010-10-25 17:50:35 +00:00
|
|
|
// Format version
|
|
|
|
OutStreamer.EmitIntValue(0x41, 1);
|
2010-10-11 23:01:44 +00:00
|
|
|
}
|
|
|
|
|
2009-10-19 20:20:46 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2010-09-18 00:05:05 +00:00
|
|
|
static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
|
|
|
|
unsigned LabelId, MCContext &Ctx) {
|
|
|
|
|
|
|
|
MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
|
|
|
|
+ "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
|
|
|
|
return Label;
|
|
|
|
}
|
|
|
|
|
2010-09-22 17:39:48 +00:00
|
|
|
void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
|
|
|
|
unsigned Opcode = MI->getOpcode();
|
|
|
|
int OpNum = 1;
|
|
|
|
if (Opcode == ARM::BR_JTadd)
|
|
|
|
OpNum = 2;
|
|
|
|
else if (Opcode == ARM::BR_JTm)
|
|
|
|
OpNum = 3;
|
|
|
|
|
|
|
|
const MachineOperand &MO1 = MI->getOperand(OpNum);
|
|
|
|
const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
|
|
|
|
unsigned JTI = MO1.getIndex();
|
|
|
|
|
|
|
|
// Emit a label for the jump table.
|
|
|
|
MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
|
|
|
|
OutStreamer.EmitLabel(JTISymbol);
|
|
|
|
|
|
|
|
// Emit each entry of the table.
|
|
|
|
const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
|
|
|
|
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
|
|
|
|
const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
|
|
|
|
|
|
|
|
for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
|
|
|
|
MachineBasicBlock *MBB = JTBBs[i];
|
|
|
|
// Construct an MCExpr for the entry. We want a value of the form:
|
|
|
|
// (BasicBlockAddr - TableBeginAddr)
|
|
|
|
//
|
|
|
|
// For example, a table with entries jumping to basic blocks BB0 and BB1
|
|
|
|
// would look like:
|
|
|
|
// LJTI_0_0:
|
|
|
|
// .word (LBB0 - LJTI_0_0)
|
|
|
|
// .word (LBB1 - LJTI_0_0)
|
|
|
|
const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
|
|
|
|
|
|
|
|
if (TM.getRelocationModel() == Reloc::PIC_)
|
|
|
|
Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
|
|
|
|
OutContext),
|
|
|
|
OutContext);
|
|
|
|
OutStreamer.EmitValue(Expr, 4);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-09-21 23:28:16 +00:00
|
|
|
void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
|
|
|
|
unsigned Opcode = MI->getOpcode();
|
|
|
|
int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
|
|
|
|
const MachineOperand &MO1 = MI->getOperand(OpNum);
|
|
|
|
const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
|
|
|
|
unsigned JTI = MO1.getIndex();
|
|
|
|
|
|
|
|
// Emit a label for the jump table.
|
|
|
|
MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
|
|
|
|
OutStreamer.EmitLabel(JTISymbol);
|
|
|
|
|
|
|
|
// Emit each entry of the table.
|
|
|
|
const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
|
|
|
|
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
|
|
|
|
const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
|
2010-09-22 17:15:35 +00:00
|
|
|
unsigned OffsetWidth = 4;
|
2010-09-21 23:28:16 +00:00
|
|
|
if (MI->getOpcode() == ARM::t2TBB)
|
2010-09-22 17:15:35 +00:00
|
|
|
OffsetWidth = 1;
|
2010-09-21 23:28:16 +00:00
|
|
|
else if (MI->getOpcode() == ARM::t2TBH)
|
2010-09-22 17:15:35 +00:00
|
|
|
OffsetWidth = 2;
|
2010-09-21 23:28:16 +00:00
|
|
|
|
|
|
|
for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
|
|
|
|
MachineBasicBlock *MBB = JTBBs[i];
|
2010-09-22 17:15:35 +00:00
|
|
|
const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
|
|
|
|
OutContext);
|
2010-09-21 23:28:16 +00:00
|
|
|
// If this isn't a TBB or TBH, the entries are direct branch instructions.
|
2010-09-22 17:15:35 +00:00
|
|
|
if (OffsetWidth == 4) {
|
2010-09-21 23:28:16 +00:00
|
|
|
MCInst BrInst;
|
|
|
|
BrInst.setOpcode(ARM::t2B);
|
2010-09-22 17:15:35 +00:00
|
|
|
BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
|
2010-09-21 23:28:16 +00:00
|
|
|
OutStreamer.EmitInstruction(BrInst);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
// Otherwise it's an offset from the dispatch instruction. Construct an
|
2010-09-22 17:15:35 +00:00
|
|
|
// MCExpr for the entry. We want a value of the form:
|
|
|
|
// (BasicBlockAddr - TableBeginAddr) / 2
|
|
|
|
//
|
|
|
|
// For example, a TBB table with entries jumping to basic blocks BB0 and BB1
|
|
|
|
// would look like:
|
|
|
|
// LJTI_0_0:
|
|
|
|
// .byte (LBB0 - LJTI_0_0) / 2
|
|
|
|
// .byte (LBB1 - LJTI_0_0) / 2
|
|
|
|
const MCExpr *Expr =
|
|
|
|
MCBinaryExpr::CreateSub(MBBSymbolExpr,
|
|
|
|
MCSymbolRefExpr::Create(JTISymbol, OutContext),
|
|
|
|
OutContext);
|
|
|
|
Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
|
|
|
|
OutContext);
|
|
|
|
OutStreamer.EmitValue(Expr, OffsetWidth);
|
2010-09-21 23:28:16 +00:00
|
|
|
}
|
2010-09-22 17:15:35 +00:00
|
|
|
|
|
|
|
// Make sure the instruction that follows TBB is 2-byte aligned.
|
|
|
|
// FIXME: Constant island pass should insert an "ALIGN" instruction instead.
|
|
|
|
if (MI->getOpcode() == ARM::t2TBB)
|
|
|
|
EmitAlignment(1);
|
2010-09-21 23:28:16 +00:00
|
|
|
}
|
|
|
|
|
2010-09-28 17:05:56 +00:00
|
|
|
void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
|
|
|
|
raw_ostream &OS) {
|
|
|
|
unsigned NOps = MI->getNumOperands();
|
|
|
|
assert(NOps==4);
|
|
|
|
OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
|
|
|
|
// cast away const; DIetc do not take const operands for some reason.
|
|
|
|
DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
|
|
|
|
OS << V.getName();
|
|
|
|
OS << " <- ";
|
|
|
|
// Frame address. Currently handles register +- offset only.
|
|
|
|
assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
|
|
|
|
OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
|
|
|
|
OS << ']';
|
|
|
|
OS << "+";
|
|
|
|
printOperand(MI, NOps-2, OS);
|
|
|
|
}
|
|
|
|
|
2010-09-29 15:23:40 +00:00
|
|
|
void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
|
2009-10-20 00:52:47 +00:00
|
|
|
ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
|
2009-10-19 20:20:46 +00:00
|
|
|
switch (MI->getOpcode()) {
|
2009-10-20 05:58:02 +00:00
|
|
|
case ARM::t2MOVi32imm:
|
|
|
|
assert(0 && "Should be lowered by thumb2it pass");
|
2009-10-19 22:23:04 +00:00
|
|
|
default: break;
|
2010-09-28 17:05:56 +00:00
|
|
|
case ARM::DBG_VALUE: {
|
|
|
|
if (isVerbose() && OutStreamer.hasRawTextSupport()) {
|
|
|
|
SmallString<128> TmpStr;
|
|
|
|
raw_svector_ostream OS(TmpStr);
|
|
|
|
PrintDebugValueComment(MI, OS);
|
|
|
|
OutStreamer.EmitRawText(StringRef(OS.str()));
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
2010-09-17 23:41:53 +00:00
|
|
|
case ARM::tPICADD: {
|
|
|
|
// This is a pseudo op for a label + instruction sequence, which looks like:
|
|
|
|
// LPC0:
|
|
|
|
// add r0, pc
|
|
|
|
// This adds the address of LPC0 to r0.
|
|
|
|
|
|
|
|
// Emit the label.
|
2010-09-18 00:05:05 +00:00
|
|
|
OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
|
|
|
|
getFunctionNumber(), MI->getOperand(2).getImm(),
|
|
|
|
OutContext));
|
2010-09-17 23:41:53 +00:00
|
|
|
|
|
|
|
// Form and emit the add.
|
|
|
|
MCInst AddInst;
|
|
|
|
AddInst.setOpcode(ARM::tADDhirr);
|
|
|
|
AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
|
|
|
|
AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
|
|
|
|
AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
|
|
|
|
// Add predicate operands.
|
|
|
|
AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
|
|
AddInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
OutStreamer.EmitInstruction(AddInst);
|
|
|
|
return;
|
|
|
|
}
|
2010-09-30 19:53:58 +00:00
|
|
|
case ARM::PICADD: {
|
2009-10-19 22:23:04 +00:00
|
|
|
// This is a pseudo op for a label + instruction sequence, which looks like:
|
|
|
|
// LPC0:
|
|
|
|
// add r0, pc, r0
|
|
|
|
// This adds the address of LPC0 to r0.
|
2010-09-02 01:02:06 +00:00
|
|
|
|
2009-10-19 22:23:04 +00:00
|
|
|
// Emit the label.
|
2010-09-18 00:05:05 +00:00
|
|
|
OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
|
|
|
|
getFunctionNumber(), MI->getOperand(2).getImm(),
|
|
|
|
OutContext));
|
2010-09-02 01:02:06 +00:00
|
|
|
|
2010-09-14 21:05:34 +00:00
|
|
|
// Form and emit the add.
|
2009-10-19 22:23:04 +00:00
|
|
|
MCInst AddInst;
|
|
|
|
AddInst.setOpcode(ARM::ADDrr);
|
|
|
|
AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
|
|
|
|
AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
|
|
|
|
AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
|
2010-09-14 21:28:17 +00:00
|
|
|
// Add predicate operands.
|
|
|
|
AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
|
|
|
|
AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
|
|
|
|
// Add 's' bit operand (always reg0 for this)
|
|
|
|
AddInst.addOperand(MCOperand::CreateReg(0));
|
2010-02-03 01:16:28 +00:00
|
|
|
OutStreamer.EmitInstruction(AddInst);
|
2009-10-19 22:23:04 +00:00
|
|
|
return;
|
2010-09-16 17:43:25 +00:00
|
|
|
}
|
2010-09-17 16:25:52 +00:00
|
|
|
case ARM::PICSTR:
|
|
|
|
case ARM::PICSTRB:
|
|
|
|
case ARM::PICSTRH:
|
|
|
|
case ARM::PICLDR:
|
|
|
|
case ARM::PICLDRB:
|
|
|
|
case ARM::PICLDRH:
|
|
|
|
case ARM::PICLDRSB:
|
|
|
|
case ARM::PICLDRSH: {
|
2010-09-16 17:43:25 +00:00
|
|
|
// This is a pseudo op for a label + instruction sequence, which looks like:
|
|
|
|
// LPC0:
|
2010-09-17 16:25:52 +00:00
|
|
|
// OP r0, [pc, r0]
|
2010-09-16 17:43:25 +00:00
|
|
|
// The LCP0 label is referenced by a constant pool entry in order to get
|
|
|
|
// a PC-relative address at the ldr instruction.
|
|
|
|
|
|
|
|
// Emit the label.
|
2010-09-18 00:05:05 +00:00
|
|
|
OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
|
|
|
|
getFunctionNumber(), MI->getOperand(2).getImm(),
|
|
|
|
OutContext));
|
2010-09-16 17:43:25 +00:00
|
|
|
|
|
|
|
// Form and emit the load
|
2010-09-17 16:25:52 +00:00
|
|
|
unsigned Opcode;
|
|
|
|
switch (MI->getOpcode()) {
|
|
|
|
default:
|
|
|
|
llvm_unreachable("Unexpected opcode!");
|
|
|
|
case ARM::PICSTR: Opcode = ARM::STR; break;
|
|
|
|
case ARM::PICSTRB: Opcode = ARM::STRB; break;
|
|
|
|
case ARM::PICSTRH: Opcode = ARM::STRH; break;
|
|
|
|
case ARM::PICLDR: Opcode = ARM::LDR; break;
|
|
|
|
case ARM::PICLDRB: Opcode = ARM::LDRB; break;
|
|
|
|
case ARM::PICLDRH: Opcode = ARM::LDRH; break;
|
|
|
|
case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
|
|
|
|
case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
|
|
|
|
}
|
|
|
|
MCInst LdStInst;
|
|
|
|
LdStInst.setOpcode(Opcode);
|
|
|
|
LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
|
|
|
|
LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
|
|
|
|
LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
|
|
|
|
LdStInst.addOperand(MCOperand::CreateImm(0));
|
2010-09-16 17:43:25 +00:00
|
|
|
// Add predicate operands.
|
2010-09-17 16:25:52 +00:00
|
|
|
LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
|
|
|
|
LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
|
|
|
|
OutStreamer.EmitInstruction(LdStInst);
|
2010-09-16 17:43:25 +00:00
|
|
|
|
|
|
|
return;
|
2009-10-19 22:23:04 +00:00
|
|
|
}
|
2010-09-30 19:53:58 +00:00
|
|
|
case ARM::CONSTPOOL_ENTRY: {
|
2009-10-19 22:33:05 +00:00
|
|
|
/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
|
|
|
|
/// in the function. The first operand is the ID# for this instruction, the
|
|
|
|
/// second is the index into the MachineConstantPool that this is, the third
|
|
|
|
/// is the size in bytes of this constant pool entry.
|
|
|
|
unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
|
|
|
|
unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
|
|
|
|
|
|
|
|
EmitAlignment(2);
|
2010-01-23 07:00:21 +00:00
|
|
|
OutStreamer.EmitLabel(GetCPISymbol(LabelId));
|
2009-10-19 22:33:05 +00:00
|
|
|
|
|
|
|
const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
|
|
|
|
if (MCPE.isMachineConstantPoolEntry())
|
|
|
|
EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
|
|
|
|
else
|
|
|
|
EmitGlobalConstant(MCPE.Val.ConstVal);
|
2010-09-02 01:02:06 +00:00
|
|
|
|
2009-10-19 22:33:05 +00:00
|
|
|
return;
|
|
|
|
}
|
2010-09-30 19:53:58 +00:00
|
|
|
case ARM::MOVi2pieces: {
|
|
|
|
// FIXME: We'd like to remove the asm string in the .td file, but the
|
2009-10-20 00:40:56 +00:00
|
|
|
// This is a hack that lowers as a two instruction sequence.
|
|
|
|
unsigned DstReg = MI->getOperand(0).getReg();
|
|
|
|
unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
|
|
|
|
|
|
|
|
unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
|
|
|
|
unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
|
2010-09-02 01:02:06 +00:00
|
|
|
|
2009-10-20 00:40:56 +00:00
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::MOVi);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(DstReg));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
|
2010-09-02 01:02:06 +00:00
|
|
|
|
2009-10-20 00:40:56 +00:00
|
|
|
// Predicate.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
|
2009-10-20 00:46:11 +00:00
|
|
|
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
|
2010-02-03 01:16:28 +00:00
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
2009-10-20 00:40:56 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::ORRri);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
|
|
|
|
// Predicate.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
|
2010-09-02 01:02:06 +00:00
|
|
|
|
2009-10-20 00:40:56 +00:00
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
|
2010-02-03 01:16:28 +00:00
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
2009-10-20 00:40:56 +00:00
|
|
|
}
|
2010-09-02 01:02:06 +00:00
|
|
|
return;
|
2009-10-20 00:40:56 +00:00
|
|
|
}
|
2010-09-30 19:53:58 +00:00
|
|
|
case ARM::MOVi32imm: {
|
|
|
|
// FIXME: We'd like to remove the asm string in the .td file, but the
|
2009-10-20 01:11:37 +00:00
|
|
|
// This is a hack that lowers as a two instruction sequence.
|
|
|
|
unsigned DstReg = MI->getOperand(0).getReg();
|
2010-05-12 05:16:34 +00:00
|
|
|
const MachineOperand &MO = MI->getOperand(1);
|
|
|
|
MCOperand V1, V2;
|
|
|
|
if (MO.isImm()) {
|
|
|
|
unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
|
|
|
|
V1 = MCOperand::CreateImm(ImmVal & 65535);
|
|
|
|
V2 = MCOperand::CreateImm(ImmVal >> 16);
|
|
|
|
} else if (MO.isGlobal()) {
|
2010-09-17 18:25:25 +00:00
|
|
|
MCSymbol *Symbol = MCInstLowering.GetGlobalAddressSymbol(MO.getGlobal());
|
2010-05-12 05:16:34 +00:00
|
|
|
const MCSymbolRefExpr *SymRef1 =
|
2010-07-12 08:16:59 +00:00
|
|
|
MCSymbolRefExpr::Create(Symbol,
|
|
|
|
MCSymbolRefExpr::VK_ARM_LO16, OutContext);
|
2010-05-12 05:16:34 +00:00
|
|
|
const MCSymbolRefExpr *SymRef2 =
|
2010-07-12 08:16:59 +00:00
|
|
|
MCSymbolRefExpr::Create(Symbol,
|
|
|
|
MCSymbolRefExpr::VK_ARM_HI16, OutContext);
|
2010-05-12 05:16:34 +00:00
|
|
|
V1 = MCOperand::CreateExpr(SymRef1);
|
|
|
|
V2 = MCOperand::CreateExpr(SymRef2);
|
|
|
|
} else {
|
2010-09-22 20:55:15 +00:00
|
|
|
// FIXME: External symbol?
|
2010-05-12 05:16:34 +00:00
|
|
|
MI->dump();
|
|
|
|
llvm_unreachable("cannot handle this operand");
|
|
|
|
}
|
|
|
|
|
2009-10-20 01:11:37 +00:00
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::MOVi16);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
|
2010-05-12 05:16:34 +00:00
|
|
|
TmpInst.addOperand(V1); // lower16(imm)
|
2010-09-02 01:02:06 +00:00
|
|
|
|
2009-10-20 01:11:37 +00:00
|
|
|
// Predicate.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
|
2010-09-02 01:02:06 +00:00
|
|
|
|
2010-02-03 01:16:28 +00:00
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
2009-10-20 01:11:37 +00:00
|
|
|
}
|
2010-09-02 01:02:06 +00:00
|
|
|
|
2009-10-20 01:11:37 +00:00
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::MOVTi16);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
|
2010-05-12 05:16:34 +00:00
|
|
|
TmpInst.addOperand(V2); // upper16(imm)
|
2010-09-02 01:02:06 +00:00
|
|
|
|
2009-10-20 01:11:37 +00:00
|
|
|
// Predicate.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
|
2010-09-02 01:02:06 +00:00
|
|
|
|
2010-02-03 01:16:28 +00:00
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
2009-10-20 01:11:37 +00:00
|
|
|
}
|
2010-09-02 01:02:06 +00:00
|
|
|
|
2009-10-20 01:11:37 +00:00
|
|
|
return;
|
|
|
|
}
|
2010-09-21 23:28:16 +00:00
|
|
|
case ARM::t2TBB:
|
|
|
|
case ARM::t2TBH:
|
|
|
|
case ARM::t2BR_JT: {
|
|
|
|
// Lower and emit the instruction itself, then the jump table following it.
|
|
|
|
MCInst TmpInst;
|
|
|
|
MCInstLowering.Lower(MI, TmpInst);
|
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
|
|
EmitJump2Table(MI);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
case ARM::tBR_JTr:
|
|
|
|
case ARM::BR_JTr:
|
|
|
|
case ARM::BR_JTm:
|
2010-09-22 17:39:48 +00:00
|
|
|
case ARM::BR_JTadd: {
|
|
|
|
// Lower and emit the instruction itself, then the jump table following it.
|
|
|
|
MCInst TmpInst;
|
|
|
|
MCInstLowering.Lower(MI, TmpInst);
|
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
|
|
EmitJumpTable(MI);
|
|
|
|
return;
|
|
|
|
}
|
2010-09-23 18:05:37 +00:00
|
|
|
case ARM::TRAP: {
|
|
|
|
// Non-Darwin binutils don't yet support the "trap" mnemonic.
|
|
|
|
// FIXME: Remove this special case when they do.
|
|
|
|
if (!Subtarget->isTargetDarwin()) {
|
2010-10-01 23:21:38 +00:00
|
|
|
//.long 0xe7ffdefe @ trap
|
2010-09-23 19:42:17 +00:00
|
|
|
uint32_t Val = 0xe7ffdefeUL;
|
2010-09-23 18:05:37 +00:00
|
|
|
OutStreamer.AddComment("trap");
|
|
|
|
OutStreamer.EmitIntValue(Val, 4);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case ARM::tTRAP: {
|
|
|
|
// Non-Darwin binutils don't yet support the "trap" mnemonic.
|
|
|
|
// FIXME: Remove this special case when they do.
|
|
|
|
if (!Subtarget->isTargetDarwin()) {
|
2010-10-01 23:21:38 +00:00
|
|
|
//.short 57086 @ trap
|
2010-09-23 18:57:26 +00:00
|
|
|
uint16_t Val = 0xdefe;
|
2010-09-23 18:05:37 +00:00
|
|
|
OutStreamer.AddComment("trap");
|
|
|
|
OutStreamer.EmitIntValue(Val, 2);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2010-09-24 20:47:58 +00:00
|
|
|
case ARM::t2Int_eh_sjlj_setjmp:
|
|
|
|
case ARM::t2Int_eh_sjlj_setjmp_nofp:
|
2010-09-30 19:53:58 +00:00
|
|
|
case ARM::tInt_eh_sjlj_setjmp: {
|
2010-09-24 20:47:58 +00:00
|
|
|
// Two incoming args: GPR:$src, GPR:$val
|
|
|
|
// mov $val, pc
|
|
|
|
// adds $val, #7
|
|
|
|
// str $val, [$src, #4]
|
|
|
|
// movs r0, #0
|
|
|
|
// b 1f
|
|
|
|
// movs r0, #1
|
|
|
|
// 1:
|
|
|
|
unsigned SrcReg = MI->getOperand(0).getReg();
|
|
|
|
unsigned ValReg = MI->getOperand(1).getReg();
|
|
|
|
MCSymbol *Label = GetARMSJLJEHLabel();
|
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ValReg));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
|
|
|
|
// 's' bit operand
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
|
|
|
|
OutStreamer.AddComment("eh_setjmp begin");
|
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
|
|
}
|
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::tADDi3);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ValReg));
|
|
|
|
// 's' bit operand
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ValReg));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(7));
|
|
|
|
// Predicate.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
|
|
}
|
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::tSTR);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ValReg));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
|
|
|
|
// The offset immediate is #4. The operand value is scaled by 4 for the
|
|
|
|
// tSTR instruction.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(1));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
// Predicate.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
|
|
}
|
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::tMOVi8);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(0));
|
|
|
|
// Predicate.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
|
|
}
|
|
|
|
{
|
|
|
|
const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::tB);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
|
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
|
|
}
|
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::tMOVi8);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(1));
|
|
|
|
// Predicate.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
OutStreamer.AddComment("eh_setjmp end");
|
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
|
|
}
|
|
|
|
OutStreamer.EmitLabel(Label);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2010-09-23 23:33:56 +00:00
|
|
|
case ARM::Int_eh_sjlj_setjmp_nofp:
|
2010-09-30 19:53:58 +00:00
|
|
|
case ARM::Int_eh_sjlj_setjmp: {
|
2010-09-23 23:33:56 +00:00
|
|
|
// Two incoming args: GPR:$src, GPR:$val
|
|
|
|
// add $val, pc, #8
|
|
|
|
// str $val, [$src, #+4]
|
|
|
|
// mov r0, #0
|
|
|
|
// add pc, pc, #0
|
|
|
|
// mov r0, #1
|
|
|
|
unsigned SrcReg = MI->getOperand(0).getReg();
|
|
|
|
unsigned ValReg = MI->getOperand(1).getReg();
|
|
|
|
|
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::ADDri);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ValReg));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(8));
|
|
|
|
// Predicate.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
// 's' bit operand (always reg0 for this).
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
OutStreamer.AddComment("eh_setjmp begin");
|
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
|
|
}
|
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::STR);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ValReg));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(4));
|
|
|
|
// Predicate.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
|
|
}
|
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::MOVi);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(0));
|
|
|
|
// Predicate.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
// 's' bit operand (always reg0 for this).
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
|
|
}
|
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::ADDri);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(0));
|
|
|
|
// Predicate.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
// 's' bit operand (always reg0 for this).
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
|
|
}
|
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::MOVi);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(1));
|
|
|
|
// Predicate.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
// 's' bit operand (always reg0 for this).
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
OutStreamer.AddComment("eh_setjmp end");
|
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
2010-09-27 21:47:04 +00:00
|
|
|
case ARM::Int_eh_sjlj_longjmp: {
|
|
|
|
// ldr sp, [$src, #8]
|
|
|
|
// ldr $scratch, [$src, #4]
|
|
|
|
// ldr r7, [$src]
|
|
|
|
// bx $scratch
|
|
|
|
unsigned SrcReg = MI->getOperand(0).getReg();
|
|
|
|
unsigned ScratchReg = MI->getOperand(1).getReg();
|
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::LDR);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(8));
|
|
|
|
// Predicate.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
|
|
}
|
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::LDR);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(4));
|
|
|
|
// Predicate.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
|
|
}
|
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::LDR);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(0));
|
|
|
|
// Predicate.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
|
|
}
|
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::BRIND);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
|
|
|
|
// Predicate.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
2010-09-27 22:28:11 +00:00
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
case ARM::tInt_eh_sjlj_longjmp: {
|
|
|
|
// ldr $scratch, [$src, #8]
|
|
|
|
// mov sp, $scratch
|
|
|
|
// ldr $scratch, [$src, #4]
|
|
|
|
// ldr r7, [$src]
|
|
|
|
// bx $scratch
|
|
|
|
unsigned SrcReg = MI->getOperand(0).getReg();
|
|
|
|
unsigned ScratchReg = MI->getOperand(1).getReg();
|
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::tLDR);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
|
|
|
|
// The offset immediate is #8. The operand value is scaled by 4 for the
|
|
|
|
// tSTR instruction.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(2));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
// Predicate.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
|
|
}
|
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
|
|
|
|
// Predicate.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
|
|
}
|
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::tLDR);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(1));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
// Predicate.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
|
|
}
|
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::tLDR);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(0));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
// Predicate.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
|
|
}
|
|
|
|
{
|
|
|
|
MCInst TmpInst;
|
|
|
|
TmpInst.setOpcode(ARM::tBX_RET_vararg);
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
|
|
|
|
// Predicate.
|
|
|
|
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
|
|
|
TmpInst.addOperand(MCOperand::CreateReg(0));
|
2010-09-27 21:47:04 +00:00
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
2009-10-19 20:20:46 +00:00
|
|
|
}
|
2010-09-02 01:02:06 +00:00
|
|
|
|
2009-10-19 20:20:46 +00:00
|
|
|
MCInst TmpInst;
|
|
|
|
MCInstLowering.Lower(MI, TmpInst);
|
2010-02-03 01:16:28 +00:00
|
|
|
OutStreamer.EmitInstruction(TmpInst);
|
2009-10-19 20:20:46 +00:00
|
|
|
}
|
2009-10-20 05:15:36 +00:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Target Registry Stuff
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
static MCInstPrinter *createARMMCInstPrinter(const Target &T,
|
|
|
|
unsigned SyntaxVariant,
|
2010-04-04 05:04:31 +00:00
|
|
|
const MCAsmInfo &MAI) {
|
2009-10-20 05:15:36 +00:00
|
|
|
if (SyntaxVariant == 0)
|
2010-09-17 21:33:25 +00:00
|
|
|
return new ARMInstPrinter(MAI);
|
2009-10-20 05:15:36 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Force static initialization.
|
|
|
|
extern "C" void LLVMInitializeARMAsmPrinter() {
|
|
|
|
RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
|
|
|
|
RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
|
|
|
|
|
|
|
|
TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
|
|
|
|
TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
|
|
|
|
}
|
|
|
|
|