2012-02-18 12:03:15 +00:00
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//===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
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2005-04-21 23:30:14 +00:00
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//
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2004-08-17 04:55:41 +00:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-21 23:30:14 +00:00
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//
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2004-08-17 04:55:41 +00:00
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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2005-10-14 23:59:06 +00:00
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#include "PPCInstrInfo.h"
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2012-12-03 16:50:05 +00:00
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#include "MCTargetDesc/PPCPredicates.h"
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2011-07-11 03:57:24 +00:00
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#include "PPC.h"
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2012-12-03 16:50:05 +00:00
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#include "PPCHazardRecognizers.h"
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2008-01-01 21:11:32 +00:00
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#include "PPCInstrBuilder.h"
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2008-03-03 22:19:16 +00:00
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#include "PPCMachineFunctionInfo.h"
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2006-06-17 00:01:04 +00:00
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#include "PPCTargetMachine.h"
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2012-12-03 16:50:05 +00:00
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#include "llvm/ADT/STLExtras.h"
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2010-07-16 18:22:00 +00:00
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#include "llvm/CodeGen/MachineFrameInfo.h"
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2004-08-17 04:55:41 +00:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2010-07-16 18:22:00 +00:00
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#include "llvm/CodeGen/MachineMemOperand.h"
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2010-02-26 21:09:24 +00:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2012-04-01 19:22:40 +00:00
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#include "llvm/CodeGen/PseudoSourceValue.h"
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2011-07-11 03:57:24 +00:00
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#include "llvm/MC/MCAsmInfo.h"
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2008-03-04 23:13:51 +00:00
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#include "llvm/Support/CommandLine.h"
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2009-07-08 20:53:28 +00:00
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#include "llvm/Support/ErrorHandling.h"
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2011-08-24 18:08:43 +00:00
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#include "llvm/Support/TargetRegistry.h"
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2009-07-08 20:53:28 +00:00
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#include "llvm/Support/raw_ostream.h"
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2004-08-17 04:55:41 +00:00
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2011-07-01 17:57:27 +00:00
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#define GET_INSTRINFO_CTOR
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2011-06-28 20:07:07 +00:00
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#include "PPCGenInstrInfo.inc"
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2010-04-15 17:20:57 +00:00
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using namespace llvm;
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2008-03-04 23:13:51 +00:00
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2012-06-08 15:38:25 +00:00
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static cl::
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2012-06-08 19:19:53 +00:00
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opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
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cl::desc("Disable analysis for CTR loops"));
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2012-06-08 15:38:25 +00:00
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2006-06-17 00:01:04 +00:00
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PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
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2011-07-01 17:57:27 +00:00
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: PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
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2011-06-28 21:14:33 +00:00
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TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
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2006-06-17 00:01:04 +00:00
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Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24 05:03:26 +00:00
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/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
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/// this target when scheduling the DAG.
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ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
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const TargetMachine *TM,
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const ScheduleDAG *DAG) const {
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2011-10-17 04:03:49 +00:00
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unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective();
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2012-08-28 16:12:39 +00:00
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if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
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Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
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2011-11-22 16:21:04 +00:00
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const InstrItineraryData *II = TM->getInstrItineraryData();
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2012-03-31 14:45:15 +00:00
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return new PPCScoreboardHazardRecognizer(II, DAG);
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2011-10-17 04:03:49 +00:00
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}
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2011-12-02 04:58:02 +00:00
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2012-11-28 02:35:17 +00:00
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return TargetInstrInfo::CreateTargetHazardRecognizer(TM, DAG);
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Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24 05:03:26 +00:00
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}
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2011-12-02 04:58:02 +00:00
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/// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
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/// to use for this target when scheduling the DAG.
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ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer(
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const InstrItineraryData *II,
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const ScheduleDAG *DAG) const {
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unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
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// Most subtargets use a PPC970 recognizer.
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2012-08-28 16:12:39 +00:00
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if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
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Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
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2011-12-02 04:58:02 +00:00
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const TargetInstrInfo *TII = TM.getInstrInfo();
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assert(TII && "No InstrInfo?");
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return new PPCHazardRecognizer970(*TII);
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}
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2012-04-01 19:22:40 +00:00
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return new PPCScoreboardHazardRecognizer(II, DAG);
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2011-12-02 04:58:02 +00:00
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}
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2012-06-19 21:14:34 +00:00
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// Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
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bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SubIdx) const {
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switch (MI.getOpcode()) {
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default: return false;
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case PPC::EXTSW:
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case PPC::EXTSW_32_64:
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SrcReg = MI.getOperand(1).getReg();
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DstReg = MI.getOperand(0).getReg();
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SubIdx = PPC::sub_32;
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return true;
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}
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}
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2010-12-24 04:28:06 +00:00
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unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
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2006-03-16 22:24:02 +00:00
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int &FrameIndex) const {
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2013-03-27 21:21:15 +00:00
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// Note: This list must be kept consistent with LoadRegFromStackSlot.
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2006-02-02 20:12:32 +00:00
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switch (MI->getOpcode()) {
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default: break;
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case PPC::LD:
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case PPC::LWZ:
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case PPC::LFS:
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case PPC::LFD:
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2013-03-27 21:21:15 +00:00
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case PPC::RESTORE_CR:
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case PPC::LVX:
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case PPC::RESTORE_VRSAVE:
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// Check for the operands added by addFrameReference (the immediate is the
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// offset which defaults to 0).
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2008-10-03 15:45:36 +00:00
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if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
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MI->getOperand(2).isFI()) {
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2007-12-30 23:10:15 +00:00
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FrameIndex = MI->getOperand(2).getIndex();
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2006-02-02 20:12:32 +00:00
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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2006-02-02 20:16:12 +00:00
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}
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2006-02-02 20:12:32 +00:00
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2010-12-24 04:28:06 +00:00
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unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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2006-02-02 20:16:12 +00:00
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int &FrameIndex) const {
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2013-03-27 21:21:15 +00:00
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// Note: This list must be kept consistent with StoreRegToStackSlot.
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2006-02-02 20:16:12 +00:00
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switch (MI->getOpcode()) {
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default: break;
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2006-02-02 21:07:50 +00:00
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case PPC::STD:
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2006-02-02 20:16:12 +00:00
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case PPC::STW:
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case PPC::STFS:
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case PPC::STFD:
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2013-03-27 21:21:15 +00:00
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case PPC::SPILL_CR:
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case PPC::STVX:
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case PPC::SPILL_VRSAVE:
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// Check for the operands added by addFrameReference (the immediate is the
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// offset which defaults to 0).
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2008-10-03 15:45:36 +00:00
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if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
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MI->getOperand(2).isFI()) {
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2007-12-30 23:10:15 +00:00
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FrameIndex = MI->getOperand(2).getIndex();
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2006-02-02 20:16:12 +00:00
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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2006-02-02 20:12:32 +00:00
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2005-09-09 18:17:41 +00:00
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// commuteInstruction - We can commute rlwimi instructions, but only if the
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// rotate amt is zero. We also have to munge the immediates a bit.
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2008-06-16 07:33:11 +00:00
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MachineInstr *
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PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
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2008-07-07 23:14:23 +00:00
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MachineFunction &MF = *MI->getParent()->getParent();
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2005-09-09 18:17:41 +00:00
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// Normal instructions can be commuted the obvious way.
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if (MI->getOpcode() != PPC::RLWIMI)
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2012-11-28 02:35:17 +00:00
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return TargetInstrInfo::commuteInstruction(MI, NewMI);
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2010-12-24 04:28:06 +00:00
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2005-09-09 18:17:41 +00:00
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// Cannot commute if it has a non-zero rotate count.
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2007-12-30 20:49:49 +00:00
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if (MI->getOperand(3).getImm() != 0)
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2005-09-09 18:17:41 +00:00
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return 0;
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2010-12-24 04:28:06 +00:00
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2005-09-09 18:17:41 +00:00
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// If we have a zero rotate count, we have:
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// M = mask(MB,ME)
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// Op0 = (Op1 & ~M) | (Op2 & M)
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// Change this to:
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// M = mask((ME+1)&31, (MB-1)&31)
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// Op0 = (Op2 & ~M) | (Op1 & M)
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// Swap op1/op2
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2008-02-13 02:46:49 +00:00
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unsigned Reg0 = MI->getOperand(0).getReg();
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2005-09-09 18:17:41 +00:00
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unsigned Reg1 = MI->getOperand(1).getReg();
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unsigned Reg2 = MI->getOperand(2).getReg();
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2006-11-15 20:58:11 +00:00
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bool Reg1IsKill = MI->getOperand(1).isKill();
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bool Reg2IsKill = MI->getOperand(2).isKill();
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2008-06-16 07:33:11 +00:00
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bool ChangeReg0 = false;
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2008-02-13 02:46:49 +00:00
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// If machine instrs are no longer in two-address forms, update
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// destination register as well.
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if (Reg0 == Reg1) {
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// Must be two address instruction!
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2011-06-28 19:10:37 +00:00
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assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
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2008-02-13 02:46:49 +00:00
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"Expecting a two-address instruction!");
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Reg2IsKill = false;
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2008-06-16 07:33:11 +00:00
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ChangeReg0 = true;
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}
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// Masks.
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unsigned MB = MI->getOperand(4).getImm();
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unsigned ME = MI->getOperand(5).getImm();
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if (NewMI) {
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// Create a new instruction.
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unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
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bool Reg0IsDead = MI->getOperand(0).isDead();
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2009-02-12 00:02:55 +00:00
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return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
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2009-05-13 21:33:08 +00:00
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.addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
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.addReg(Reg2, getKillRegState(Reg2IsKill))
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.addReg(Reg1, getKillRegState(Reg1IsKill))
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2008-06-16 07:33:11 +00:00
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.addImm((ME+1) & 31)
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.addImm((MB-1) & 31);
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2008-02-13 02:46:49 +00:00
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}
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2008-06-16 07:33:11 +00:00
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if (ChangeReg0)
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MI->getOperand(0).setReg(Reg2);
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2006-05-04 17:52:23 +00:00
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MI->getOperand(2).setReg(Reg1);
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MI->getOperand(1).setReg(Reg2);
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2007-12-30 21:56:09 +00:00
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MI->getOperand(2).setIsKill(Reg1IsKill);
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MI->getOperand(1).setIsKill(Reg2IsKill);
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2010-12-24 04:28:06 +00:00
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2005-09-09 18:17:41 +00:00
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// Swap the mask around.
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2007-12-30 20:49:49 +00:00
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MI->getOperand(4).setImm((ME+1) & 31);
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MI->getOperand(5).setImm((MB-1) & 31);
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2005-09-09 18:17:41 +00:00
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return MI;
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}
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2006-03-05 23:49:55 +00:00
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2010-12-24 04:28:06 +00:00
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void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
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2006-03-05 23:49:55 +00:00
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MachineBasicBlock::iterator MI) const {
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2010-04-02 20:16:16 +00:00
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DebugLoc DL;
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2009-02-12 00:02:55 +00:00
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BuildMI(MBB, MI, DL, get(PPC::NOP));
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2006-03-05 23:49:55 +00:00
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}
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2006-10-13 21:21:17 +00:00
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// Branch analysis.
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2012-06-08 15:38:21 +00:00
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// Note: If the condition register is set to CTR or CTR8 then this is a
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// BDNZ (imm == 1) or BDZ (imm == 0) branch.
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2006-10-13 21:21:17 +00:00
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bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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2009-02-09 07:14:22 +00:00
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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2012-06-08 15:38:21 +00:00
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bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
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2006-10-13 21:21:17 +00:00
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.end();
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2010-04-02 01:38:09 +00:00
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if (I == MBB.begin())
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return false;
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--I;
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while (I->isDebugValue()) {
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if (I == MBB.begin())
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return false;
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--I;
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}
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if (!isUnpredicatedTerminator(I))
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2006-10-13 21:21:17 +00:00
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return false;
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// Get the last instruction in the block.
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MachineInstr *LastInst = I;
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2010-12-24 04:28:06 +00:00
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2006-10-13 21:21:17 +00:00
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|
|
// If there is only one terminator instruction, process it.
|
2007-06-08 21:59:56 +00:00
|
|
|
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
|
2006-10-13 21:21:17 +00:00
|
|
|
if (LastInst->getOpcode() == PPC::B) {
|
2009-05-08 23:09:25 +00:00
|
|
|
if (!LastInst->getOperand(0).isMBB())
|
|
|
|
return true;
|
2007-12-30 23:10:15 +00:00
|
|
|
TBB = LastInst->getOperand(0).getMBB();
|
2006-10-13 21:21:17 +00:00
|
|
|
return false;
|
2006-11-17 22:14:47 +00:00
|
|
|
} else if (LastInst->getOpcode() == PPC::BCC) {
|
2009-05-08 23:09:25 +00:00
|
|
|
if (!LastInst->getOperand(2).isMBB())
|
|
|
|
return true;
|
2006-10-13 21:21:17 +00:00
|
|
|
// Block ends with fall-through condbranch.
|
2007-12-30 23:10:15 +00:00
|
|
|
TBB = LastInst->getOperand(2).getMBB();
|
2006-10-13 21:21:17 +00:00
|
|
|
Cond.push_back(LastInst->getOperand(0));
|
|
|
|
Cond.push_back(LastInst->getOperand(1));
|
2006-10-21 06:03:11 +00:00
|
|
|
return false;
|
2012-06-08 15:38:21 +00:00
|
|
|
} else if (LastInst->getOpcode() == PPC::BDNZ8 ||
|
|
|
|
LastInst->getOpcode() == PPC::BDNZ) {
|
|
|
|
if (!LastInst->getOperand(0).isMBB())
|
|
|
|
return true;
|
2012-06-08 19:19:53 +00:00
|
|
|
if (DisableCTRLoopAnal)
|
2012-06-08 15:38:25 +00:00
|
|
|
return true;
|
2012-06-08 15:38:21 +00:00
|
|
|
TBB = LastInst->getOperand(0).getMBB();
|
|
|
|
Cond.push_back(MachineOperand::CreateImm(1));
|
|
|
|
Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
|
|
|
|
true));
|
|
|
|
return false;
|
|
|
|
} else if (LastInst->getOpcode() == PPC::BDZ8 ||
|
|
|
|
LastInst->getOpcode() == PPC::BDZ) {
|
|
|
|
if (!LastInst->getOperand(0).isMBB())
|
|
|
|
return true;
|
2012-06-08 19:19:53 +00:00
|
|
|
if (DisableCTRLoopAnal)
|
2012-06-08 15:38:25 +00:00
|
|
|
return true;
|
2012-06-08 15:38:21 +00:00
|
|
|
TBB = LastInst->getOperand(0).getMBB();
|
|
|
|
Cond.push_back(MachineOperand::CreateImm(0));
|
|
|
|
Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
|
|
|
|
true));
|
|
|
|
return false;
|
2006-10-13 21:21:17 +00:00
|
|
|
}
|
2012-06-08 15:38:21 +00:00
|
|
|
|
2006-10-13 21:21:17 +00:00
|
|
|
// Otherwise, don't know what this is.
|
|
|
|
return true;
|
|
|
|
}
|
2010-12-24 04:28:06 +00:00
|
|
|
|
2006-10-13 21:21:17 +00:00
|
|
|
// Get the instruction before it if it's a terminator.
|
|
|
|
MachineInstr *SecondLastInst = I;
|
|
|
|
|
|
|
|
// If there are three terminators, we don't know what sort of block this is.
|
|
|
|
if (SecondLastInst && I != MBB.begin() &&
|
2007-06-08 21:59:56 +00:00
|
|
|
isUnpredicatedTerminator(--I))
|
2006-10-13 21:21:17 +00:00
|
|
|
return true;
|
2010-12-24 04:28:06 +00:00
|
|
|
|
2006-11-17 22:14:47 +00:00
|
|
|
// If the block ends with PPC::B and PPC:BCC, handle it.
|
2010-12-24 04:28:06 +00:00
|
|
|
if (SecondLastInst->getOpcode() == PPC::BCC &&
|
2006-10-13 21:21:17 +00:00
|
|
|
LastInst->getOpcode() == PPC::B) {
|
2009-05-08 23:09:25 +00:00
|
|
|
if (!SecondLastInst->getOperand(2).isMBB() ||
|
|
|
|
!LastInst->getOperand(0).isMBB())
|
|
|
|
return true;
|
2007-12-30 23:10:15 +00:00
|
|
|
TBB = SecondLastInst->getOperand(2).getMBB();
|
2006-10-13 21:21:17 +00:00
|
|
|
Cond.push_back(SecondLastInst->getOperand(0));
|
|
|
|
Cond.push_back(SecondLastInst->getOperand(1));
|
2007-12-30 23:10:15 +00:00
|
|
|
FBB = LastInst->getOperand(0).getMBB();
|
2006-10-13 21:21:17 +00:00
|
|
|
return false;
|
2012-06-08 15:38:21 +00:00
|
|
|
} else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 ||
|
|
|
|
SecondLastInst->getOpcode() == PPC::BDNZ) &&
|
|
|
|
LastInst->getOpcode() == PPC::B) {
|
|
|
|
if (!SecondLastInst->getOperand(0).isMBB() ||
|
|
|
|
!LastInst->getOperand(0).isMBB())
|
|
|
|
return true;
|
2012-06-08 19:19:53 +00:00
|
|
|
if (DisableCTRLoopAnal)
|
2012-06-08 15:38:25 +00:00
|
|
|
return true;
|
2012-06-08 15:38:21 +00:00
|
|
|
TBB = SecondLastInst->getOperand(0).getMBB();
|
|
|
|
Cond.push_back(MachineOperand::CreateImm(1));
|
|
|
|
Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
|
|
|
|
true));
|
|
|
|
FBB = LastInst->getOperand(0).getMBB();
|
|
|
|
return false;
|
|
|
|
} else if ((SecondLastInst->getOpcode() == PPC::BDZ8 ||
|
|
|
|
SecondLastInst->getOpcode() == PPC::BDZ) &&
|
|
|
|
LastInst->getOpcode() == PPC::B) {
|
|
|
|
if (!SecondLastInst->getOperand(0).isMBB() ||
|
|
|
|
!LastInst->getOperand(0).isMBB())
|
|
|
|
return true;
|
2012-06-08 19:19:53 +00:00
|
|
|
if (DisableCTRLoopAnal)
|
2012-06-08 15:38:25 +00:00
|
|
|
return true;
|
2012-06-08 15:38:21 +00:00
|
|
|
TBB = SecondLastInst->getOperand(0).getMBB();
|
|
|
|
Cond.push_back(MachineOperand::CreateImm(0));
|
|
|
|
Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
|
|
|
|
true));
|
|
|
|
FBB = LastInst->getOperand(0).getMBB();
|
|
|
|
return false;
|
2006-10-13 21:21:17 +00:00
|
|
|
}
|
2010-12-24 04:28:06 +00:00
|
|
|
|
2007-06-13 17:59:52 +00:00
|
|
|
// If the block ends with two PPC:Bs, handle it. The second one is not
|
|
|
|
// executed, so remove it.
|
2010-12-24 04:28:06 +00:00
|
|
|
if (SecondLastInst->getOpcode() == PPC::B &&
|
2007-06-13 17:59:52 +00:00
|
|
|
LastInst->getOpcode() == PPC::B) {
|
2009-05-08 23:09:25 +00:00
|
|
|
if (!SecondLastInst->getOperand(0).isMBB())
|
|
|
|
return true;
|
2007-12-30 23:10:15 +00:00
|
|
|
TBB = SecondLastInst->getOperand(0).getMBB();
|
2007-06-13 17:59:52 +00:00
|
|
|
I = LastInst;
|
2009-02-09 07:14:22 +00:00
|
|
|
if (AllowModify)
|
|
|
|
I->eraseFromParent();
|
2007-06-13 17:59:52 +00:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2006-10-13 21:21:17 +00:00
|
|
|
// Otherwise, can't handle this.
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2007-05-18 00:05:48 +00:00
|
|
|
unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
|
2006-10-13 21:21:17 +00:00
|
|
|
MachineBasicBlock::iterator I = MBB.end();
|
2007-05-18 00:05:48 +00:00
|
|
|
if (I == MBB.begin()) return 0;
|
2006-10-13 21:21:17 +00:00
|
|
|
--I;
|
2010-04-02 01:38:09 +00:00
|
|
|
while (I->isDebugValue()) {
|
|
|
|
if (I == MBB.begin())
|
|
|
|
return 0;
|
|
|
|
--I;
|
|
|
|
}
|
2012-06-08 15:38:21 +00:00
|
|
|
if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
|
|
|
|
I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
|
|
|
|
I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
|
2007-05-18 00:05:48 +00:00
|
|
|
return 0;
|
2010-12-24 04:28:06 +00:00
|
|
|
|
2006-10-13 21:21:17 +00:00
|
|
|
// Remove the branch.
|
|
|
|
I->eraseFromParent();
|
2010-12-24 04:28:06 +00:00
|
|
|
|
2006-10-13 21:21:17 +00:00
|
|
|
I = MBB.end();
|
|
|
|
|
2007-05-18 00:05:48 +00:00
|
|
|
if (I == MBB.begin()) return 1;
|
2006-10-13 21:21:17 +00:00
|
|
|
--I;
|
2012-06-08 15:38:21 +00:00
|
|
|
if (I->getOpcode() != PPC::BCC &&
|
|
|
|
I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
|
|
|
|
I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
|
2007-05-18 00:05:48 +00:00
|
|
|
return 1;
|
2010-12-24 04:28:06 +00:00
|
|
|
|
2006-10-13 21:21:17 +00:00
|
|
|
// Remove the branch.
|
|
|
|
I->eraseFromParent();
|
2007-05-18 00:05:48 +00:00
|
|
|
return 2;
|
2006-10-13 21:21:17 +00:00
|
|
|
}
|
|
|
|
|
2007-05-18 00:05:48 +00:00
|
|
|
unsigned
|
|
|
|
PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
|
|
|
MachineBasicBlock *FBB,
|
2010-06-17 22:43:56 +00:00
|
|
|
const SmallVectorImpl<MachineOperand> &Cond,
|
|
|
|
DebugLoc DL) const {
|
2006-10-17 18:06:55 +00:00
|
|
|
// Shouldn't be a fall through.
|
|
|
|
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
2010-12-24 04:28:06 +00:00
|
|
|
assert((Cond.size() == 2 || Cond.size() == 0) &&
|
2006-10-21 05:36:13 +00:00
|
|
|
"PPC branch conditions have two components!");
|
2010-12-24 04:28:06 +00:00
|
|
|
|
2012-06-08 15:38:21 +00:00
|
|
|
bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
|
|
|
|
|
2006-10-21 05:36:13 +00:00
|
|
|
// One-way branch.
|
2006-10-17 18:06:55 +00:00
|
|
|
if (FBB == 0) {
|
2006-10-21 05:36:13 +00:00
|
|
|
if (Cond.empty()) // Unconditional branch
|
2010-06-17 22:43:56 +00:00
|
|
|
BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
|
2012-06-08 15:38:21 +00:00
|
|
|
else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
|
|
|
|
BuildMI(&MBB, DL, get(Cond[0].getImm() ?
|
|
|
|
(isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
|
|
|
|
(isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
|
2006-10-21 05:36:13 +00:00
|
|
|
else // Conditional branch
|
2010-06-17 22:43:56 +00:00
|
|
|
BuildMI(&MBB, DL, get(PPC::BCC))
|
2006-11-17 22:37:34 +00:00
|
|
|
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
|
2007-05-18 00:05:48 +00:00
|
|
|
return 1;
|
2006-10-17 18:06:55 +00:00
|
|
|
}
|
2010-12-24 04:28:06 +00:00
|
|
|
|
2006-10-21 05:42:09 +00:00
|
|
|
// Two-way Conditional Branch.
|
2012-06-08 15:38:21 +00:00
|
|
|
if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
|
|
|
|
BuildMI(&MBB, DL, get(Cond[0].getImm() ?
|
|
|
|
(isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
|
|
|
|
(isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
|
|
|
|
else
|
|
|
|
BuildMI(&MBB, DL, get(PPC::BCC))
|
|
|
|
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
|
2010-06-17 22:43:56 +00:00
|
|
|
BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
|
2007-05-18 00:05:48 +00:00
|
|
|
return 2;
|
2006-10-13 21:21:17 +00:00
|
|
|
}
|
|
|
|
|
2010-07-11 07:31:00 +00:00
|
|
|
void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator I, DebugLoc DL,
|
|
|
|
unsigned DestReg, unsigned SrcReg,
|
|
|
|
bool KillSrc) const {
|
|
|
|
unsigned Opc;
|
|
|
|
if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
|
|
|
|
Opc = PPC::OR;
|
|
|
|
else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
|
|
|
|
Opc = PPC::OR8;
|
|
|
|
else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
|
|
|
|
Opc = PPC::FMR;
|
|
|
|
else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
|
|
|
|
Opc = PPC::MCRF;
|
|
|
|
else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
|
|
|
|
Opc = PPC::VOR;
|
|
|
|
else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
|
|
|
|
Opc = PPC::CROR;
|
|
|
|
else
|
|
|
|
llvm_unreachable("Impossible reg-to-reg copy");
|
2007-12-31 06:32:00 +00:00
|
|
|
|
2011-06-28 19:10:37 +00:00
|
|
|
const MCInstrDesc &MCID = get(Opc);
|
|
|
|
if (MCID.getNumOperands() == 3)
|
|
|
|
BuildMI(MBB, I, DL, MCID, DestReg)
|
2010-07-11 07:31:00 +00:00
|
|
|
.addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
|
|
|
|
else
|
2011-06-28 19:10:37 +00:00
|
|
|
BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
|
2007-12-31 06:32:00 +00:00
|
|
|
}
|
|
|
|
|
2011-12-05 17:55:17 +00:00
|
|
|
// This function returns true if a CR spill is necessary and false otherwise.
|
2008-03-10 22:49:16 +00:00
|
|
|
bool
|
2008-07-07 23:14:23 +00:00
|
|
|
PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
|
|
|
|
unsigned SrcReg, bool isKill,
|
2008-03-10 22:49:16 +00:00
|
|
|
int FrameIdx,
|
|
|
|
const TargetRegisterClass *RC,
|
2013-03-17 04:43:44 +00:00
|
|
|
SmallVectorImpl<MachineInstr*> &NewMIs,
|
2013-03-23 22:06:03 +00:00
|
|
|
bool &NonRI, bool &SpillsVRS) const{
|
2013-03-27 21:21:15 +00:00
|
|
|
// Note: If additional store instructions are added here,
|
|
|
|
// update isStoreToStackSlot.
|
|
|
|
|
2010-04-02 20:16:16 +00:00
|
|
|
DebugLoc DL;
|
2012-04-20 06:31:50 +00:00
|
|
|
if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
|
2013-03-23 17:14:27 +00:00
|
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
|
|
|
|
.addReg(SrcReg,
|
|
|
|
getKillRegState(isKill)),
|
|
|
|
FrameIdx));
|
2012-04-20 06:31:50 +00:00
|
|
|
} else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
|
2013-03-23 17:14:27 +00:00
|
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
|
|
|
|
.addReg(SrcReg,
|
|
|
|
getKillRegState(isKill)),
|
|
|
|
FrameIdx));
|
2012-04-20 06:31:50 +00:00
|
|
|
} else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
|
2009-02-12 23:08:38 +00:00
|
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
|
2009-05-13 21:33:08 +00:00
|
|
|
.addReg(SrcReg,
|
|
|
|
getKillRegState(isKill)),
|
|
|
|
FrameIdx));
|
2012-04-20 06:31:50 +00:00
|
|
|
} else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
|
2009-02-12 23:08:38 +00:00
|
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
|
2009-05-13 21:33:08 +00:00
|
|
|
.addReg(SrcReg,
|
|
|
|
getKillRegState(isKill)),
|
|
|
|
FrameIdx));
|
2012-04-20 06:31:50 +00:00
|
|
|
} else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
|
2013-03-12 14:12:16 +00:00
|
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
|
|
|
|
.addReg(SrcReg,
|
|
|
|
getKillRegState(isKill)),
|
|
|
|
FrameIdx));
|
|
|
|
return true;
|
2012-04-20 06:31:50 +00:00
|
|
|
} else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
|
2008-03-10 14:12:10 +00:00
|
|
|
// FIXME: We use CRi here because there is no mtcrf on a bit. Since the
|
|
|
|
// backend currently only uses CR1EQ as an individual bit, this should
|
|
|
|
// not cause any bug. If we need other uses of CR bits, the following
|
|
|
|
// code may be invalid.
|
2008-03-10 17:46:45 +00:00
|
|
|
unsigned Reg = 0;
|
2009-07-03 06:47:55 +00:00
|
|
|
if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
|
|
|
|
SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
|
2008-03-10 17:46:45 +00:00
|
|
|
Reg = PPC::CR0;
|
2009-07-03 06:47:55 +00:00
|
|
|
else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
|
|
|
|
SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
|
2008-03-10 17:46:45 +00:00
|
|
|
Reg = PPC::CR1;
|
2009-07-03 06:47:55 +00:00
|
|
|
else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
|
|
|
|
SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
|
2008-03-10 17:46:45 +00:00
|
|
|
Reg = PPC::CR2;
|
2009-07-03 06:47:55 +00:00
|
|
|
else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
|
|
|
|
SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
|
2008-03-10 17:46:45 +00:00
|
|
|
Reg = PPC::CR3;
|
2009-07-03 06:47:55 +00:00
|
|
|
else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
|
|
|
|
SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
|
2008-03-10 17:46:45 +00:00
|
|
|
Reg = PPC::CR4;
|
2009-07-03 06:47:55 +00:00
|
|
|
else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
|
|
|
|
SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
|
2008-03-10 17:46:45 +00:00
|
|
|
Reg = PPC::CR5;
|
2009-07-03 06:47:55 +00:00
|
|
|
else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
|
|
|
|
SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
|
2008-03-10 17:46:45 +00:00
|
|
|
Reg = PPC::CR6;
|
2009-07-03 06:47:55 +00:00
|
|
|
else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
|
|
|
|
SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
|
2008-03-10 17:46:45 +00:00
|
|
|
Reg = PPC::CR7;
|
|
|
|
|
2010-12-24 04:28:06 +00:00
|
|
|
return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
|
2013-03-23 22:06:03 +00:00
|
|
|
&PPC::CRRCRegClass, NewMIs, NonRI, SpillsVRS);
|
2008-03-10 17:46:45 +00:00
|
|
|
|
2012-04-20 06:31:50 +00:00
|
|
|
} else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
|
2013-03-17 04:43:44 +00:00
|
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
|
|
|
|
.addReg(SrcReg,
|
|
|
|
getKillRegState(isKill)),
|
|
|
|
FrameIdx));
|
|
|
|
NonRI = true;
|
2013-03-21 19:03:21 +00:00
|
|
|
} else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
|
2013-03-27 00:02:20 +00:00
|
|
|
assert(TM.getSubtargetImpl()->isDarwin() &&
|
|
|
|
"VRSAVE only needs spill/restore on Darwin");
|
2013-03-21 19:03:21 +00:00
|
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE))
|
|
|
|
.addReg(SrcReg,
|
|
|
|
getKillRegState(isKill)),
|
|
|
|
FrameIdx));
|
2013-03-23 22:06:03 +00:00
|
|
|
SpillsVRS = true;
|
2008-01-01 21:11:32 +00:00
|
|
|
} else {
|
2009-07-14 16:55:14 +00:00
|
|
|
llvm_unreachable("Unknown regclass!");
|
2008-01-01 21:11:32 +00:00
|
|
|
}
|
2008-03-03 22:19:16 +00:00
|
|
|
|
|
|
|
return false;
|
2008-01-01 21:11:32 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
2008-03-03 22:19:16 +00:00
|
|
|
MachineBasicBlock::iterator MI,
|
|
|
|
unsigned SrcReg, bool isKill, int FrameIdx,
|
2010-05-06 19:06:44 +00:00
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
const TargetRegisterInfo *TRI) const {
|
2008-07-07 23:14:23 +00:00
|
|
|
MachineFunction &MF = *MBB.getParent();
|
2008-01-01 21:11:32 +00:00
|
|
|
SmallVector<MachineInstr*, 4> NewMIs;
|
2008-03-03 22:19:16 +00:00
|
|
|
|
2013-03-15 05:06:04 +00:00
|
|
|
PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
|
|
|
|
FuncInfo->setHasSpills();
|
|
|
|
|
2013-03-23 22:06:03 +00:00
|
|
|
bool NonRI = false, SpillsVRS = false;
|
|
|
|
if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
|
|
|
|
NonRI, SpillsVRS))
|
2008-03-03 22:19:16 +00:00
|
|
|
FuncInfo->setSpillsCR();
|
|
|
|
|
2013-03-23 22:06:03 +00:00
|
|
|
if (SpillsVRS)
|
|
|
|
FuncInfo->setSpillsVRSAVE();
|
|
|
|
|
2013-03-17 04:43:44 +00:00
|
|
|
if (NonRI)
|
|
|
|
FuncInfo->setHasNonRISpills();
|
|
|
|
|
2008-01-01 21:11:32 +00:00
|
|
|
for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
|
|
|
|
MBB.insert(MI, NewMIs[i]);
|
2010-07-16 18:22:00 +00:00
|
|
|
|
|
|
|
const MachineFrameInfo &MFI = *MF.getFrameInfo();
|
|
|
|
MachineMemOperand *MMO =
|
2011-11-15 07:34:52 +00:00
|
|
|
MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
|
2010-09-21 04:39:43 +00:00
|
|
|
MachineMemOperand::MOStore,
|
2010-07-16 18:22:00 +00:00
|
|
|
MFI.getObjectSize(FrameIdx),
|
|
|
|
MFI.getObjectAlignment(FrameIdx));
|
|
|
|
NewMIs.back()->addMemOperand(MF, MMO);
|
2008-01-01 21:11:32 +00:00
|
|
|
}
|
|
|
|
|
2011-12-06 20:55:36 +00:00
|
|
|
bool
|
2009-02-12 00:02:55 +00:00
|
|
|
PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
|
2008-07-07 23:14:23 +00:00
|
|
|
unsigned DestReg, int FrameIdx,
|
2008-03-10 22:49:16 +00:00
|
|
|
const TargetRegisterClass *RC,
|
2013-03-17 04:43:44 +00:00
|
|
|
SmallVectorImpl<MachineInstr*> &NewMIs,
|
2013-03-23 22:06:03 +00:00
|
|
|
bool &NonRI, bool &SpillsVRS) const{
|
2013-03-27 21:21:15 +00:00
|
|
|
// Note: If additional load instructions are added here,
|
|
|
|
// update isLoadFromStackSlot.
|
|
|
|
|
2012-04-20 06:31:50 +00:00
|
|
|
if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
|
2013-03-27 19:10:40 +00:00
|
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
|
|
|
|
DestReg), FrameIdx));
|
2012-04-20 06:31:50 +00:00
|
|
|
} else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
|
2013-03-27 19:10:40 +00:00
|
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
|
|
|
|
FrameIdx));
|
2012-04-20 06:31:50 +00:00
|
|
|
} else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
|
2009-02-12 00:02:55 +00:00
|
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
|
2008-01-01 21:11:32 +00:00
|
|
|
FrameIdx));
|
2012-04-20 06:31:50 +00:00
|
|
|
} else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
|
2009-02-12 00:02:55 +00:00
|
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
|
2008-01-01 21:11:32 +00:00
|
|
|
FrameIdx));
|
2012-04-20 06:31:50 +00:00
|
|
|
} else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
|
2013-03-12 14:12:16 +00:00
|
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
|
|
|
|
get(PPC::RESTORE_CR), DestReg),
|
|
|
|
FrameIdx));
|
|
|
|
return true;
|
2012-04-20 06:31:50 +00:00
|
|
|
} else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
|
2010-12-24 04:28:06 +00:00
|
|
|
|
2008-03-10 17:46:45 +00:00
|
|
|
unsigned Reg = 0;
|
2009-07-03 06:47:55 +00:00
|
|
|
if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
|
|
|
|
DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
|
2008-03-10 17:46:45 +00:00
|
|
|
Reg = PPC::CR0;
|
2009-07-03 06:47:55 +00:00
|
|
|
else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
|
|
|
|
DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
|
2008-03-10 17:46:45 +00:00
|
|
|
Reg = PPC::CR1;
|
2009-07-03 06:47:55 +00:00
|
|
|
else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
|
|
|
|
DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
|
2008-03-10 17:46:45 +00:00
|
|
|
Reg = PPC::CR2;
|
2009-07-03 06:47:55 +00:00
|
|
|
else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
|
|
|
|
DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
|
2008-03-10 17:46:45 +00:00
|
|
|
Reg = PPC::CR3;
|
2009-07-03 06:47:55 +00:00
|
|
|
else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
|
|
|
|
DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
|
2008-03-10 17:46:45 +00:00
|
|
|
Reg = PPC::CR4;
|
2009-07-03 06:47:55 +00:00
|
|
|
else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
|
|
|
|
DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
|
2008-03-10 17:46:45 +00:00
|
|
|
Reg = PPC::CR5;
|
2009-07-03 06:47:55 +00:00
|
|
|
else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
|
|
|
|
DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
|
2008-03-10 17:46:45 +00:00
|
|
|
Reg = PPC::CR6;
|
2009-07-03 06:47:55 +00:00
|
|
|
else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
|
|
|
|
DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
|
2008-03-10 17:46:45 +00:00
|
|
|
Reg = PPC::CR7;
|
|
|
|
|
2010-12-24 04:28:06 +00:00
|
|
|
return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
|
2013-03-23 22:06:03 +00:00
|
|
|
&PPC::CRRCRegClass, NewMIs, NonRI, SpillsVRS);
|
2008-03-10 17:46:45 +00:00
|
|
|
|
2012-04-20 06:31:50 +00:00
|
|
|
} else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
|
2013-03-17 04:43:44 +00:00
|
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg),
|
|
|
|
FrameIdx));
|
|
|
|
NonRI = true;
|
2013-03-21 19:03:21 +00:00
|
|
|
} else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
|
2013-03-27 00:02:20 +00:00
|
|
|
assert(TM.getSubtargetImpl()->isDarwin() &&
|
|
|
|
"VRSAVE only needs spill/restore on Darwin");
|
2013-03-21 19:03:21 +00:00
|
|
|
NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
|
|
|
|
get(PPC::RESTORE_VRSAVE),
|
|
|
|
DestReg),
|
|
|
|
FrameIdx));
|
2013-03-23 22:06:03 +00:00
|
|
|
SpillsVRS = true;
|
2008-01-01 21:11:32 +00:00
|
|
|
} else {
|
2009-07-14 16:55:14 +00:00
|
|
|
llvm_unreachable("Unknown regclass!");
|
2008-01-01 21:11:32 +00:00
|
|
|
}
|
2011-12-06 20:55:36 +00:00
|
|
|
|
|
|
|
return false;
|
2008-01-01 21:11:32 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
2008-03-03 22:19:16 +00:00
|
|
|
MachineBasicBlock::iterator MI,
|
|
|
|
unsigned DestReg, int FrameIdx,
|
2010-05-06 19:06:44 +00:00
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
const TargetRegisterInfo *TRI) const {
|
2008-07-07 23:14:23 +00:00
|
|
|
MachineFunction &MF = *MBB.getParent();
|
2008-01-01 21:11:32 +00:00
|
|
|
SmallVector<MachineInstr*, 4> NewMIs;
|
2010-04-02 20:16:16 +00:00
|
|
|
DebugLoc DL;
|
2009-02-12 00:02:55 +00:00
|
|
|
if (MI != MBB.end()) DL = MI->getDebugLoc();
|
2013-03-17 04:43:44 +00:00
|
|
|
|
|
|
|
PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
|
|
|
|
FuncInfo->setHasSpills();
|
|
|
|
|
2013-03-23 22:06:03 +00:00
|
|
|
bool NonRI = false, SpillsVRS = false;
|
|
|
|
if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs,
|
|
|
|
NonRI, SpillsVRS))
|
2011-12-06 20:55:36 +00:00
|
|
|
FuncInfo->setSpillsCR();
|
2013-03-17 04:43:44 +00:00
|
|
|
|
2013-03-23 22:06:03 +00:00
|
|
|
if (SpillsVRS)
|
|
|
|
FuncInfo->setSpillsVRSAVE();
|
|
|
|
|
2013-03-17 04:43:44 +00:00
|
|
|
if (NonRI)
|
|
|
|
FuncInfo->setHasNonRISpills();
|
|
|
|
|
2008-01-01 21:11:32 +00:00
|
|
|
for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
|
|
|
|
MBB.insert(MI, NewMIs[i]);
|
2010-07-16 18:22:00 +00:00
|
|
|
|
|
|
|
const MachineFrameInfo &MFI = *MF.getFrameInfo();
|
|
|
|
MachineMemOperand *MMO =
|
2011-11-15 07:34:52 +00:00
|
|
|
MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
|
2010-09-21 04:39:43 +00:00
|
|
|
MachineMemOperand::MOLoad,
|
2010-07-16 18:22:00 +00:00
|
|
|
MFI.getObjectSize(FrameIdx),
|
|
|
|
MFI.getObjectAlignment(FrameIdx));
|
|
|
|
NewMIs.back()->addMemOperand(MF, MMO);
|
2008-01-01 21:11:32 +00:00
|
|
|
}
|
|
|
|
|
2010-04-26 07:39:36 +00:00
|
|
|
MachineInstr*
|
|
|
|
PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
|
2010-04-29 01:13:30 +00:00
|
|
|
int FrameIx, uint64_t Offset,
|
2010-04-26 07:39:36 +00:00
|
|
|
const MDNode *MDPtr,
|
|
|
|
DebugLoc DL) const {
|
|
|
|
MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
|
|
|
|
addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
|
|
|
|
return &*MIB;
|
|
|
|
}
|
|
|
|
|
2006-10-13 21:21:17 +00:00
|
|
|
bool PPCInstrInfo::
|
2008-08-14 22:49:33 +00:00
|
|
|
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
|
2006-10-21 06:03:11 +00:00
|
|
|
assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
|
2012-06-08 15:38:21 +00:00
|
|
|
if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
|
|
|
|
Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
|
|
|
|
else
|
|
|
|
// Leave the CR# the same, but invert the condition.
|
|
|
|
Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
|
2006-10-21 06:03:11 +00:00
|
|
|
return false;
|
2006-10-13 21:21:17 +00:00
|
|
|
}
|
2008-04-16 20:10:13 +00:00
|
|
|
|
|
|
|
/// GetInstSize - Return the number of bytes of code the specified
|
|
|
|
/// instruction may be. This returns the maximum number of bytes.
|
|
|
|
///
|
|
|
|
unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
|
|
|
|
switch (MI->getOpcode()) {
|
|
|
|
case PPC::INLINEASM: { // Inline Asm: Variable size.
|
|
|
|
const MachineFunction *MF = MI->getParent()->getParent();
|
|
|
|
const char *AsmStr = MI->getOperand(0).getSymbolName();
|
2009-08-22 20:48:53 +00:00
|
|
|
return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
|
2008-04-16 20:10:13 +00:00
|
|
|
}
|
2010-07-16 22:20:36 +00:00
|
|
|
case PPC::PROLOG_LABEL:
|
2008-07-01 00:05:16 +00:00
|
|
|
case PPC::EH_LABEL:
|
|
|
|
case PPC::GC_LABEL:
|
2010-04-07 19:51:44 +00:00
|
|
|
case PPC::DBG_VALUE:
|
2008-04-16 20:10:13 +00:00
|
|
|
return 0;
|
2013-03-22 15:24:13 +00:00
|
|
|
case PPC::BL8_NOP:
|
|
|
|
case PPC::BLA8_NOP:
|
2012-03-31 14:45:15 +00:00
|
|
|
return 8;
|
2008-04-16 20:10:13 +00:00
|
|
|
default:
|
|
|
|
return 4; // PowerPC instructions are all 4 bytes
|
|
|
|
}
|
|
|
|
}
|