2011-04-15 21:51:11 +00:00
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//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
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2007-06-06 07:42:06 +00:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 20:36:04 +00:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-06-06 07:42:06 +00:00
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//
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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//
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// This file defines the interfaces that Mips uses to lower LLVM code into a
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// selection DAG.
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//
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2011-04-15 21:51:11 +00:00
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//===----------------------------------------------------------------------===//
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2007-06-06 07:42:06 +00:00
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#define DEBUG_TYPE "mips-lower"
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#include "MipsISelLowering.h"
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2007-08-28 05:08:16 +00:00
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#include "MipsMachineFunction.h"
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2007-06-06 07:42:06 +00:00
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#include "MipsTargetMachine.h"
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2009-08-13 06:28:06 +00:00
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#include "MipsTargetObjectFile.h"
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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#include "MipsSubtarget.h"
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2007-06-06 07:42:06 +00:00
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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2008-07-21 18:52:34 +00:00
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#include "llvm/GlobalVariable.h"
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2007-06-06 07:42:06 +00:00
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#include "llvm/Intrinsics.h"
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#include "llvm/CallingConv.h"
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2011-07-07 23:56:50 +00:00
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#include "InstPrinter/MipsInstPrinter.h"
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2011-11-11 22:58:42 +00:00
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#include "MCTargetDesc/MipsBaseInfo.h"
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2007-06-06 07:42:06 +00:00
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2007-12-31 04:13:23 +00:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2007-06-06 07:42:06 +00:00
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/Support/Debug.h"
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2009-07-11 20:10:48 +00:00
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#include "llvm/Support/ErrorHandling.h"
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2007-06-06 07:42:06 +00:00
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using namespace llvm;
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2011-08-18 20:07:42 +00:00
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// If I is a shifted mask, set the size (Size) and the first bit of the
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// mask (Pos), and return true.
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2011-08-19 22:59:00 +00:00
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// For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
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static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
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if (!isUInt<32>(I) || !isShiftedMask_32(I))
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return false;
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2011-08-17 02:05:42 +00:00
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2011-08-19 22:59:00 +00:00
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Size = CountPopulation_32(I);
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Pos = CountTrailingZeros_32(I);
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2011-08-18 20:07:42 +00:00
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return true;
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2011-08-17 02:05:42 +00:00
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}
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2009-07-28 03:13:23 +00:00
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const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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2011-05-23 21:13:59 +00:00
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case MipsISD::JmpLink: return "MipsISD::JmpLink";
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case MipsISD::Hi: return "MipsISD::Hi";
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case MipsISD::Lo: return "MipsISD::Lo";
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case MipsISD::GPRel: return "MipsISD::GPRel";
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2011-05-31 02:53:58 +00:00
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case MipsISD::TlsGd: return "MipsISD::TlsGd";
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case MipsISD::TprelHi: return "MipsISD::TprelHi";
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case MipsISD::TprelLo: return "MipsISD::TprelLo";
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case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
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2011-05-23 21:13:59 +00:00
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case MipsISD::Ret: return "MipsISD::Ret";
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case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
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case MipsISD::FPCmp: return "MipsISD::FPCmp";
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case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
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case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
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case MipsISD::FPRound: return "MipsISD::FPRound";
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case MipsISD::MAdd: return "MipsISD::MAdd";
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case MipsISD::MAddu: return "MipsISD::MAddu";
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case MipsISD::MSub: return "MipsISD::MSub";
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case MipsISD::MSubu: return "MipsISD::MSubu";
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case MipsISD::DivRem: return "MipsISD::DivRem";
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case MipsISD::DivRemU: return "MipsISD::DivRemU";
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case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
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case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
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2011-05-28 01:07:07 +00:00
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case MipsISD::WrapperPIC: return "MipsISD::WrapperPIC";
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2011-06-21 00:40:49 +00:00
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case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
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2011-07-19 23:30:50 +00:00
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case MipsISD::Sync: return "MipsISD::Sync";
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2011-08-17 02:05:42 +00:00
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case MipsISD::Ext: return "MipsISD::Ext";
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case MipsISD::Ins: return "MipsISD::Ins";
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2011-06-07 18:58:42 +00:00
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default: return NULL;
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2007-06-06 07:42:06 +00:00
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}
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}
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MipsTargetLowering::
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2009-07-28 03:13:23 +00:00
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MipsTargetLowering(MipsTargetMachine &TM)
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2011-09-26 21:47:02 +00:00
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: TargetLowering(TM, new MipsTargetObjectFile()),
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Subtarget(&TM.getSubtarget<MipsSubtarget>()),
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2011-10-28 18:47:24 +00:00
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HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()),
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IsO32(Subtarget->isABI_O32()) {
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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2007-06-06 07:42:06 +00:00
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// Mips does not have i1 type, so use i32 for
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2010-11-23 03:31:01 +00:00
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// setcc operations results (slt, sgt, ...).
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2008-11-23 15:47:28 +00:00
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setBooleanContents(ZeroOrOneBooleanContent);
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2011-09-06 19:07:46 +00:00
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setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
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2007-06-06 07:42:06 +00:00
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// Set up the register classes
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2009-08-11 20:47:22 +00:00
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addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
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addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
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2007-06-06 07:42:06 +00:00
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2011-09-24 01:34:44 +00:00
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if (HasMips64)
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addRegisterClass(MVT::i64, Mips::CPU64RegsRegisterClass);
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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// When dealing with single precision only, use libcalls
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2011-09-23 18:28:39 +00:00
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if (!Subtarget->isSingleFloat()) {
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if (HasMips64)
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addRegisterClass(MVT::f64, Mips::FGR64RegisterClass);
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else
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2009-08-11 20:47:22 +00:00
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addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
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2011-09-23 18:28:39 +00:00
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}
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
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2010-11-23 03:31:01 +00:00
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// Load extented operations for i1 types must be promoted
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2009-08-11 20:47:22 +00:00
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setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
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2007-06-06 07:42:06 +00:00
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2009-07-17 04:07:24 +00:00
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// MIPS doesn't have extending float->double load/store
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2009-08-11 20:47:22 +00:00
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setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
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setTruncStoreAction(MVT::f64, MVT::f32, Expand);
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2009-07-17 02:28:12 +00:00
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2010-11-23 03:31:01 +00:00
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// Used by legalize types to correctly generate the setcc result.
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// Without this, every float setcc comes with a AND/OR with the result,
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// we don't want this, since the fpcmp result goes to a flag register,
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2008-07-31 18:31:28 +00:00
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// which is used implicitly by brcond and select operations.
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2009-08-11 20:47:22 +00:00
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AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
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2008-07-31 18:31:28 +00:00
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2008-07-09 04:15:08 +00:00
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// Mips Custom Operations
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2009-08-11 20:47:22 +00:00
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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2011-10-11 00:55:05 +00:00
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setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
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2011-03-04 20:01:52 +00:00
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setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
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2009-08-11 20:47:22 +00:00
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setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
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setOperationAction(ISD::JumpTable, MVT::i32, Custom);
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setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
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setOperationAction(ISD::SELECT, MVT::f32, Custom);
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setOperationAction(ISD::SELECT, MVT::f64, Custom);
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setOperationAction(ISD::SELECT, MVT::i32, Custom);
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setOperationAction(ISD::BRCOND, MVT::Other, Custom);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
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2010-02-06 21:00:02 +00:00
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setOperationAction(ISD::VASTART, MVT::Other, Custom);
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2011-03-04 21:03:24 +00:00
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setOperationAction(ISD::SDIV, MVT::i32, Expand);
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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setOperationAction(ISD::UDIV, MVT::i32, Expand);
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setOperationAction(ISD::UREM, MVT::i32, Expand);
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2011-10-03 21:06:13 +00:00
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setOperationAction(ISD::SDIV, MVT::i64, Expand);
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setOperationAction(ISD::SREM, MVT::i64, Expand);
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setOperationAction(ISD::UDIV, MVT::i64, Expand);
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setOperationAction(ISD::UREM, MVT::i64, Expand);
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2011-03-04 21:03:24 +00:00
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2008-07-09 04:15:08 +00:00
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// Operations not directly supported by Mips.
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2009-08-11 20:47:22 +00:00
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::BR_CC, MVT::Other, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
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setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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setOperationAction(ISD::CTPOP, MVT::i32, Expand);
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setOperationAction(ISD::CTTZ, MVT::i32, Expand);
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setOperationAction(ISD::ROTL, MVT::i32, Expand);
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2011-09-30 18:51:46 +00:00
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setOperationAction(ISD::ROTL, MVT::i64, Expand);
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2010-12-09 17:32:30 +00:00
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2011-09-20 23:53:09 +00:00
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if (!Subtarget->hasMips32r2())
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2010-12-09 17:32:30 +00:00
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setOperationAction(ISD::ROTR, MVT::i32, Expand);
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2011-09-30 18:51:46 +00:00
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if (!Subtarget->hasMips64r2())
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setOperationAction(ISD::ROTR, MVT::i64, Expand);
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2009-08-11 20:47:22 +00:00
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
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2011-05-25 19:32:07 +00:00
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setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
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setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
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2009-08-11 20:47:22 +00:00
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setOperationAction(ISD::FSIN, MVT::f32, Expand);
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2011-03-04 18:54:14 +00:00
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setOperationAction(ISD::FSIN, MVT::f64, Expand);
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2009-08-11 20:47:22 +00:00
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setOperationAction(ISD::FCOS, MVT::f32, Expand);
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2011-03-04 18:54:14 +00:00
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setOperationAction(ISD::FCOS, MVT::f64, Expand);
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2009-08-11 20:47:22 +00:00
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setOperationAction(ISD::FPOWI, MVT::f32, Expand);
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setOperationAction(ISD::FPOW, MVT::f32, Expand);
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2011-05-23 22:23:58 +00:00
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setOperationAction(ISD::FPOW, MVT::f64, Expand);
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2009-08-11 20:47:22 +00:00
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setOperationAction(ISD::FLOG, MVT::f32, Expand);
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|
|
setOperationAction(ISD::FLOG2, MVT::f32, Expand);
|
|
|
|
setOperationAction(ISD::FLOG10, MVT::f32, Expand);
|
|
|
|
setOperationAction(ISD::FEXP, MVT::f32, Expand);
|
2011-07-08 21:39:21 +00:00
|
|
|
setOperationAction(ISD::FMA, MVT::f32, Expand);
|
|
|
|
setOperationAction(ISD::FMA, MVT::f64, Expand);
|
2008-07-09 04:15:08 +00:00
|
|
|
|
2011-05-26 18:59:03 +00:00
|
|
|
setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
|
|
|
|
setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
|
2011-06-08 23:55:35 +00:00
|
|
|
|
2011-03-09 19:22:22 +00:00
|
|
|
setOperationAction(ISD::VAARG, MVT::Other, Expand);
|
|
|
|
setOperationAction(ISD::VACOPY, MVT::Other, Expand);
|
|
|
|
setOperationAction(ISD::VAEND, MVT::Other, Expand);
|
|
|
|
|
2008-07-09 04:15:08 +00:00
|
|
|
// Use the default for now
|
2009-08-11 20:47:22 +00:00
|
|
|
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
|
|
|
|
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
|
2011-07-27 22:21:52 +00:00
|
|
|
|
2011-07-19 23:30:50 +00:00
|
|
|
setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
|
2011-07-27 22:21:52 +00:00
|
|
|
setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
|
2008-07-07 19:11:24 +00:00
|
|
|
|
2011-08-29 18:23:02 +00:00
|
|
|
setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
|
|
|
|
setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
|
|
|
|
|
2011-08-03 21:06:02 +00:00
|
|
|
setInsertFencesForAtomic(true);
|
|
|
|
|
2008-08-04 06:44:31 +00:00
|
|
|
if (Subtarget->isSingleFloat())
|
2009-08-11 20:47:22 +00:00
|
|
|
setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2008-07-09 05:32:22 +00:00
|
|
|
if (!Subtarget->hasSEInReg()) {
|
2009-08-11 20:47:22 +00:00
|
|
|
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
|
|
|
|
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
}
|
|
|
|
|
2008-08-08 06:16:31 +00:00
|
|
|
if (!Subtarget->hasBitCount())
|
2009-08-11 20:47:22 +00:00
|
|
|
setOperationAction(ISD::CTLZ, MVT::i32, Expand);
|
2008-08-08 06:16:31 +00:00
|
|
|
|
2008-08-13 07:13:40 +00:00
|
|
|
if (!Subtarget->hasSwap())
|
2009-08-11 20:47:22 +00:00
|
|
|
setOperationAction(ISD::BSWAP, MVT::i32, Expand);
|
2008-08-13 07:13:40 +00:00
|
|
|
|
2011-01-18 19:29:17 +00:00
|
|
|
setTargetDAGCombine(ISD::ADDE);
|
|
|
|
setTargetDAGCombine(ISD::SUBE);
|
2011-03-04 21:03:24 +00:00
|
|
|
setTargetDAGCombine(ISD::SDIVREM);
|
|
|
|
setTargetDAGCombine(ISD::UDIVREM);
|
2011-03-31 18:26:17 +00:00
|
|
|
setTargetDAGCombine(ISD::SETCC);
|
2011-08-17 17:45:08 +00:00
|
|
|
setTargetDAGCombine(ISD::AND);
|
|
|
|
setTargetDAGCombine(ISD::OR);
|
2011-01-18 19:29:17 +00:00
|
|
|
|
2011-05-06 20:34:06 +00:00
|
|
|
setMinFunctionAlignment(2);
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
setStackPointerRegisterToSaveRestore(Mips::SP);
|
|
|
|
computeRegisterProperties();
|
2011-05-26 18:59:03 +00:00
|
|
|
|
|
|
|
setExceptionPointerRegister(Mips::A0);
|
|
|
|
setExceptionSelectorRegister(Mips::A1);
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
2011-08-12 21:30:06 +00:00
|
|
|
bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
|
2011-08-17 18:49:18 +00:00
|
|
|
MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
|
2011-10-11 00:27:28 +00:00
|
|
|
return SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16;
|
2011-08-12 21:30:06 +00:00
|
|
|
}
|
|
|
|
|
2011-09-06 19:07:46 +00:00
|
|
|
EVT MipsTargetLowering::getSetCCResultType(EVT VT) const {
|
2009-08-11 20:47:22 +00:00
|
|
|
return MVT::i32;
|
2008-03-10 15:42:14 +00:00
|
|
|
}
|
|
|
|
|
2011-01-18 19:29:17 +00:00
|
|
|
// SelectMadd -
|
|
|
|
// Transforms a subgraph in CurDAG if the following pattern is found:
|
|
|
|
// (addc multLo, Lo0), (adde multHi, Hi0),
|
|
|
|
// where,
|
|
|
|
// multHi/Lo: product of multiplication
|
2011-02-10 18:05:10 +00:00
|
|
|
// Lo0: initial value of Lo register
|
|
|
|
// Hi0: initial value of Hi register
|
2011-03-30 21:15:35 +00:00
|
|
|
// Return true if pattern matching was successful.
|
2011-01-18 19:29:17 +00:00
|
|
|
static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) {
|
2011-02-10 18:05:10 +00:00
|
|
|
// ADDENode's second operand must be a flag output of an ADDC node in order
|
2011-01-18 19:29:17 +00:00
|
|
|
// for the matching to be successful.
|
|
|
|
SDNode* ADDCNode = ADDENode->getOperand(2).getNode();
|
|
|
|
|
|
|
|
if (ADDCNode->getOpcode() != ISD::ADDC)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
SDValue MultHi = ADDENode->getOperand(0);
|
|
|
|
SDValue MultLo = ADDCNode->getOperand(0);
|
2011-02-10 18:05:10 +00:00
|
|
|
SDNode* MultNode = MultHi.getNode();
|
2011-01-18 19:29:17 +00:00
|
|
|
unsigned MultOpc = MultHi.getOpcode();
|
|
|
|
|
|
|
|
// MultHi and MultLo must be generated by the same node,
|
|
|
|
if (MultLo.getNode() != MultNode)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// and it must be a multiplication.
|
|
|
|
if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
|
|
|
|
return false;
|
2011-02-10 18:05:10 +00:00
|
|
|
|
|
|
|
// MultLo amd MultHi must be the first and second output of MultNode
|
|
|
|
// respectively.
|
2011-01-18 19:29:17 +00:00
|
|
|
if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
|
|
|
|
return false;
|
|
|
|
|
2011-02-10 18:05:10 +00:00
|
|
|
// Transform this to a MADD only if ADDENode and ADDCNode are the only users
|
2011-01-18 19:29:17 +00:00
|
|
|
// of the values of MultNode, in which case MultNode will be removed in later
|
|
|
|
// phases.
|
2011-04-15 21:51:11 +00:00
|
|
|
// If there exist users other than ADDENode or ADDCNode, this function returns
|
|
|
|
// here, which will result in MultNode being mapped to a single MULT
|
2011-02-10 18:05:10 +00:00
|
|
|
// instruction node rather than a pair of MULT and MADD instructions being
|
2011-01-18 19:29:17 +00:00
|
|
|
// produced.
|
|
|
|
if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
|
|
|
|
return false;
|
|
|
|
|
2011-02-10 18:05:10 +00:00
|
|
|
SDValue Chain = CurDAG->getEntryNode();
|
2011-01-18 19:29:17 +00:00
|
|
|
DebugLoc dl = ADDENode->getDebugLoc();
|
|
|
|
|
|
|
|
// create MipsMAdd(u) node
|
|
|
|
MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
|
2011-02-10 18:05:10 +00:00
|
|
|
|
2011-01-18 19:29:17 +00:00
|
|
|
SDValue MAdd = CurDAG->getNode(MultOpc, dl,
|
|
|
|
MVT::Glue,
|
|
|
|
MultNode->getOperand(0),// Factor 0
|
|
|
|
MultNode->getOperand(1),// Factor 1
|
2011-02-10 18:05:10 +00:00
|
|
|
ADDCNode->getOperand(1),// Lo0
|
2011-01-18 19:29:17 +00:00
|
|
|
ADDENode->getOperand(1));// Hi0
|
|
|
|
|
|
|
|
// create CopyFromReg nodes
|
|
|
|
SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
|
|
|
|
MAdd);
|
2011-02-10 18:05:10 +00:00
|
|
|
SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
|
2011-01-18 19:29:17 +00:00
|
|
|
Mips::HI, MVT::i32,
|
|
|
|
CopyFromLo.getValue(2));
|
|
|
|
|
|
|
|
// replace uses of adde and addc here
|
|
|
|
if (!SDValue(ADDCNode, 0).use_empty())
|
|
|
|
CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
|
|
|
|
|
|
|
|
if (!SDValue(ADDENode, 0).use_empty())
|
|
|
|
CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
|
|
|
|
|
2011-02-10 18:05:10 +00:00
|
|
|
return true;
|
2011-01-18 19:29:17 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// SelectMsub -
|
|
|
|
// Transforms a subgraph in CurDAG if the following pattern is found:
|
|
|
|
// (addc Lo0, multLo), (sube Hi0, multHi),
|
|
|
|
// where,
|
|
|
|
// multHi/Lo: product of multiplication
|
2011-02-10 18:05:10 +00:00
|
|
|
// Lo0: initial value of Lo register
|
|
|
|
// Hi0: initial value of Hi register
|
2011-03-30 21:15:35 +00:00
|
|
|
// Return true if pattern matching was successful.
|
2011-01-18 19:29:17 +00:00
|
|
|
static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) {
|
2011-02-10 18:05:10 +00:00
|
|
|
// SUBENode's second operand must be a flag output of an SUBC node in order
|
2011-01-18 19:29:17 +00:00
|
|
|
// for the matching to be successful.
|
|
|
|
SDNode* SUBCNode = SUBENode->getOperand(2).getNode();
|
|
|
|
|
|
|
|
if (SUBCNode->getOpcode() != ISD::SUBC)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
SDValue MultHi = SUBENode->getOperand(1);
|
|
|
|
SDValue MultLo = SUBCNode->getOperand(1);
|
2011-02-10 18:05:10 +00:00
|
|
|
SDNode* MultNode = MultHi.getNode();
|
2011-01-18 19:29:17 +00:00
|
|
|
unsigned MultOpc = MultHi.getOpcode();
|
|
|
|
|
|
|
|
// MultHi and MultLo must be generated by the same node,
|
|
|
|
if (MultLo.getNode() != MultNode)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// and it must be a multiplication.
|
|
|
|
if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// MultLo amd MultHi must be the first and second output of MultNode
|
|
|
|
// respectively.
|
|
|
|
if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Transform this to a MSUB only if SUBENode and SUBCNode are the only users
|
|
|
|
// of the values of MultNode, in which case MultNode will be removed in later
|
|
|
|
// phases.
|
2011-04-15 21:51:11 +00:00
|
|
|
// If there exist users other than SUBENode or SUBCNode, this function returns
|
|
|
|
// here, which will result in MultNode being mapped to a single MULT
|
2011-01-18 19:29:17 +00:00
|
|
|
// instruction node rather than a pair of MULT and MSUB instructions being
|
|
|
|
// produced.
|
|
|
|
if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
SDValue Chain = CurDAG->getEntryNode();
|
|
|
|
DebugLoc dl = SUBENode->getDebugLoc();
|
|
|
|
|
|
|
|
// create MipsSub(u) node
|
|
|
|
MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
|
|
|
|
|
|
|
|
SDValue MSub = CurDAG->getNode(MultOpc, dl,
|
|
|
|
MVT::Glue,
|
|
|
|
MultNode->getOperand(0),// Factor 0
|
|
|
|
MultNode->getOperand(1),// Factor 1
|
|
|
|
SUBCNode->getOperand(0),// Lo0
|
|
|
|
SUBENode->getOperand(0));// Hi0
|
|
|
|
|
|
|
|
// create CopyFromReg nodes
|
|
|
|
SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
|
|
|
|
MSub);
|
|
|
|
SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
|
|
|
|
Mips::HI, MVT::i32,
|
|
|
|
CopyFromLo.getValue(2));
|
|
|
|
|
|
|
|
// replace uses of sube and subc here
|
|
|
|
if (!SDValue(SUBCNode, 0).use_empty())
|
|
|
|
CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
|
|
|
|
|
|
|
|
if (!SDValue(SUBENode, 0).use_empty())
|
|
|
|
CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG,
|
|
|
|
TargetLowering::DAGCombinerInfo &DCI,
|
|
|
|
const MipsSubtarget* Subtarget) {
|
|
|
|
if (DCI.isBeforeLegalize())
|
|
|
|
return SDValue();
|
|
|
|
|
2011-11-11 04:18:21 +00:00
|
|
|
if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
|
|
|
|
SelectMadd(N, &DAG))
|
2011-01-18 19:29:17 +00:00
|
|
|
return SDValue(N, 0);
|
2011-02-10 18:05:10 +00:00
|
|
|
|
2011-01-18 19:29:17 +00:00
|
|
|
return SDValue();
|
2011-02-10 18:05:10 +00:00
|
|
|
}
|
2011-01-18 19:29:17 +00:00
|
|
|
|
|
|
|
static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG,
|
|
|
|
TargetLowering::DAGCombinerInfo &DCI,
|
|
|
|
const MipsSubtarget* Subtarget) {
|
|
|
|
if (DCI.isBeforeLegalize())
|
|
|
|
return SDValue();
|
|
|
|
|
2011-11-11 04:18:21 +00:00
|
|
|
if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
|
|
|
|
SelectMsub(N, &DAG))
|
2011-01-18 19:29:17 +00:00
|
|
|
return SDValue(N, 0);
|
2011-02-10 18:05:10 +00:00
|
|
|
|
2011-01-18 19:29:17 +00:00
|
|
|
return SDValue();
|
2011-02-10 18:05:10 +00:00
|
|
|
}
|
2011-01-18 19:29:17 +00:00
|
|
|
|
2011-03-04 21:03:24 +00:00
|
|
|
static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG,
|
|
|
|
TargetLowering::DAGCombinerInfo &DCI,
|
|
|
|
const MipsSubtarget* Subtarget) {
|
|
|
|
if (DCI.isBeforeLegalizeOps())
|
|
|
|
return SDValue();
|
|
|
|
|
2011-10-03 21:06:13 +00:00
|
|
|
EVT Ty = N->getValueType(0);
|
|
|
|
unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64;
|
|
|
|
unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64;
|
2011-03-04 21:03:24 +00:00
|
|
|
unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
|
|
|
|
MipsISD::DivRemU;
|
|
|
|
DebugLoc dl = N->getDebugLoc();
|
|
|
|
|
|
|
|
SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
|
|
|
|
N->getOperand(0), N->getOperand(1));
|
|
|
|
SDValue InChain = DAG.getEntryNode();
|
|
|
|
SDValue InGlue = DivRem;
|
|
|
|
|
|
|
|
// insert MFLO
|
|
|
|
if (N->hasAnyUseOfValue(0)) {
|
2011-10-03 21:06:13 +00:00
|
|
|
SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty,
|
2011-03-04 21:03:24 +00:00
|
|
|
InGlue);
|
|
|
|
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
|
|
|
|
InChain = CopyFromLo.getValue(1);
|
|
|
|
InGlue = CopyFromLo.getValue(2);
|
|
|
|
}
|
|
|
|
|
|
|
|
// insert MFHI
|
|
|
|
if (N->hasAnyUseOfValue(1)) {
|
|
|
|
SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
|
2011-10-03 21:06:13 +00:00
|
|
|
HI, Ty, InGlue);
|
2011-03-04 21:03:24 +00:00
|
|
|
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
|
|
|
|
}
|
|
|
|
|
|
|
|
return SDValue();
|
|
|
|
}
|
|
|
|
|
2011-03-31 18:26:17 +00:00
|
|
|
static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
|
|
|
|
switch (CC) {
|
|
|
|
default: llvm_unreachable("Unknown fp condition code!");
|
|
|
|
case ISD::SETEQ:
|
|
|
|
case ISD::SETOEQ: return Mips::FCOND_OEQ;
|
|
|
|
case ISD::SETUNE: return Mips::FCOND_UNE;
|
|
|
|
case ISD::SETLT:
|
|
|
|
case ISD::SETOLT: return Mips::FCOND_OLT;
|
|
|
|
case ISD::SETGT:
|
|
|
|
case ISD::SETOGT: return Mips::FCOND_OGT;
|
|
|
|
case ISD::SETLE:
|
|
|
|
case ISD::SETOLE: return Mips::FCOND_OLE;
|
|
|
|
case ISD::SETGE:
|
|
|
|
case ISD::SETOGE: return Mips::FCOND_OGE;
|
|
|
|
case ISD::SETULT: return Mips::FCOND_ULT;
|
|
|
|
case ISD::SETULE: return Mips::FCOND_ULE;
|
|
|
|
case ISD::SETUGT: return Mips::FCOND_UGT;
|
|
|
|
case ISD::SETUGE: return Mips::FCOND_UGE;
|
|
|
|
case ISD::SETUO: return Mips::FCOND_UN;
|
|
|
|
case ISD::SETO: return Mips::FCOND_OR;
|
|
|
|
case ISD::SETNE:
|
|
|
|
case ISD::SETONE: return Mips::FCOND_ONE;
|
|
|
|
case ISD::SETUEQ: return Mips::FCOND_UEQ;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// Returns true if condition code has to be inverted.
|
|
|
|
static bool InvertFPCondCode(Mips::CondCode CC) {
|
|
|
|
if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
assert(false && "Illegal Condition Code");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Creates and returns an FPCmp node from a setcc node.
|
|
|
|
// Returns Op if setcc is not a floating point comparison.
|
|
|
|
static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) {
|
|
|
|
// must be a SETCC node
|
|
|
|
if (Op.getOpcode() != ISD::SETCC)
|
|
|
|
return Op;
|
|
|
|
|
|
|
|
SDValue LHS = Op.getOperand(0);
|
|
|
|
|
|
|
|
if (!LHS.getValueType().isFloatingPoint())
|
|
|
|
return Op;
|
|
|
|
|
|
|
|
SDValue RHS = Op.getOperand(1);
|
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
|
2011-04-15 21:00:26 +00:00
|
|
|
// Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
|
|
|
|
// node if necessary.
|
2011-03-31 18:26:17 +00:00
|
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
|
|
|
|
|
|
|
|
return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS,
|
|
|
|
DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
|
|
|
|
}
|
|
|
|
|
|
|
|
// Creates and returns a CMovFPT/F node.
|
|
|
|
static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True,
|
|
|
|
SDValue False, DebugLoc DL) {
|
|
|
|
bool invert = InvertFPCondCode((Mips::CondCode)
|
|
|
|
cast<ConstantSDNode>(Cond.getOperand(2))
|
|
|
|
->getSExtValue());
|
|
|
|
|
|
|
|
return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
|
|
|
|
True.getValueType(), True, False, Cond);
|
|
|
|
}
|
|
|
|
|
|
|
|
static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG& DAG,
|
|
|
|
TargetLowering::DAGCombinerInfo &DCI,
|
|
|
|
const MipsSubtarget* Subtarget) {
|
|
|
|
if (DCI.isBeforeLegalizeOps())
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
SDValue Cond = CreateFPCmp(DAG, SDValue(N, 0));
|
|
|
|
|
|
|
|
if (Cond.getOpcode() != MipsISD::FPCmp)
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
SDValue True = DAG.getConstant(1, MVT::i32);
|
|
|
|
SDValue False = DAG.getConstant(0, MVT::i32);
|
|
|
|
|
|
|
|
return CreateCMovFP(DAG, Cond, True, False, N->getDebugLoc());
|
|
|
|
}
|
|
|
|
|
2011-08-17 17:45:08 +00:00
|
|
|
static SDValue PerformANDCombine(SDNode *N, SelectionDAG& DAG,
|
|
|
|
TargetLowering::DAGCombinerInfo &DCI,
|
|
|
|
const MipsSubtarget* Subtarget) {
|
|
|
|
// Pattern match EXT.
|
|
|
|
// $dst = and ((sra or srl) $src , pos), (2**size - 1)
|
|
|
|
// => ext $dst, $src, size, pos
|
2011-09-20 23:53:09 +00:00
|
|
|
if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
|
2011-08-17 17:45:08 +00:00
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
|
|
|
|
|
|
|
|
// Op's first operand must be a shift right.
|
|
|
|
if (ShiftRight.getOpcode() != ISD::SRA && ShiftRight.getOpcode() != ISD::SRL)
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
// The second operand of the shift must be an immediate.
|
|
|
|
uint64_t Pos;
|
|
|
|
ConstantSDNode *CN;
|
|
|
|
if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
Pos = CN->getZExtValue();
|
|
|
|
|
|
|
|
uint64_t SMPos, SMSize;
|
|
|
|
// Op's second operand must be a shifted mask.
|
|
|
|
if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
|
2011-08-19 22:59:00 +00:00
|
|
|
!IsShiftedMask(CN->getZExtValue(), SMPos, SMSize))
|
2011-08-17 17:45:08 +00:00
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
// Return if the shifted mask does not start at bit 0 or the sum of its size
|
|
|
|
// and Pos exceeds the word's size.
|
|
|
|
if (SMPos != 0 || Pos + SMSize > 32)
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), MVT::i32,
|
|
|
|
ShiftRight.getOperand(0),
|
2011-08-17 22:59:46 +00:00
|
|
|
DAG.getConstant(Pos, MVT::i32),
|
|
|
|
DAG.getConstant(SMSize, MVT::i32));
|
2011-08-17 17:45:08 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG,
|
|
|
|
TargetLowering::DAGCombinerInfo &DCI,
|
|
|
|
const MipsSubtarget* Subtarget) {
|
|
|
|
// Pattern match INS.
|
|
|
|
// $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
|
|
|
|
// where mask1 = (2**size - 1) << pos, mask0 = ~mask1
|
|
|
|
// => ins $dst, $src, size, pos, $src1
|
2011-09-20 23:53:09 +00:00
|
|
|
if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
|
2011-08-17 17:45:08 +00:00
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
|
|
|
|
uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
|
|
|
|
ConstantSDNode *CN;
|
|
|
|
|
|
|
|
// See if Op's first operand matches (and $src1 , mask0).
|
|
|
|
if (And0.getOpcode() != ISD::AND)
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
|
2011-08-19 22:59:00 +00:00
|
|
|
!IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
|
2011-08-17 17:45:08 +00:00
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
// See if Op's second operand matches (and (shl $src, pos), mask1).
|
|
|
|
if (And1.getOpcode() != ISD::AND)
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
|
2011-08-19 22:59:00 +00:00
|
|
|
!IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
|
2011-08-17 17:45:08 +00:00
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
// The shift masks must have the same position and size.
|
|
|
|
if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
SDValue Shl = And1.getOperand(0);
|
|
|
|
if (Shl.getOpcode() != ISD::SHL)
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
unsigned Shamt = CN->getZExtValue();
|
|
|
|
|
|
|
|
// Return if the shift amount and the first bit position of mask are not the
|
|
|
|
// same.
|
|
|
|
if (Shamt != SMPos0)
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), MVT::i32,
|
|
|
|
Shl.getOperand(0),
|
|
|
|
DAG.getConstant(SMPos0, MVT::i32),
|
2011-08-17 22:59:46 +00:00
|
|
|
DAG.getConstant(SMSize0, MVT::i32),
|
2011-08-17 17:45:08 +00:00
|
|
|
And0.getOperand(0));
|
|
|
|
}
|
|
|
|
|
2011-02-10 18:05:10 +00:00
|
|
|
SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
|
2011-01-18 19:29:17 +00:00
|
|
|
const {
|
|
|
|
SelectionDAG &DAG = DCI.DAG;
|
|
|
|
unsigned opc = N->getOpcode();
|
|
|
|
|
|
|
|
switch (opc) {
|
|
|
|
default: break;
|
|
|
|
case ISD::ADDE:
|
|
|
|
return PerformADDECombine(N, DAG, DCI, Subtarget);
|
|
|
|
case ISD::SUBE:
|
|
|
|
return PerformSUBECombine(N, DAG, DCI, Subtarget);
|
2011-03-04 21:03:24 +00:00
|
|
|
case ISD::SDIVREM:
|
|
|
|
case ISD::UDIVREM:
|
|
|
|
return PerformDivRemCombine(N, DAG, DCI, Subtarget);
|
2011-03-31 18:26:17 +00:00
|
|
|
case ISD::SETCC:
|
|
|
|
return PerformSETCCCombine(N, DAG, DCI, Subtarget);
|
2011-08-17 17:45:08 +00:00
|
|
|
case ISD::AND:
|
|
|
|
return PerformANDCombine(N, DAG, DCI, Subtarget);
|
|
|
|
case ISD::OR:
|
|
|
|
return PerformORCombine(N, DAG, DCI, Subtarget);
|
2011-01-18 19:29:17 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return SDValue();
|
|
|
|
}
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue MipsTargetLowering::
|
2010-04-17 15:26:15 +00:00
|
|
|
LowerOperation(SDValue Op, SelectionDAG &DAG) const
|
2007-06-06 07:42:06 +00:00
|
|
|
{
|
2010-11-23 03:31:01 +00:00
|
|
|
switch (Op.getOpcode())
|
2007-06-06 07:42:06 +00:00
|
|
|
{
|
2008-08-07 19:08:11 +00:00
|
|
|
case ISD::BRCOND: return LowerBRCOND(Op, DAG);
|
|
|
|
case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
|
|
|
|
case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
|
|
|
|
case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
|
2011-03-04 20:01:52 +00:00
|
|
|
case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
|
2008-08-07 19:08:11 +00:00
|
|
|
case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
|
|
|
|
case ISD::JumpTable: return LowerJumpTable(Op, DAG);
|
|
|
|
case ISD::SELECT: return LowerSELECT(Op, DAG);
|
2010-02-06 21:00:02 +00:00
|
|
|
case ISD::VASTART: return LowerVASTART(Op, DAG);
|
2011-05-25 19:32:07 +00:00
|
|
|
case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
|
2011-06-02 00:24:44 +00:00
|
|
|
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
|
2011-07-19 23:30:50 +00:00
|
|
|
case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
|
2011-07-27 22:21:52 +00:00
|
|
|
case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
2008-07-27 21:46:04 +00:00
|
|
|
return SDValue();
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 07:42:06 +00:00
|
|
|
// Lower helper functions
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
// AddLiveIn - This helper function adds the specified physical register to the
|
|
|
|
// MachineFunction as a live in value. It also creates a corresponding
|
|
|
|
// virtual register for it.
|
|
|
|
static unsigned
|
2010-11-23 03:31:01 +00:00
|
|
|
AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
|
2007-06-06 07:42:06 +00:00
|
|
|
{
|
|
|
|
assert(RC->contains(PReg) && "Not the correct regclass!");
|
2007-12-31 04:13:23 +00:00
|
|
|
unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
|
|
|
|
MF.getRegInfo().addLiveIn(PReg, VReg);
|
2007-06-06 07:42:06 +00:00
|
|
|
return VReg;
|
|
|
|
}
|
|
|
|
|
2008-07-28 19:11:24 +00:00
|
|
|
// Get fp branch code (not opcode) from condition code.
|
|
|
|
static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
|
|
|
|
if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
|
|
|
|
return Mips::BRANCH_T;
|
|
|
|
|
|
|
|
if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
|
|
|
|
return Mips::BRANCH_F;
|
|
|
|
|
|
|
|
return Mips::BRANCH_INVALID;
|
|
|
|
}
|
2010-11-23 03:31:01 +00:00
|
|
|
|
2011-10-17 18:53:29 +00:00
|
|
|
/*
|
2011-06-07 19:28:39 +00:00
|
|
|
static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,
|
|
|
|
DebugLoc dl,
|
|
|
|
const MipsSubtarget* Subtarget,
|
|
|
|
const TargetInstrInfo *TII,
|
|
|
|
bool isFPCmp, unsigned Opc) {
|
2011-05-31 02:54:07 +00:00
|
|
|
// There is no need to expand CMov instructions if target has
|
|
|
|
// conditional moves.
|
|
|
|
if (Subtarget->hasCondMov())
|
|
|
|
return BB;
|
|
|
|
|
2011-03-31 18:26:17 +00:00
|
|
|
// To "insert" a SELECT_CC instruction, we actually have to insert the
|
|
|
|
// diamond control-flow pattern. The incoming instruction knows the
|
|
|
|
// destination vreg to set, the condition code register to branch on, the
|
|
|
|
// true/false values to select between, and a branch opcode to use.
|
|
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
|
|
MachineFunction::iterator It = BB;
|
|
|
|
++It;
|
|
|
|
|
|
|
|
// thisMBB:
|
|
|
|
// ...
|
|
|
|
// TrueVal = ...
|
|
|
|
// setcc r1, r2, r3
|
|
|
|
// bNE r1, r0, copy1MBB
|
|
|
|
// fallthrough --> copy0MBB
|
|
|
|
MachineBasicBlock *thisMBB = BB;
|
|
|
|
MachineFunction *F = BB->getParent();
|
|
|
|
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
F->insert(It, copy0MBB);
|
|
|
|
F->insert(It, sinkMBB);
|
|
|
|
|
|
|
|
// Transfer the remainder of BB and its successor edges to sinkMBB.
|
|
|
|
sinkMBB->splice(sinkMBB->begin(), BB,
|
|
|
|
llvm::next(MachineBasicBlock::iterator(MI)),
|
|
|
|
BB->end());
|
|
|
|
sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
|
|
|
|
|
|
|
|
// Next, add the true and fallthrough blocks as its successors.
|
|
|
|
BB->addSuccessor(copy0MBB);
|
|
|
|
BB->addSuccessor(sinkMBB);
|
|
|
|
|
|
|
|
// Emit the right instruction according to the type of the operands compared
|
|
|
|
if (isFPCmp)
|
|
|
|
BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
|
|
|
|
else
|
|
|
|
BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
|
|
|
|
.addReg(Mips::ZERO).addMBB(sinkMBB);
|
|
|
|
|
|
|
|
// copy0MBB:
|
|
|
|
// %FalseValue = ...
|
|
|
|
// # fallthrough to sinkMBB
|
|
|
|
BB = copy0MBB;
|
|
|
|
|
|
|
|
// Update machine-CFG edges
|
|
|
|
BB->addSuccessor(sinkMBB);
|
|
|
|
|
|
|
|
// sinkMBB:
|
|
|
|
// %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
|
|
|
|
// ...
|
|
|
|
BB = sinkMBB;
|
|
|
|
|
|
|
|
if (isFPCmp)
|
2010-07-06 20:24:04 +00:00
|
|
|
BuildMI(*BB, BB->begin(), dl,
|
|
|
|
TII->get(Mips::PHI), MI->getOperand(0).getReg())
|
2010-07-20 07:58:51 +00:00
|
|
|
.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
|
2011-03-31 18:26:17 +00:00
|
|
|
.addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
|
|
|
|
else
|
|
|
|
BuildMI(*BB, BB->begin(), dl,
|
|
|
|
TII->get(Mips::PHI), MI->getOperand(0).getReg())
|
|
|
|
.addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
|
|
|
|
.addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
|
2008-07-29 19:05:28 +00:00
|
|
|
|
2011-03-31 18:26:17 +00:00
|
|
|
MI->eraseFromParent(); // The pseudo instruction is gone now.
|
|
|
|
return BB;
|
2008-07-29 19:05:28 +00:00
|
|
|
}
|
2011-10-17 18:53:29 +00:00
|
|
|
*/
|
2011-06-07 19:28:39 +00:00
|
|
|
MachineBasicBlock *
|
|
|
|
MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
|
|
|
MachineBasicBlock *BB) const {
|
|
|
|
switch (MI->getOpcode()) {
|
|
|
|
default:
|
|
|
|
assert(false && "Unexpected instr type to insert");
|
|
|
|
return NULL;
|
|
|
|
case Mips::ATOMIC_LOAD_ADD_I8:
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_ADD_I8_P8:
|
2011-06-07 19:28:39 +00:00
|
|
|
return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
|
|
|
|
case Mips::ATOMIC_LOAD_ADD_I16:
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_ADD_I16_P8:
|
2011-06-07 19:28:39 +00:00
|
|
|
return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
|
|
|
|
case Mips::ATOMIC_LOAD_ADD_I32:
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_ADD_I32_P8:
|
2011-06-07 19:28:39 +00:00
|
|
|
return EmitAtomicBinary(MI, BB, 4, Mips::ADDu);
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_ADD_I64:
|
|
|
|
case Mips::ATOMIC_LOAD_ADD_I64_P8:
|
|
|
|
return EmitAtomicBinary(MI, BB, 8, Mips::DADDu);
|
2011-06-07 19:28:39 +00:00
|
|
|
|
|
|
|
case Mips::ATOMIC_LOAD_AND_I8:
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_AND_I8_P8:
|
2011-06-07 19:28:39 +00:00
|
|
|
return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
|
|
|
|
case Mips::ATOMIC_LOAD_AND_I16:
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_AND_I16_P8:
|
2011-06-07 19:28:39 +00:00
|
|
|
return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
|
|
|
|
case Mips::ATOMIC_LOAD_AND_I32:
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_AND_I32_P8:
|
2011-06-07 19:28:39 +00:00
|
|
|
return EmitAtomicBinary(MI, BB, 4, Mips::AND);
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_AND_I64:
|
|
|
|
case Mips::ATOMIC_LOAD_AND_I64_P8:
|
|
|
|
return EmitAtomicBinary(MI, BB, 48, Mips::AND64);
|
2011-06-07 19:28:39 +00:00
|
|
|
|
|
|
|
case Mips::ATOMIC_LOAD_OR_I8:
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_OR_I8_P8:
|
2011-06-07 19:28:39 +00:00
|
|
|
return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
|
|
|
|
case Mips::ATOMIC_LOAD_OR_I16:
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_OR_I16_P8:
|
2011-06-07 19:28:39 +00:00
|
|
|
return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
|
|
|
|
case Mips::ATOMIC_LOAD_OR_I32:
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_OR_I32_P8:
|
2011-06-07 19:28:39 +00:00
|
|
|
return EmitAtomicBinary(MI, BB, 4, Mips::OR);
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_OR_I64:
|
|
|
|
case Mips::ATOMIC_LOAD_OR_I64_P8:
|
|
|
|
return EmitAtomicBinary(MI, BB, 8, Mips::OR64);
|
2011-06-07 19:28:39 +00:00
|
|
|
|
|
|
|
case Mips::ATOMIC_LOAD_XOR_I8:
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_XOR_I8_P8:
|
2011-06-07 19:28:39 +00:00
|
|
|
return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
|
|
|
|
case Mips::ATOMIC_LOAD_XOR_I16:
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_XOR_I16_P8:
|
2011-06-07 19:28:39 +00:00
|
|
|
return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
|
|
|
|
case Mips::ATOMIC_LOAD_XOR_I32:
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_XOR_I32_P8:
|
2011-06-07 19:28:39 +00:00
|
|
|
return EmitAtomicBinary(MI, BB, 4, Mips::XOR);
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_XOR_I64:
|
|
|
|
case Mips::ATOMIC_LOAD_XOR_I64_P8:
|
|
|
|
return EmitAtomicBinary(MI, BB, 8, Mips::XOR64);
|
2011-06-07 19:28:39 +00:00
|
|
|
|
|
|
|
case Mips::ATOMIC_LOAD_NAND_I8:
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_NAND_I8_P8:
|
2011-06-07 19:28:39 +00:00
|
|
|
return EmitAtomicBinaryPartword(MI, BB, 1, 0, true);
|
|
|
|
case Mips::ATOMIC_LOAD_NAND_I16:
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_NAND_I16_P8:
|
2011-06-07 19:28:39 +00:00
|
|
|
return EmitAtomicBinaryPartword(MI, BB, 2, 0, true);
|
|
|
|
case Mips::ATOMIC_LOAD_NAND_I32:
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_NAND_I32_P8:
|
2011-06-07 19:28:39 +00:00
|
|
|
return EmitAtomicBinary(MI, BB, 4, 0, true);
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_NAND_I64:
|
|
|
|
case Mips::ATOMIC_LOAD_NAND_I64_P8:
|
|
|
|
return EmitAtomicBinary(MI, BB, 8, 0, true);
|
2011-06-07 19:28:39 +00:00
|
|
|
|
|
|
|
case Mips::ATOMIC_LOAD_SUB_I8:
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_SUB_I8_P8:
|
2011-06-07 19:28:39 +00:00
|
|
|
return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
|
|
|
|
case Mips::ATOMIC_LOAD_SUB_I16:
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_SUB_I16_P8:
|
2011-06-07 19:28:39 +00:00
|
|
|
return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
|
|
|
|
case Mips::ATOMIC_LOAD_SUB_I32:
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_SUB_I32_P8:
|
2011-06-07 19:28:39 +00:00
|
|
|
return EmitAtomicBinary(MI, BB, 4, Mips::SUBu);
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_LOAD_SUB_I64:
|
|
|
|
case Mips::ATOMIC_LOAD_SUB_I64_P8:
|
|
|
|
return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu);
|
2011-06-07 19:28:39 +00:00
|
|
|
|
|
|
|
case Mips::ATOMIC_SWAP_I8:
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_SWAP_I8_P8:
|
2011-06-07 19:28:39 +00:00
|
|
|
return EmitAtomicBinaryPartword(MI, BB, 1, 0);
|
|
|
|
case Mips::ATOMIC_SWAP_I16:
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_SWAP_I16_P8:
|
2011-06-07 19:28:39 +00:00
|
|
|
return EmitAtomicBinaryPartword(MI, BB, 2, 0);
|
|
|
|
case Mips::ATOMIC_SWAP_I32:
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_SWAP_I32_P8:
|
2011-06-07 19:28:39 +00:00
|
|
|
return EmitAtomicBinary(MI, BB, 4, 0);
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_SWAP_I64:
|
|
|
|
case Mips::ATOMIC_SWAP_I64_P8:
|
|
|
|
return EmitAtomicBinary(MI, BB, 8, 0);
|
2011-06-07 19:28:39 +00:00
|
|
|
|
|
|
|
case Mips::ATOMIC_CMP_SWAP_I8:
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_CMP_SWAP_I8_P8:
|
2011-06-07 19:28:39 +00:00
|
|
|
return EmitAtomicCmpSwapPartword(MI, BB, 1);
|
|
|
|
case Mips::ATOMIC_CMP_SWAP_I16:
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_CMP_SWAP_I16_P8:
|
2011-06-07 19:28:39 +00:00
|
|
|
return EmitAtomicCmpSwapPartword(MI, BB, 2);
|
|
|
|
case Mips::ATOMIC_CMP_SWAP_I32:
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_CMP_SWAP_I32_P8:
|
2011-06-07 19:28:39 +00:00
|
|
|
return EmitAtomicCmpSwap(MI, BB, 4);
|
2011-11-11 04:14:30 +00:00
|
|
|
case Mips::ATOMIC_CMP_SWAP_I64:
|
|
|
|
case Mips::ATOMIC_CMP_SWAP_I64_P8:
|
|
|
|
return EmitAtomicCmpSwap(MI, BB, 8);
|
2011-06-07 19:28:39 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-05-31 02:54:07 +00:00
|
|
|
// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
|
|
|
|
// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
|
|
|
|
MachineBasicBlock *
|
|
|
|
MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
|
2011-06-08 23:55:35 +00:00
|
|
|
unsigned Size, unsigned BinOpcode,
|
2011-06-07 18:58:42 +00:00
|
|
|
bool Nand) const {
|
2011-11-11 04:14:30 +00:00
|
|
|
assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
MachineFunction *MF = BB->getParent();
|
|
|
|
MachineRegisterInfo &RegInfo = MF->getRegInfo();
|
2011-11-11 04:14:30 +00:00
|
|
|
const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
|
2011-05-31 02:54:07 +00:00
|
|
|
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
|
|
|
DebugLoc dl = MI->getDebugLoc();
|
2011-11-11 04:14:30 +00:00
|
|
|
unsigned LL, SC, AND, NOR, ZERO, BEQ;
|
|
|
|
|
|
|
|
if (Size == 4) {
|
|
|
|
LL = IsN64 ? Mips::LL_P8 : Mips::LL;
|
|
|
|
SC = IsN64 ? Mips::SC_P8 : Mips::SC;
|
|
|
|
AND = Mips::AND;
|
|
|
|
NOR = Mips::NOR;
|
|
|
|
ZERO = Mips::ZERO;
|
|
|
|
BEQ = Mips::BEQ;
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
|
|
|
|
SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
|
|
|
|
AND = Mips::AND64;
|
|
|
|
NOR = Mips::NOR64;
|
|
|
|
ZERO = Mips::ZERO_64;
|
|
|
|
BEQ = Mips::BEQ64;
|
|
|
|
}
|
2011-05-31 02:54:07 +00:00
|
|
|
|
2011-07-19 20:11:17 +00:00
|
|
|
unsigned OldVal = MI->getOperand(0).getReg();
|
2011-05-31 02:54:07 +00:00
|
|
|
unsigned Ptr = MI->getOperand(1).getReg();
|
|
|
|
unsigned Incr = MI->getOperand(2).getReg();
|
|
|
|
|
2011-07-19 20:11:17 +00:00
|
|
|
unsigned StoreVal = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned AndRes = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned Success = RegInfo.createVirtualRegister(RC);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
// insert new blocks after the current block
|
|
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
|
|
MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
MachineFunction::iterator It = BB;
|
|
|
|
++It;
|
|
|
|
MF->insert(It, loopMBB);
|
|
|
|
MF->insert(It, exitMBB);
|
|
|
|
|
|
|
|
// Transfer the remainder of BB and its successor edges to exitMBB.
|
|
|
|
exitMBB->splice(exitMBB->begin(), BB,
|
|
|
|
llvm::next(MachineBasicBlock::iterator(MI)),
|
|
|
|
BB->end());
|
|
|
|
exitMBB->transferSuccessorsAndUpdatePHIs(BB);
|
|
|
|
|
|
|
|
// thisMBB:
|
|
|
|
// ...
|
|
|
|
// fallthrough --> loopMBB
|
|
|
|
BB->addSuccessor(loopMBB);
|
2011-07-19 17:09:53 +00:00
|
|
|
loopMBB->addSuccessor(loopMBB);
|
|
|
|
loopMBB->addSuccessor(exitMBB);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
// loopMBB:
|
|
|
|
// ll oldval, 0(ptr)
|
2011-07-19 20:11:17 +00:00
|
|
|
// <binop> storeval, oldval, incr
|
|
|
|
// sc success, storeval, 0(ptr)
|
|
|
|
// beq success, $0, loopMBB
|
2011-05-31 02:54:07 +00:00
|
|
|
BB = loopMBB;
|
2011-11-11 04:14:30 +00:00
|
|
|
BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
|
2011-05-31 02:54:07 +00:00
|
|
|
if (Nand) {
|
2011-07-19 20:11:17 +00:00
|
|
|
// and andres, oldval, incr
|
|
|
|
// nor storeval, $0, andres
|
2011-11-11 04:14:30 +00:00
|
|
|
BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
|
|
|
|
BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
|
2011-05-31 02:54:07 +00:00
|
|
|
} else if (BinOpcode) {
|
2011-07-19 20:11:17 +00:00
|
|
|
// <binop> storeval, oldval, incr
|
|
|
|
BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
|
2011-05-31 02:54:07 +00:00
|
|
|
} else {
|
2011-07-19 20:11:17 +00:00
|
|
|
StoreVal = Incr;
|
2011-05-31 02:54:07 +00:00
|
|
|
}
|
2011-11-11 04:14:30 +00:00
|
|
|
BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
|
|
|
|
BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
MI->eraseFromParent(); // The instruction is gone now.
|
|
|
|
|
2011-07-19 03:42:13 +00:00
|
|
|
return exitMBB;
|
2011-05-31 02:54:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
MachineBasicBlock *
|
|
|
|
MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
|
2011-06-07 18:58:42 +00:00
|
|
|
MachineBasicBlock *BB,
|
|
|
|
unsigned Size, unsigned BinOpcode,
|
|
|
|
bool Nand) const {
|
2011-05-31 02:54:07 +00:00
|
|
|
assert((Size == 1 || Size == 2) &&
|
|
|
|
"Unsupported size for EmitAtomicBinaryPartial.");
|
|
|
|
|
|
|
|
MachineFunction *MF = BB->getParent();
|
|
|
|
MachineRegisterInfo &RegInfo = MF->getRegInfo();
|
|
|
|
const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
|
|
|
|
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
|
|
|
DebugLoc dl = MI->getDebugLoc();
|
2011-11-11 04:14:30 +00:00
|
|
|
unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
|
|
|
|
unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
unsigned Dest = MI->getOperand(0).getReg();
|
|
|
|
unsigned Ptr = MI->getOperand(1).getReg();
|
|
|
|
unsigned Incr = MI->getOperand(2).getReg();
|
|
|
|
|
2011-07-19 20:11:17 +00:00
|
|
|
unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
|
2011-05-31 02:54:07 +00:00
|
|
|
unsigned Mask = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned Mask2 = RegInfo.createVirtualRegister(RC);
|
2011-07-19 20:11:17 +00:00
|
|
|
unsigned NewVal = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned OldVal = RegInfo.createVirtualRegister(RC);
|
2011-05-31 02:54:07 +00:00
|
|
|
unsigned Incr2 = RegInfo.createVirtualRegister(RC);
|
2011-07-19 20:11:17 +00:00
|
|
|
unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned AndRes = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
|
2011-07-19 20:56:53 +00:00
|
|
|
unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
|
2011-07-19 20:11:17 +00:00
|
|
|
unsigned StoreVal = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned SrlRes = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned SllRes = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned Success = RegInfo.createVirtualRegister(RC);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
// insert new blocks after the current block
|
|
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
|
|
MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
2011-07-19 03:42:13 +00:00
|
|
|
MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
2011-05-31 02:54:07 +00:00
|
|
|
MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
MachineFunction::iterator It = BB;
|
|
|
|
++It;
|
|
|
|
MF->insert(It, loopMBB);
|
2011-07-19 03:42:13 +00:00
|
|
|
MF->insert(It, sinkMBB);
|
2011-05-31 02:54:07 +00:00
|
|
|
MF->insert(It, exitMBB);
|
|
|
|
|
|
|
|
// Transfer the remainder of BB and its successor edges to exitMBB.
|
|
|
|
exitMBB->splice(exitMBB->begin(), BB,
|
|
|
|
llvm::next(MachineBasicBlock::iterator(MI)),
|
|
|
|
BB->end());
|
|
|
|
exitMBB->transferSuccessorsAndUpdatePHIs(BB);
|
|
|
|
|
2011-07-19 17:09:53 +00:00
|
|
|
BB->addSuccessor(loopMBB);
|
|
|
|
loopMBB->addSuccessor(loopMBB);
|
|
|
|
loopMBB->addSuccessor(sinkMBB);
|
|
|
|
sinkMBB->addSuccessor(exitMBB);
|
|
|
|
|
2011-05-31 02:54:07 +00:00
|
|
|
// thisMBB:
|
2011-07-19 20:11:17 +00:00
|
|
|
// addiu masklsb2,$0,-4 # 0xfffffffc
|
|
|
|
// and alignedaddr,ptr,masklsb2
|
|
|
|
// andi ptrlsb2,ptr,3
|
|
|
|
// sll shiftamt,ptrlsb2,3
|
|
|
|
// ori maskupper,$0,255 # 0xff
|
|
|
|
// sll mask,maskupper,shiftamt
|
2011-05-31 02:54:07 +00:00
|
|
|
// nor mask2,$0,mask
|
2011-07-19 20:11:17 +00:00
|
|
|
// sll incr2,incr,shiftamt
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
int64_t MaskImm = (Size == 1) ? 255 : 65535;
|
2011-07-19 20:11:17 +00:00
|
|
|
BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
|
|
|
|
.addReg(Mips::ZERO).addImm(-4);
|
|
|
|
BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
|
|
|
|
.addReg(Ptr).addReg(MaskLSB2);
|
|
|
|
BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
|
|
|
|
BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
|
|
|
|
BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
|
|
|
|
.addReg(Mips::ZERO).addImm(MaskImm);
|
2011-07-19 20:34:00 +00:00
|
|
|
BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
|
|
|
|
.addReg(ShiftAmt).addReg(MaskUpper);
|
2011-05-31 02:54:07 +00:00
|
|
|
BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
|
2011-07-19 20:34:00 +00:00
|
|
|
BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr);
|
2011-05-31 20:25:26 +00:00
|
|
|
|
2011-05-31 02:54:07 +00:00
|
|
|
|
2011-07-18 18:52:12 +00:00
|
|
|
// atomic.load.binop
|
2011-05-31 02:54:07 +00:00
|
|
|
// loopMBB:
|
2011-07-19 20:11:17 +00:00
|
|
|
// ll oldval,0(alignedaddr)
|
|
|
|
// binop binopres,oldval,incr2
|
|
|
|
// and newval,binopres,mask
|
|
|
|
// and maskedoldval0,oldval,mask2
|
|
|
|
// or storeval,maskedoldval0,newval
|
|
|
|
// sc success,storeval,0(alignedaddr)
|
|
|
|
// beq success,$0,loopMBB
|
|
|
|
|
2011-07-18 18:52:12 +00:00
|
|
|
// atomic.swap
|
|
|
|
// loopMBB:
|
2011-07-19 20:11:17 +00:00
|
|
|
// ll oldval,0(alignedaddr)
|
2011-07-19 18:14:26 +00:00
|
|
|
// and newval,incr2,mask
|
2011-07-19 20:11:17 +00:00
|
|
|
// and maskedoldval0,oldval,mask2
|
|
|
|
// or storeval,maskedoldval0,newval
|
|
|
|
// sc success,storeval,0(alignedaddr)
|
|
|
|
// beq success,$0,loopMBB
|
2011-07-18 18:52:12 +00:00
|
|
|
|
2011-05-31 02:54:07 +00:00
|
|
|
BB = loopMBB;
|
2011-11-11 04:14:30 +00:00
|
|
|
BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
|
2011-05-31 02:54:07 +00:00
|
|
|
if (Nand) {
|
2011-07-19 20:11:17 +00:00
|
|
|
// and andres, oldval, incr2
|
|
|
|
// nor binopres, $0, andres
|
|
|
|
// and newval, binopres, mask
|
|
|
|
BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
|
|
|
|
BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes)
|
|
|
|
.addReg(Mips::ZERO).addReg(AndRes);
|
|
|
|
BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
|
2011-05-31 02:54:07 +00:00
|
|
|
} else if (BinOpcode) {
|
2011-07-19 20:11:17 +00:00
|
|
|
// <binop> binopres, oldval, incr2
|
|
|
|
// and newval, binopres, mask
|
|
|
|
BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
|
|
|
|
BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
|
2011-07-19 18:14:26 +00:00
|
|
|
} else {// atomic.swap
|
2011-07-19 20:11:17 +00:00
|
|
|
// and newval, incr2, mask
|
2011-07-19 20:34:00 +00:00
|
|
|
BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
|
2011-07-19 18:14:26 +00:00
|
|
|
}
|
|
|
|
|
2011-07-19 20:56:53 +00:00
|
|
|
BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(OldVal).addReg(Mask2);
|
|
|
|
BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
|
2011-07-19 20:56:53 +00:00
|
|
|
.addReg(MaskedOldVal0).addReg(NewVal);
|
2011-11-11 04:14:30 +00:00
|
|
|
BuildMI(BB, dl, TII->get(SC), Success)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(StoreVal).addReg(AlignedAddr).addImm(0);
|
2011-05-31 02:54:07 +00:00
|
|
|
BuildMI(BB, dl, TII->get(Mips::BEQ))
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
2011-07-19 03:42:13 +00:00
|
|
|
// sinkMBB:
|
2011-07-19 20:11:17 +00:00
|
|
|
// and maskedoldval1,oldval,mask
|
|
|
|
// srl srlres,maskedoldval1,shiftamt
|
|
|
|
// sll sllres,srlres,24
|
|
|
|
// sra dest,sllres,24
|
2011-07-19 03:42:13 +00:00
|
|
|
BB = sinkMBB;
|
2011-05-31 02:54:07 +00:00
|
|
|
int64_t ShiftImm = (Size == 1) ? 24 : 16;
|
2011-07-19 03:14:58 +00:00
|
|
|
|
2011-07-19 20:11:17 +00:00
|
|
|
BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
|
|
|
|
.addReg(OldVal).addReg(Mask);
|
2011-07-19 20:34:00 +00:00
|
|
|
BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
|
|
|
|
.addReg(ShiftAmt).addReg(MaskedOldVal1);
|
2011-07-19 20:11:17 +00:00
|
|
|
BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
|
|
|
|
.addReg(SrlRes).addImm(ShiftImm);
|
2011-07-19 03:42:13 +00:00
|
|
|
BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(SllRes).addImm(ShiftImm);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
MI->eraseFromParent(); // The instruction is gone now.
|
|
|
|
|
2011-07-19 03:42:13 +00:00
|
|
|
return exitMBB;
|
2011-05-31 02:54:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
MachineBasicBlock *
|
|
|
|
MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
|
2011-06-07 18:58:42 +00:00
|
|
|
MachineBasicBlock *BB,
|
|
|
|
unsigned Size) const {
|
2011-11-11 04:14:30 +00:00
|
|
|
assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
MachineFunction *MF = BB->getParent();
|
|
|
|
MachineRegisterInfo &RegInfo = MF->getRegInfo();
|
2011-11-11 04:14:30 +00:00
|
|
|
const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
|
2011-05-31 02:54:07 +00:00
|
|
|
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
|
|
|
DebugLoc dl = MI->getDebugLoc();
|
2011-11-11 04:14:30 +00:00
|
|
|
unsigned LL, SC, ZERO, BNE, BEQ;
|
|
|
|
|
|
|
|
if (Size == 4) {
|
|
|
|
LL = IsN64 ? Mips::LL_P8 : Mips::LL;
|
|
|
|
SC = IsN64 ? Mips::SC_P8 : Mips::SC;
|
|
|
|
ZERO = Mips::ZERO;
|
|
|
|
BNE = Mips::BNE;
|
|
|
|
BEQ = Mips::BEQ;
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
|
|
|
|
SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
|
|
|
|
ZERO = Mips::ZERO_64;
|
|
|
|
BNE = Mips::BNE64;
|
|
|
|
BEQ = Mips::BEQ64;
|
|
|
|
}
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
unsigned Dest = MI->getOperand(0).getReg();
|
|
|
|
unsigned Ptr = MI->getOperand(1).getReg();
|
2011-07-19 20:11:17 +00:00
|
|
|
unsigned OldVal = MI->getOperand(2).getReg();
|
|
|
|
unsigned NewVal = MI->getOperand(3).getReg();
|
2011-05-31 02:54:07 +00:00
|
|
|
|
2011-07-19 20:11:17 +00:00
|
|
|
unsigned Success = RegInfo.createVirtualRegister(RC);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
// insert new blocks after the current block
|
|
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
|
|
MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
MachineFunction::iterator It = BB;
|
|
|
|
++It;
|
|
|
|
MF->insert(It, loop1MBB);
|
|
|
|
MF->insert(It, loop2MBB);
|
|
|
|
MF->insert(It, exitMBB);
|
|
|
|
|
|
|
|
// Transfer the remainder of BB and its successor edges to exitMBB.
|
|
|
|
exitMBB->splice(exitMBB->begin(), BB,
|
|
|
|
llvm::next(MachineBasicBlock::iterator(MI)),
|
|
|
|
BB->end());
|
|
|
|
exitMBB->transferSuccessorsAndUpdatePHIs(BB);
|
|
|
|
|
|
|
|
// thisMBB:
|
|
|
|
// ...
|
|
|
|
// fallthrough --> loop1MBB
|
|
|
|
BB->addSuccessor(loop1MBB);
|
2011-07-19 17:09:53 +00:00
|
|
|
loop1MBB->addSuccessor(exitMBB);
|
|
|
|
loop1MBB->addSuccessor(loop2MBB);
|
|
|
|
loop2MBB->addSuccessor(loop1MBB);
|
|
|
|
loop2MBB->addSuccessor(exitMBB);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
// loop1MBB:
|
|
|
|
// ll dest, 0(ptr)
|
|
|
|
// bne dest, oldval, exitMBB
|
|
|
|
BB = loop1MBB;
|
2011-11-11 04:14:30 +00:00
|
|
|
BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0);
|
|
|
|
BuildMI(BB, dl, TII->get(BNE))
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(Dest).addReg(OldVal).addMBB(exitMBB);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
// loop2MBB:
|
2011-07-19 20:11:17 +00:00
|
|
|
// sc success, newval, 0(ptr)
|
|
|
|
// beq success, $0, loop1MBB
|
2011-05-31 02:54:07 +00:00
|
|
|
BB = loop2MBB;
|
2011-11-11 04:14:30 +00:00
|
|
|
BuildMI(BB, dl, TII->get(SC), Success)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(NewVal).addReg(Ptr).addImm(0);
|
2011-11-11 04:14:30 +00:00
|
|
|
BuildMI(BB, dl, TII->get(BEQ))
|
|
|
|
.addReg(Success).addReg(ZERO).addMBB(loop1MBB);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
MI->eraseFromParent(); // The instruction is gone now.
|
|
|
|
|
2011-07-19 03:42:13 +00:00
|
|
|
return exitMBB;
|
2011-05-31 02:54:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
MachineBasicBlock *
|
|
|
|
MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
|
2011-06-07 18:58:42 +00:00
|
|
|
MachineBasicBlock *BB,
|
|
|
|
unsigned Size) const {
|
2011-05-31 02:54:07 +00:00
|
|
|
assert((Size == 1 || Size == 2) &&
|
|
|
|
"Unsupported size for EmitAtomicCmpSwapPartial.");
|
|
|
|
|
|
|
|
MachineFunction *MF = BB->getParent();
|
|
|
|
MachineRegisterInfo &RegInfo = MF->getRegInfo();
|
|
|
|
const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
|
|
|
|
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
|
|
|
DebugLoc dl = MI->getDebugLoc();
|
2011-11-11 04:14:30 +00:00
|
|
|
unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
|
|
|
|
unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
unsigned Dest = MI->getOperand(0).getReg();
|
|
|
|
unsigned Ptr = MI->getOperand(1).getReg();
|
2011-07-19 20:11:17 +00:00
|
|
|
unsigned CmpVal = MI->getOperand(2).getReg();
|
|
|
|
unsigned NewVal = MI->getOperand(3).getReg();
|
2011-05-31 02:54:07 +00:00
|
|
|
|
2011-07-19 20:11:17 +00:00
|
|
|
unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
|
2011-05-31 02:54:07 +00:00
|
|
|
unsigned Mask = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned Mask2 = RegInfo.createVirtualRegister(RC);
|
2011-07-19 20:11:17 +00:00
|
|
|
unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned OldVal = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned StoreVal = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned SrlRes = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned SllRes = RegInfo.createVirtualRegister(RC);
|
|
|
|
unsigned Success = RegInfo.createVirtualRegister(RC);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
// insert new blocks after the current block
|
|
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
|
|
MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
2011-07-19 03:42:13 +00:00
|
|
|
MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
2011-05-31 02:54:07 +00:00
|
|
|
MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
MachineFunction::iterator It = BB;
|
|
|
|
++It;
|
|
|
|
MF->insert(It, loop1MBB);
|
|
|
|
MF->insert(It, loop2MBB);
|
2011-07-19 03:42:13 +00:00
|
|
|
MF->insert(It, sinkMBB);
|
2011-05-31 02:54:07 +00:00
|
|
|
MF->insert(It, exitMBB);
|
|
|
|
|
|
|
|
// Transfer the remainder of BB and its successor edges to exitMBB.
|
|
|
|
exitMBB->splice(exitMBB->begin(), BB,
|
|
|
|
llvm::next(MachineBasicBlock::iterator(MI)),
|
|
|
|
BB->end());
|
|
|
|
exitMBB->transferSuccessorsAndUpdatePHIs(BB);
|
|
|
|
|
2011-07-19 17:09:53 +00:00
|
|
|
BB->addSuccessor(loop1MBB);
|
|
|
|
loop1MBB->addSuccessor(sinkMBB);
|
|
|
|
loop1MBB->addSuccessor(loop2MBB);
|
|
|
|
loop2MBB->addSuccessor(loop1MBB);
|
|
|
|
loop2MBB->addSuccessor(sinkMBB);
|
|
|
|
sinkMBB->addSuccessor(exitMBB);
|
|
|
|
|
2011-07-19 18:14:26 +00:00
|
|
|
// FIXME: computation of newval2 can be moved to loop2MBB.
|
2011-05-31 02:54:07 +00:00
|
|
|
// thisMBB:
|
2011-07-19 20:11:17 +00:00
|
|
|
// addiu masklsb2,$0,-4 # 0xfffffffc
|
|
|
|
// and alignedaddr,ptr,masklsb2
|
|
|
|
// andi ptrlsb2,ptr,3
|
|
|
|
// sll shiftamt,ptrlsb2,3
|
|
|
|
// ori maskupper,$0,255 # 0xff
|
|
|
|
// sll mask,maskupper,shiftamt
|
2011-05-31 02:54:07 +00:00
|
|
|
// nor mask2,$0,mask
|
2011-07-19 20:11:17 +00:00
|
|
|
// andi maskedcmpval,cmpval,255
|
|
|
|
// sll shiftedcmpval,maskedcmpval,shiftamt
|
|
|
|
// andi maskednewval,newval,255
|
|
|
|
// sll shiftednewval,maskednewval,shiftamt
|
2011-05-31 02:54:07 +00:00
|
|
|
int64_t MaskImm = (Size == 1) ? 255 : 65535;
|
2011-07-19 20:11:17 +00:00
|
|
|
BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
|
|
|
|
.addReg(Mips::ZERO).addImm(-4);
|
|
|
|
BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
|
|
|
|
.addReg(Ptr).addReg(MaskLSB2);
|
|
|
|
BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
|
|
|
|
BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
|
|
|
|
BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
|
|
|
|
.addReg(Mips::ZERO).addImm(MaskImm);
|
2011-07-19 20:34:00 +00:00
|
|
|
BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
|
|
|
|
.addReg(ShiftAmt).addReg(MaskUpper);
|
2011-05-31 02:54:07 +00:00
|
|
|
BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
|
2011-07-19 20:11:17 +00:00
|
|
|
BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal)
|
|
|
|
.addReg(CmpVal).addImm(MaskImm);
|
2011-07-19 20:34:00 +00:00
|
|
|
BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal)
|
|
|
|
.addReg(ShiftAmt).addReg(MaskedCmpVal);
|
2011-07-19 20:11:17 +00:00
|
|
|
BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal)
|
|
|
|
.addReg(NewVal).addImm(MaskImm);
|
2011-07-19 20:34:00 +00:00
|
|
|
BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal)
|
|
|
|
.addReg(ShiftAmt).addReg(MaskedNewVal);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
// loop1MBB:
|
2011-07-19 20:11:17 +00:00
|
|
|
// ll oldval,0(alginedaddr)
|
|
|
|
// and maskedoldval0,oldval,mask
|
|
|
|
// bne maskedoldval0,shiftedcmpval,sinkMBB
|
2011-05-31 02:54:07 +00:00
|
|
|
BB = loop1MBB;
|
2011-11-11 04:14:30 +00:00
|
|
|
BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
|
2011-07-19 20:11:17 +00:00
|
|
|
BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
|
|
|
|
.addReg(OldVal).addReg(Mask);
|
2011-05-31 02:54:07 +00:00
|
|
|
BuildMI(BB, dl, TII->get(Mips::BNE))
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
// loop2MBB:
|
2011-07-19 20:11:17 +00:00
|
|
|
// and maskedoldval1,oldval,mask2
|
|
|
|
// or storeval,maskedoldval1,shiftednewval
|
|
|
|
// sc success,storeval,0(alignedaddr)
|
|
|
|
// beq success,$0,loop1MBB
|
2011-05-31 02:54:07 +00:00
|
|
|
BB = loop2MBB;
|
2011-07-19 20:11:17 +00:00
|
|
|
BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
|
|
|
|
.addReg(OldVal).addReg(Mask2);
|
|
|
|
BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
|
|
|
|
.addReg(MaskedOldVal1).addReg(ShiftedNewVal);
|
2011-11-11 04:14:30 +00:00
|
|
|
BuildMI(BB, dl, TII->get(SC), Success)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(StoreVal).addReg(AlignedAddr).addImm(0);
|
2011-05-31 02:54:07 +00:00
|
|
|
BuildMI(BB, dl, TII->get(Mips::BEQ))
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
2011-07-19 03:42:13 +00:00
|
|
|
// sinkMBB:
|
2011-07-19 20:11:17 +00:00
|
|
|
// srl srlres,maskedoldval0,shiftamt
|
|
|
|
// sll sllres,srlres,24
|
|
|
|
// sra dest,sllres,24
|
2011-07-19 03:42:13 +00:00
|
|
|
BB = sinkMBB;
|
2011-05-31 02:54:07 +00:00
|
|
|
int64_t ShiftImm = (Size == 1) ? 24 : 16;
|
2011-07-19 03:14:58 +00:00
|
|
|
|
2011-07-19 20:34:00 +00:00
|
|
|
BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
|
|
|
|
.addReg(ShiftAmt).addReg(MaskedOldVal0);
|
2011-07-19 20:11:17 +00:00
|
|
|
BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
|
|
|
|
.addReg(SrlRes).addImm(ShiftImm);
|
2011-07-19 03:42:13 +00:00
|
|
|
BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
|
2011-07-19 20:11:17 +00:00
|
|
|
.addReg(SllRes).addImm(ShiftImm);
|
2011-05-31 02:54:07 +00:00
|
|
|
|
|
|
|
MI->eraseFromParent(); // The instruction is gone now.
|
|
|
|
|
2011-07-19 03:42:13 +00:00
|
|
|
return exitMBB;
|
2011-05-31 02:54:07 +00:00
|
|
|
}
|
|
|
|
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 07:42:06 +00:00
|
|
|
// Misc Lower Operation implementation
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2008-08-07 19:08:11 +00:00
|
|
|
SDValue MipsTargetLowering::
|
2010-04-17 15:26:15 +00:00
|
|
|
LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
|
2008-08-07 19:08:11 +00:00
|
|
|
{
|
2011-06-21 00:40:49 +00:00
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
2011-11-11 04:06:38 +00:00
|
|
|
unsigned SP = IsN64 ? Mips::SP_64 : Mips::SP;
|
2011-06-21 00:40:49 +00:00
|
|
|
|
|
|
|
assert(getTargetMachine().getFrameLowering()->getStackAlignment() >=
|
2011-05-25 02:20:00 +00:00
|
|
|
cast<ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue() &&
|
|
|
|
"Cannot lower if the alignment of the allocated space is larger than \
|
|
|
|
that of the stack.");
|
|
|
|
|
2008-08-07 19:08:11 +00:00
|
|
|
SDValue Chain = Op.getOperand(0);
|
|
|
|
SDValue Size = Op.getOperand(1);
|
2009-02-04 23:02:30 +00:00
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
2008-08-07 19:08:11 +00:00
|
|
|
|
|
|
|
// Get a reference from Mips stack pointer
|
2011-11-11 04:06:38 +00:00
|
|
|
SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, SP, getPointerTy());
|
2008-08-07 19:08:11 +00:00
|
|
|
|
|
|
|
// Subtract the dynamic size from the actual stack size to
|
|
|
|
// obtain the new stack size.
|
2011-11-11 04:06:38 +00:00
|
|
|
SDValue Sub = DAG.getNode(ISD::SUB, dl, getPointerTy(), StackPointer, Size);
|
2008-08-07 19:08:11 +00:00
|
|
|
|
2010-11-23 03:31:01 +00:00
|
|
|
// The Sub result contains the new stack start address, so it
|
2008-08-07 19:08:11 +00:00
|
|
|
// must be placed in the stack pointer register.
|
2011-11-11 04:06:38 +00:00
|
|
|
Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, SP, Sub, SDValue());
|
2010-11-23 03:31:01 +00:00
|
|
|
|
|
|
|
// This node always has two return values: a new stack pointer
|
2008-08-07 19:08:11 +00:00
|
|
|
// value and a chain
|
2011-11-11 04:06:38 +00:00
|
|
|
SDVTList VTLs = DAG.getVTList(getPointerTy(), MVT::Other);
|
2011-06-21 00:40:49 +00:00
|
|
|
SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy());
|
|
|
|
SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) };
|
|
|
|
|
|
|
|
return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3);
|
2008-08-07 19:08:11 +00:00
|
|
|
}
|
|
|
|
|
2008-07-28 19:11:24 +00:00
|
|
|
SDValue MipsTargetLowering::
|
2010-04-17 15:26:15 +00:00
|
|
|
LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
|
2008-07-28 19:11:24 +00:00
|
|
|
{
|
2010-11-23 03:31:01 +00:00
|
|
|
// The first operand is the chain, the second is the condition, the third is
|
2008-07-28 19:11:24 +00:00
|
|
|
// the block to branch to if the condition is true.
|
|
|
|
SDValue Chain = Op.getOperand(0);
|
|
|
|
SDValue Dest = Op.getOperand(2);
|
2009-02-06 21:50:26 +00:00
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
2008-07-31 18:31:28 +00:00
|
|
|
|
2011-03-31 18:26:17 +00:00
|
|
|
SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1));
|
|
|
|
|
2011-04-15 05:18:47 +00:00
|
|
|
// Return if flag is not set by a floating point comparison.
|
2011-03-31 18:26:17 +00:00
|
|
|
if (CondRes.getOpcode() != MipsISD::FPCmp)
|
2008-07-30 17:06:13 +00:00
|
|
|
return Op;
|
2010-11-23 03:31:01 +00:00
|
|
|
|
2008-07-31 18:31:28 +00:00
|
|
|
SDValue CCNode = CondRes.getOperand(2);
|
2008-09-12 16:56:44 +00:00
|
|
|
Mips::CondCode CC =
|
|
|
|
(Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
|
2010-11-23 03:31:01 +00:00
|
|
|
SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
|
2008-07-28 19:11:24 +00:00
|
|
|
|
2010-11-23 03:31:01 +00:00
|
|
|
return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
|
2011-03-31 18:26:17 +00:00
|
|
|
Dest, CondRes);
|
2008-07-28 19:11:24 +00:00
|
|
|
}
|
|
|
|
|
2008-07-29 19:05:28 +00:00
|
|
|
SDValue MipsTargetLowering::
|
2010-04-17 15:26:15 +00:00
|
|
|
LowerSELECT(SDValue Op, SelectionDAG &DAG) const
|
2008-07-29 19:05:28 +00:00
|
|
|
{
|
2011-03-31 18:26:17 +00:00
|
|
|
SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0));
|
2008-07-29 19:05:28 +00:00
|
|
|
|
2011-04-15 05:18:47 +00:00
|
|
|
// Return if flag is not set by a floating point comparison.
|
2011-03-31 18:26:17 +00:00
|
|
|
if (Cond.getOpcode() != MipsISD::FPCmp)
|
|
|
|
return Op;
|
2008-08-13 07:13:40 +00:00
|
|
|
|
2011-03-31 18:26:17 +00:00
|
|
|
return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
|
|
|
|
Op.getDebugLoc());
|
2008-07-29 19:05:28 +00:00
|
|
|
}
|
|
|
|
|
2010-04-17 15:26:15 +00:00
|
|
|
SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
|
|
|
|
SelectionDAG &DAG) const {
|
2009-02-06 21:50:26 +00:00
|
|
|
// FIXME there isn't actually debug info here
|
2009-02-04 20:06:27 +00:00
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
2011-10-11 00:55:05 +00:00
|
|
|
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
|
2008-07-29 19:29:50 +00:00
|
|
|
|
2011-10-11 00:55:05 +00:00
|
|
|
if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
|
2009-08-13 05:41:27 +00:00
|
|
|
SDVTList VTs = DAG.getVTList(MVT::i32);
|
2010-11-23 03:31:01 +00:00
|
|
|
|
2009-08-13 06:28:06 +00:00
|
|
|
MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering();
|
2010-11-23 03:31:01 +00:00
|
|
|
|
2009-08-13 05:41:27 +00:00
|
|
|
// %gp_rel relocation
|
2010-11-23 03:31:01 +00:00
|
|
|
if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
|
|
|
|
SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
|
2009-09-01 17:27:58 +00:00
|
|
|
MipsII::MO_GPREL);
|
2009-08-13 05:41:27 +00:00
|
|
|
SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
|
|
|
|
SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
|
2010-11-23 03:31:01 +00:00
|
|
|
return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
|
2009-08-13 05:41:27 +00:00
|
|
|
}
|
2008-07-29 19:29:50 +00:00
|
|
|
// %hi/%lo relocation
|
2011-04-01 21:41:06 +00:00
|
|
|
SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
|
|
|
|
MipsII::MO_ABS_HI);
|
|
|
|
SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
|
|
|
|
MipsII::MO_ABS_LO);
|
|
|
|
SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1);
|
|
|
|
SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
|
2009-08-11 20:47:22 +00:00
|
|
|
return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
|
2008-07-29 19:29:50 +00:00
|
|
|
}
|
|
|
|
|
2011-10-11 00:55:05 +00:00
|
|
|
EVT ValTy = Op.getValueType();
|
|
|
|
bool HasGotOfst = (GV->hasInternalLinkage() ||
|
|
|
|
(GV->hasLocalLinkage() && !isa<Function>(GV)));
|
|
|
|
unsigned GotFlag = IsN64 ?
|
|
|
|
(HasGotOfst ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT_DISP) :
|
|
|
|
MipsII::MO_GOT;
|
|
|
|
SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag);
|
|
|
|
GA = DAG.getNode(MipsISD::WrapperPIC, dl, ValTy, GA);
|
|
|
|
SDValue ResNode = DAG.getLoad(ValTy, dl,
|
2011-06-07 18:58:42 +00:00
|
|
|
DAG.getEntryNode(), GA, MachinePointerInfo(),
|
2011-11-08 18:42:53 +00:00
|
|
|
false, false, false, 0);
|
2011-06-07 18:58:42 +00:00
|
|
|
// On functions and global targets not internal linked only
|
|
|
|
// a load from got/GP is necessary for PIC to work.
|
2011-10-11 00:55:05 +00:00
|
|
|
if (!HasGotOfst)
|
2011-06-07 18:58:42 +00:00
|
|
|
return ResNode;
|
2011-10-11 00:55:05 +00:00
|
|
|
SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0,
|
|
|
|
IsN64 ? MipsII::MO_GOT_OFST :
|
|
|
|
MipsII::MO_ABS_LO);
|
|
|
|
SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, GALo);
|
|
|
|
return DAG.getNode(ISD::ADD, dl, ValTy, ResNode, Lo);
|
2008-07-29 19:29:50 +00:00
|
|
|
}
|
|
|
|
|
2011-03-04 20:01:52 +00:00
|
|
|
SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
|
|
|
|
SelectionDAG &DAG) const {
|
2011-04-25 17:10:45 +00:00
|
|
|
const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
|
|
|
|
// FIXME there isn't actually debug info here
|
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
|
2011-03-04 20:01:52 +00:00
|
|
|
if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
|
2011-04-25 17:10:45 +00:00
|
|
|
// %hi/%lo relocation
|
|
|
|
SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true,
|
|
|
|
MipsII::MO_ABS_HI);
|
|
|
|
SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true,
|
|
|
|
MipsII::MO_ABS_LO);
|
|
|
|
SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi);
|
|
|
|
SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo);
|
|
|
|
return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
|
2011-03-04 20:01:52 +00:00
|
|
|
}
|
2011-04-25 17:10:45 +00:00
|
|
|
|
|
|
|
SDValue BAGOTOffset = DAG.getBlockAddress(BA, MVT::i32, true,
|
|
|
|
MipsII::MO_GOT);
|
2011-05-28 01:07:07 +00:00
|
|
|
BAGOTOffset = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, BAGOTOffset);
|
2011-04-25 17:10:45 +00:00
|
|
|
SDValue BALOOffset = DAG.getBlockAddress(BA, MVT::i32, true,
|
|
|
|
MipsII::MO_ABS_LO);
|
|
|
|
SDValue Load = DAG.getLoad(MVT::i32, dl,
|
|
|
|
DAG.getEntryNode(), BAGOTOffset,
|
2011-11-08 18:42:53 +00:00
|
|
|
MachinePointerInfo(), false, false, false, 0);
|
2011-04-25 17:10:45 +00:00
|
|
|
SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALOOffset);
|
|
|
|
return DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
|
2011-03-04 20:01:52 +00:00
|
|
|
}
|
|
|
|
|
2008-07-29 19:29:50 +00:00
|
|
|
SDValue MipsTargetLowering::
|
2010-04-17 15:26:15 +00:00
|
|
|
LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
|
2008-07-29 19:29:50 +00:00
|
|
|
{
|
2011-05-31 02:53:58 +00:00
|
|
|
// If the relocation model is PIC, use the General Dynamic TLS Model,
|
|
|
|
// otherwise use the Initial Exec or Local Exec TLS Model.
|
|
|
|
// TODO: implement Local Dynamic TLS model
|
|
|
|
|
|
|
|
GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
|
|
|
|
DebugLoc dl = GA->getDebugLoc();
|
|
|
|
const GlobalValue *GV = GA->getGlobal();
|
|
|
|
EVT PtrVT = getPointerTy();
|
|
|
|
|
|
|
|
if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
|
|
|
|
// General Dynamic TLS Model
|
|
|
|
SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32,
|
2011-06-21 01:02:03 +00:00
|
|
|
0, MipsII::MO_TLSGD);
|
2011-05-31 02:53:58 +00:00
|
|
|
SDValue Tlsgd = DAG.getNode(MipsISD::TlsGd, dl, MVT::i32, TGA);
|
|
|
|
SDValue GP = DAG.getRegister(Mips::GP, MVT::i32);
|
|
|
|
SDValue Argument = DAG.getNode(ISD::ADD, dl, MVT::i32, GP, Tlsgd);
|
|
|
|
|
|
|
|
ArgListTy Args;
|
|
|
|
ArgListEntry Entry;
|
|
|
|
Entry.Node = Argument;
|
2011-07-18 04:54:35 +00:00
|
|
|
Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
|
2011-05-31 02:53:58 +00:00
|
|
|
Args.push_back(Entry);
|
|
|
|
std::pair<SDValue, SDValue> CallResult =
|
|
|
|
LowerCallTo(DAG.getEntryNode(),
|
2011-07-18 04:54:35 +00:00
|
|
|
(Type *) Type::getInt32Ty(*DAG.getContext()),
|
2011-06-21 01:02:03 +00:00
|
|
|
false, false, false, false, 0, CallingConv::C, false, true,
|
|
|
|
DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG,
|
|
|
|
dl);
|
2011-05-31 02:53:58 +00:00
|
|
|
|
|
|
|
return CallResult.first;
|
2011-06-21 01:02:03 +00:00
|
|
|
}
|
2011-05-31 02:53:58 +00:00
|
|
|
|
2011-06-21 01:02:03 +00:00
|
|
|
SDValue Offset;
|
|
|
|
if (GV->isDeclaration()) {
|
|
|
|
// Initial Exec TLS Model
|
|
|
|
SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
|
|
|
|
MipsII::MO_GOTTPREL);
|
|
|
|
Offset = DAG.getLoad(MVT::i32, dl,
|
|
|
|
DAG.getEntryNode(), TGA, MachinePointerInfo(),
|
2011-11-08 18:42:53 +00:00
|
|
|
false, false, false, 0);
|
2011-06-21 01:02:03 +00:00
|
|
|
} else {
|
|
|
|
// Local Exec TLS Model
|
|
|
|
SDVTList VTs = DAG.getVTList(MVT::i32);
|
|
|
|
SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
|
|
|
|
MipsII::MO_TPREL_HI);
|
|
|
|
SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
|
|
|
|
MipsII::MO_TPREL_LO);
|
|
|
|
SDValue Hi = DAG.getNode(MipsISD::TprelHi, dl, VTs, &TGAHi, 1);
|
|
|
|
SDValue Lo = DAG.getNode(MipsISD::TprelLo, dl, MVT::i32, TGALo);
|
|
|
|
Offset = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
|
2011-05-31 02:53:58 +00:00
|
|
|
}
|
2011-06-21 01:02:03 +00:00
|
|
|
|
|
|
|
SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT);
|
|
|
|
return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
|
2008-07-29 19:29:50 +00:00
|
|
|
}
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue MipsTargetLowering::
|
2010-04-17 15:26:15 +00:00
|
|
|
LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
|
2007-11-12 19:49:57 +00:00
|
|
|
{
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue ResNode;
|
2010-11-23 03:31:01 +00:00
|
|
|
SDValue HiPart;
|
2009-02-06 21:50:26 +00:00
|
|
|
// FIXME there isn't actually debug info here
|
2009-02-04 20:06:27 +00:00
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
2009-09-01 17:27:58 +00:00
|
|
|
bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
|
2011-04-01 21:41:06 +00:00
|
|
|
unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HI;
|
2007-11-12 19:49:57 +00:00
|
|
|
|
2009-08-10 22:56:29 +00:00
|
|
|
EVT PtrVT = Op.getValueType();
|
2007-11-12 19:49:57 +00:00
|
|
|
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
|
|
|
|
|
2009-09-01 17:27:58 +00:00
|
|
|
SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
|
|
|
|
|
2010-07-20 08:37:04 +00:00
|
|
|
if (!IsPIC) {
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Ops[] = { JTI };
|
2009-09-01 17:27:58 +00:00
|
|
|
HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1);
|
2011-05-28 01:07:07 +00:00
|
|
|
} else {// Emit Load from Global Pointer
|
|
|
|
JTI = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, JTI);
|
2010-09-21 06:44:06 +00:00
|
|
|
HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI,
|
|
|
|
MachinePointerInfo(),
|
2011-11-08 18:42:53 +00:00
|
|
|
false, false, false, 0);
|
2011-05-28 01:07:07 +00:00
|
|
|
}
|
2007-11-12 19:49:57 +00:00
|
|
|
|
2011-04-15 21:00:26 +00:00
|
|
|
SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
|
|
|
|
MipsII::MO_ABS_LO);
|
2011-04-01 21:41:06 +00:00
|
|
|
SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTILo);
|
2009-08-11 20:47:22 +00:00
|
|
|
ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
|
2007-11-12 19:49:57 +00:00
|
|
|
|
|
|
|
return ResNode;
|
|
|
|
}
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue MipsTargetLowering::
|
2010-04-17 15:26:15 +00:00
|
|
|
LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
|
2008-07-09 04:15:08 +00:00
|
|
|
{
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue ResNode;
|
2008-07-23 16:01:50 +00:00
|
|
|
ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
|
2010-04-15 01:51:59 +00:00
|
|
|
const Constant *C = N->getConstVal();
|
2009-02-06 21:50:26 +00:00
|
|
|
// FIXME there isn't actually debug info here
|
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
2008-07-23 16:01:50 +00:00
|
|
|
|
|
|
|
// gp_rel relocation
|
2010-11-23 03:31:01 +00:00
|
|
|
// FIXME: we should reference the constant pool using small data sections,
|
2011-04-15 05:18:47 +00:00
|
|
|
// but the asm printer currently doesn't support this feature without
|
2010-11-23 03:31:01 +00:00
|
|
|
// hacking it. This feature should come soon so we can uncomment the
|
2008-07-28 19:26:25 +00:00
|
|
|
// stuff below.
|
2009-08-03 02:22:28 +00:00
|
|
|
//if (IsInSmallSection(C->getType())) {
|
2009-08-11 20:47:22 +00:00
|
|
|
// SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
|
|
|
|
// SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
|
2010-11-23 03:31:01 +00:00
|
|
|
// ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
|
2009-11-25 12:17:58 +00:00
|
|
|
|
|
|
|
if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
|
2011-04-01 21:41:06 +00:00
|
|
|
SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
|
2011-04-15 21:51:11 +00:00
|
|
|
N->getOffset(), MipsII::MO_ABS_HI);
|
2011-04-01 21:41:06 +00:00
|
|
|
SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
|
2011-04-15 21:51:11 +00:00
|
|
|
N->getOffset(), MipsII::MO_ABS_LO);
|
2011-04-01 21:41:06 +00:00
|
|
|
SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi);
|
|
|
|
SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
|
2009-08-11 20:47:22 +00:00
|
|
|
ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
|
2009-11-25 12:17:58 +00:00
|
|
|
} else {
|
2010-11-23 03:31:01 +00:00
|
|
|
SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
|
2011-04-01 21:41:06 +00:00
|
|
|
N->getOffset(), MipsII::MO_GOT);
|
2011-05-28 01:07:07 +00:00
|
|
|
CP = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, CP);
|
2010-11-23 03:31:01 +00:00
|
|
|
SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(),
|
2010-09-21 06:44:06 +00:00
|
|
|
CP, MachinePointerInfo::getConstantPool(),
|
2011-11-08 18:42:53 +00:00
|
|
|
false, false, false, 0);
|
2011-04-01 21:41:06 +00:00
|
|
|
SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
|
2011-04-15 21:51:11 +00:00
|
|
|
N->getOffset(), MipsII::MO_ABS_LO);
|
2011-04-01 21:41:06 +00:00
|
|
|
SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
|
2009-11-25 12:17:58 +00:00
|
|
|
ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
|
|
|
|
}
|
2008-07-23 16:01:50 +00:00
|
|
|
|
|
|
|
return ResNode;
|
2008-07-09 04:15:08 +00:00
|
|
|
}
|
|
|
|
|
2010-04-17 15:26:15 +00:00
|
|
|
SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
|
2010-04-17 14:41:14 +00:00
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
|
|
|
|
|
2010-02-06 21:00:02 +00:00
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
2010-04-17 14:41:14 +00:00
|
|
|
SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
|
|
|
|
getPointerTy());
|
2010-02-06 21:00:02 +00:00
|
|
|
|
|
|
|
// vastart just stores the address of the VarArgsFrameIndex slot into the
|
|
|
|
// memory location argument.
|
|
|
|
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
|
2010-09-21 17:50:43 +00:00
|
|
|
return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
|
|
|
|
MachinePointerInfo(SV),
|
2010-02-15 16:56:10 +00:00
|
|
|
false, false, 0);
|
2010-02-06 21:00:02 +00:00
|
|
|
}
|
|
|
|
|
2011-05-25 19:32:07 +00:00
|
|
|
static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG) {
|
|
|
|
// FIXME: Use ext/ins instructions if target architecture is Mips32r2.
|
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(0));
|
|
|
|
SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(1));
|
|
|
|
SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op0,
|
|
|
|
DAG.getConstant(0x7fffffff, MVT::i32));
|
|
|
|
SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op1,
|
|
|
|
DAG.getConstant(0x80000000, MVT::i32));
|
|
|
|
SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1);
|
|
|
|
return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Result);
|
|
|
|
}
|
|
|
|
|
|
|
|
static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool isLittle) {
|
2011-06-08 23:55:35 +00:00
|
|
|
// FIXME:
|
2011-05-25 19:32:07 +00:00
|
|
|
// Use ext/ins instructions if target architecture is Mips32r2.
|
|
|
|
// Eliminate redundant mfc1 and mtc1 instructions.
|
|
|
|
unsigned LoIdx = 0, HiIdx = 1;
|
2011-06-08 23:55:35 +00:00
|
|
|
|
2011-05-25 19:32:07 +00:00
|
|
|
if (!isLittle)
|
|
|
|
std::swap(LoIdx, HiIdx);
|
|
|
|
|
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
SDValue Word0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
|
|
|
|
Op.getOperand(0),
|
|
|
|
DAG.getConstant(LoIdx, MVT::i32));
|
|
|
|
SDValue Hi0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
|
|
|
|
Op.getOperand(0), DAG.getConstant(HiIdx, MVT::i32));
|
|
|
|
SDValue Hi1 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
|
|
|
|
Op.getOperand(1), DAG.getConstant(HiIdx, MVT::i32));
|
|
|
|
SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi0,
|
|
|
|
DAG.getConstant(0x7fffffff, MVT::i32));
|
|
|
|
SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi1,
|
|
|
|
DAG.getConstant(0x80000000, MVT::i32));
|
|
|
|
SDValue Word1 = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1);
|
|
|
|
|
|
|
|
if (!isLittle)
|
|
|
|
std::swap(Word0, Word1);
|
|
|
|
|
|
|
|
return DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, Word0, Word1);
|
|
|
|
}
|
|
|
|
|
|
|
|
SDValue MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG)
|
|
|
|
const {
|
|
|
|
EVT Ty = Op.getValueType();
|
|
|
|
|
|
|
|
assert(Ty == MVT::f32 || Ty == MVT::f64);
|
|
|
|
|
|
|
|
if (Ty == MVT::f32)
|
|
|
|
return LowerFCOPYSIGN32(Op, DAG);
|
|
|
|
else
|
|
|
|
return LowerFCOPYSIGN64(Op, DAG, Subtarget->isLittle());
|
|
|
|
}
|
|
|
|
|
2011-06-02 00:24:44 +00:00
|
|
|
SDValue MipsTargetLowering::
|
|
|
|
LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
|
2011-06-16 00:40:02 +00:00
|
|
|
// check the depth
|
|
|
|
assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
|
2011-06-07 18:58:42 +00:00
|
|
|
"Frame address can only be determined for current frame.");
|
2011-06-02 00:24:44 +00:00
|
|
|
|
|
|
|
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
|
|
|
|
MFI->setFrameAddressIsTaken(true);
|
|
|
|
EVT VT = Op.getValueType();
|
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
2011-11-11 04:11:56 +00:00
|
|
|
SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
|
|
|
|
IsN64 ? Mips::FP_64 : Mips::FP, VT);
|
2011-06-02 00:24:44 +00:00
|
|
|
return FrameAddr;
|
|
|
|
}
|
|
|
|
|
2011-07-19 23:30:50 +00:00
|
|
|
// TODO: set SType according to the desired memory barrier behavior.
|
|
|
|
SDValue MipsTargetLowering::LowerMEMBARRIER(SDValue Op,
|
|
|
|
SelectionDAG& DAG) const {
|
|
|
|
unsigned SType = 0;
|
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
|
|
|
|
DAG.getConstant(SType, MVT::i32));
|
|
|
|
}
|
|
|
|
|
2011-07-27 22:21:52 +00:00
|
|
|
SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op,
|
|
|
|
SelectionDAG& DAG) const {
|
|
|
|
// FIXME: Need pseudo-fence for 'singlethread' fences
|
|
|
|
// FIXME: Set SType for weaker fences where supported/appropriate.
|
|
|
|
unsigned SType = 0;
|
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
|
|
|
|
DAG.getConstant(SType, MVT::i32));
|
|
|
|
}
|
|
|
|
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 07:42:06 +00:00
|
|
|
// Calling Convention Implementation
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
#include "MipsGenCallingConv.inc"
|
|
|
|
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2010-11-23 03:31:01 +00:00
|
|
|
// TODO: Implement a generic logic using tblgen that can support this.
|
2009-03-19 02:12:28 +00:00
|
|
|
// Mips O32 ABI rules:
|
|
|
|
// ---
|
|
|
|
// i32 - Passed in A0, A1, A2, A3 and stack
|
2010-11-23 03:31:01 +00:00
|
|
|
// f32 - Only passed in f32 registers if no int reg has been used yet to hold
|
2009-03-19 02:12:28 +00:00
|
|
|
// an argument. Otherwise, passed in A1, A2, A3 and stack.
|
2010-11-23 03:31:01 +00:00
|
|
|
// f64 - Only passed in two aliased f32 registers if no int reg has been used
|
|
|
|
// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
|
2009-03-19 02:12:28 +00:00
|
|
|
// not used, it must be shadowed. If only A3 is avaiable, shadow it and
|
|
|
|
// go to stack.
|
2011-05-19 18:06:05 +00:00
|
|
|
//
|
|
|
|
// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2009-03-19 02:12:28 +00:00
|
|
|
|
2010-11-04 10:49:57 +00:00
|
|
|
static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
|
2010-11-03 11:35:31 +00:00
|
|
|
MVT LocVT, CCValAssign::LocInfo LocInfo,
|
2009-03-19 02:12:28 +00:00
|
|
|
ISD::ArgFlagsTy ArgFlags, CCState &State) {
|
|
|
|
|
2010-11-23 03:31:01 +00:00
|
|
|
static const unsigned IntRegsSize=4, FloatRegsSize=2;
|
2009-03-19 02:12:28 +00:00
|
|
|
|
|
|
|
static const unsigned IntRegs[] = {
|
|
|
|
Mips::A0, Mips::A1, Mips::A2, Mips::A3
|
|
|
|
};
|
|
|
|
static const unsigned F32Regs[] = {
|
|
|
|
Mips::F12, Mips::F14
|
|
|
|
};
|
|
|
|
static const unsigned F64Regs[] = {
|
|
|
|
Mips::D6, Mips::D7
|
|
|
|
};
|
|
|
|
|
2011-05-24 19:18:33 +00:00
|
|
|
// ByVal Args
|
|
|
|
if (ArgFlags.isByVal()) {
|
|
|
|
State.HandleByVal(ValNo, ValVT, LocVT, LocInfo,
|
|
|
|
1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags);
|
|
|
|
unsigned NextReg = (State.getNextStackOffset() + 3) / 4;
|
|
|
|
for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize);
|
|
|
|
r < std::min(IntRegsSize, NextReg); ++r)
|
|
|
|
State.AllocateReg(IntRegs[r]);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2010-02-06 19:20:49 +00:00
|
|
|
// Promote i8 and i16
|
|
|
|
if (LocVT == MVT::i8 || LocVT == MVT::i16) {
|
|
|
|
LocVT = MVT::i32;
|
|
|
|
if (ArgFlags.isSExt())
|
|
|
|
LocInfo = CCValAssign::SExt;
|
|
|
|
else if (ArgFlags.isZExt())
|
|
|
|
LocInfo = CCValAssign::ZExt;
|
|
|
|
else
|
|
|
|
LocInfo = CCValAssign::AExt;
|
|
|
|
}
|
|
|
|
|
2011-03-04 20:27:44 +00:00
|
|
|
unsigned Reg;
|
2010-02-06 19:20:49 +00:00
|
|
|
|
2011-05-19 18:06:05 +00:00
|
|
|
// f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
|
|
|
|
// is true: function is vararg, argument is 3rd or higher, there is previous
|
|
|
|
// argument which is not f32 or f64.
|
|
|
|
bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
|
|
|
|
|| State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
|
2011-05-19 20:29:48 +00:00
|
|
|
unsigned OrigAlign = ArgFlags.getOrigAlign();
|
|
|
|
bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
|
2011-05-19 18:06:05 +00:00
|
|
|
|
|
|
|
if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
|
2011-03-04 20:27:44 +00:00
|
|
|
Reg = State.AllocateReg(IntRegs, IntRegsSize);
|
2011-05-19 20:29:48 +00:00
|
|
|
// If this is the first part of an i64 arg,
|
|
|
|
// the allocated register must be either A0 or A2.
|
|
|
|
if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
|
|
|
|
Reg = State.AllocateReg(IntRegs, IntRegsSize);
|
2011-03-04 20:27:44 +00:00
|
|
|
LocVT = MVT::i32;
|
2011-05-19 18:06:05 +00:00
|
|
|
} else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
|
|
|
|
// Allocate int register and shadow next int register. If first
|
|
|
|
// available register is Mips::A1 or Mips::A3, shadow it too.
|
2011-03-04 20:27:44 +00:00
|
|
|
Reg = State.AllocateReg(IntRegs, IntRegsSize);
|
|
|
|
if (Reg == Mips::A1 || Reg == Mips::A3)
|
|
|
|
Reg = State.AllocateReg(IntRegs, IntRegsSize);
|
|
|
|
State.AllocateReg(IntRegs, IntRegsSize);
|
|
|
|
LocVT = MVT::i32;
|
2011-05-19 18:06:05 +00:00
|
|
|
} else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
|
|
|
|
// we are guaranteed to find an available float register
|
|
|
|
if (ValVT == MVT::f32) {
|
|
|
|
Reg = State.AllocateReg(F32Regs, FloatRegsSize);
|
|
|
|
// Shadow int register
|
|
|
|
State.AllocateReg(IntRegs, IntRegsSize);
|
|
|
|
} else {
|
|
|
|
Reg = State.AllocateReg(F64Regs, FloatRegsSize);
|
|
|
|
// Shadow int registers
|
|
|
|
unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
|
|
|
|
if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
|
|
|
|
State.AllocateReg(IntRegs, IntRegsSize);
|
|
|
|
State.AllocateReg(IntRegs, IntRegsSize);
|
|
|
|
}
|
2011-03-04 20:27:44 +00:00
|
|
|
} else
|
|
|
|
llvm_unreachable("Cannot handle this ValVT.");
|
2010-02-06 19:20:49 +00:00
|
|
|
|
2011-05-20 21:39:54 +00:00
|
|
|
unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
|
|
|
|
unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign);
|
|
|
|
|
|
|
|
if (!Reg)
|
2011-03-04 20:27:44 +00:00
|
|
|
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
|
2011-05-20 21:39:54 +00:00
|
|
|
else
|
2011-03-04 20:27:44 +00:00
|
|
|
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
|
2010-02-06 19:20:49 +00:00
|
|
|
|
2011-03-04 20:27:44 +00:00
|
|
|
return false; // CC must always match
|
2010-02-06 19:20:49 +00:00
|
|
|
}
|
|
|
|
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
// Call Calling Convention Implementation
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2011-05-24 19:18:33 +00:00
|
|
|
static const unsigned O32IntRegsSize = 4;
|
|
|
|
|
|
|
|
static const unsigned O32IntRegs[] = {
|
|
|
|
Mips::A0, Mips::A1, Mips::A2, Mips::A3
|
|
|
|
};
|
|
|
|
|
2011-09-23 00:58:33 +00:00
|
|
|
// Return next O32 integer argument register.
|
|
|
|
static unsigned getNextIntArgReg(unsigned Reg) {
|
|
|
|
assert((Reg == Mips::A0) || (Reg == Mips::A2));
|
|
|
|
return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
|
|
|
|
}
|
|
|
|
|
2011-05-24 19:18:33 +00:00
|
|
|
// Write ByVal Arg to arg registers and stack.
|
|
|
|
static void
|
2011-09-19 20:26:02 +00:00
|
|
|
WriteByValArg(SDValue& ByValChain, SDValue Chain, DebugLoc dl,
|
2011-05-24 19:18:33 +00:00
|
|
|
SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass,
|
|
|
|
SmallVector<SDValue, 8>& MemOpChains, int& LastFI,
|
|
|
|
MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
|
2011-05-25 17:32:06 +00:00
|
|
|
const CCValAssign &VA, const ISD::ArgFlagsTy& Flags,
|
2011-08-18 23:39:37 +00:00
|
|
|
MVT PtrType, bool isLittle) {
|
|
|
|
unsigned LocMemOffset = VA.getLocMemOffset();
|
|
|
|
unsigned Offset = 0;
|
|
|
|
uint32_t RemainingSize = Flags.getByValSize();
|
2011-08-12 21:30:06 +00:00
|
|
|
unsigned ByValAlign = Flags.getByValAlign();
|
2011-05-24 19:18:33 +00:00
|
|
|
|
2011-08-18 23:39:37 +00:00
|
|
|
// Copy the first 4 words of byval arg to registers A0 - A3.
|
|
|
|
// FIXME: Use a stricter alignment if it enables better optimization in passes
|
|
|
|
// run later.
|
|
|
|
for (; RemainingSize >= 4 && LocMemOffset < 4 * 4;
|
|
|
|
Offset += 4, RemainingSize -= 4, LocMemOffset += 4) {
|
2011-05-24 19:18:33 +00:00
|
|
|
SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
|
2011-08-18 23:39:37 +00:00
|
|
|
DAG.getConstant(Offset, MVT::i32));
|
2011-05-24 19:18:33 +00:00
|
|
|
SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr,
|
|
|
|
MachinePointerInfo(),
|
2011-11-08 18:42:53 +00:00
|
|
|
false, false, false, std::min(ByValAlign,
|
|
|
|
(unsigned )4));
|
2011-05-24 19:18:33 +00:00
|
|
|
MemOpChains.push_back(LoadVal.getValue(1));
|
2011-08-18 23:39:37 +00:00
|
|
|
unsigned DstReg = O32IntRegs[LocMemOffset / 4];
|
2011-05-24 19:18:33 +00:00
|
|
|
RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
|
|
|
|
}
|
|
|
|
|
2011-08-18 23:39:37 +00:00
|
|
|
if (RemainingSize == 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
// If there still is a register available for argument passing, write the
|
|
|
|
// remaining part of the structure to it using subword loads and shifts.
|
|
|
|
if (LocMemOffset < 4 * 4) {
|
|
|
|
assert(RemainingSize <= 3 && RemainingSize >= 1 &&
|
|
|
|
"There must be one to three bytes remaining.");
|
|
|
|
unsigned LoadSize = (RemainingSize == 3 ? 2 : RemainingSize);
|
|
|
|
SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
|
|
|
|
DAG.getConstant(Offset, MVT::i32));
|
|
|
|
unsigned Alignment = std::min(ByValAlign, (unsigned )4);
|
|
|
|
SDValue LoadVal = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
|
|
|
|
LoadPtr, MachinePointerInfo(),
|
|
|
|
MVT::getIntegerVT(LoadSize * 8), false,
|
|
|
|
false, Alignment);
|
|
|
|
MemOpChains.push_back(LoadVal.getValue(1));
|
|
|
|
|
|
|
|
// If target is big endian, shift it to the most significant half-word or
|
|
|
|
// byte.
|
|
|
|
if (!isLittle)
|
|
|
|
LoadVal = DAG.getNode(ISD::SHL, dl, MVT::i32, LoadVal,
|
|
|
|
DAG.getConstant(32 - LoadSize * 8, MVT::i32));
|
|
|
|
|
|
|
|
Offset += LoadSize;
|
|
|
|
RemainingSize -= LoadSize;
|
|
|
|
|
|
|
|
// Read second subword if necessary.
|
|
|
|
if (RemainingSize != 0) {
|
|
|
|
assert(RemainingSize == 1 && "There must be one byte remaining.");
|
|
|
|
LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
|
|
|
|
DAG.getConstant(Offset, MVT::i32));
|
|
|
|
unsigned Alignment = std::min(ByValAlign, (unsigned )2);
|
|
|
|
SDValue Subword = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
|
|
|
|
LoadPtr, MachinePointerInfo(),
|
|
|
|
MVT::i8, false, false, Alignment);
|
|
|
|
MemOpChains.push_back(Subword.getValue(1));
|
|
|
|
// Insert the loaded byte to LoadVal.
|
|
|
|
// FIXME: Use INS if supported by target.
|
|
|
|
unsigned ShiftAmt = isLittle ? 16 : 8;
|
|
|
|
SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i32, Subword,
|
|
|
|
DAG.getConstant(ShiftAmt, MVT::i32));
|
|
|
|
LoadVal = DAG.getNode(ISD::OR, dl, MVT::i32, LoadVal, Shift);
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned DstReg = O32IntRegs[LocMemOffset / 4];
|
|
|
|
RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
|
|
|
|
return;
|
2011-05-24 19:18:33 +00:00
|
|
|
}
|
2011-08-18 23:39:37 +00:00
|
|
|
|
|
|
|
// Create a fixed object on stack at offset LocMemOffset and copy
|
|
|
|
// remaining part of byval arg to it using memcpy.
|
|
|
|
SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
|
|
|
|
DAG.getConstant(Offset, MVT::i32));
|
|
|
|
LastFI = MFI->CreateFixedObject(RemainingSize, LocMemOffset, true);
|
|
|
|
SDValue Dst = DAG.getFrameIndex(LastFI, PtrType);
|
2011-09-19 20:26:02 +00:00
|
|
|
ByValChain = DAG.getMemcpy(ByValChain, dl, Dst, Src,
|
|
|
|
DAG.getConstant(RemainingSize, MVT::i32),
|
|
|
|
std::min(ByValAlign, (unsigned)4),
|
|
|
|
/*isVolatile=*/false, /*AlwaysInline=*/false,
|
|
|
|
MachinePointerInfo(0), MachinePointerInfo(0));
|
2011-05-24 19:18:33 +00:00
|
|
|
}
|
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
/// LowerCall - functions arguments are copied from virtual regs to
|
2009-01-26 03:15:54 +00:00
|
|
|
/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
|
2010-02-06 19:20:49 +00:00
|
|
|
/// TODO: isTailCall.
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
SDValue
|
2011-09-19 20:26:02 +00:00
|
|
|
MipsTargetLowering::LowerCall(SDValue InChain, SDValue Callee,
|
2009-09-02 08:44:58 +00:00
|
|
|
CallingConv::ID CallConv, bool isVarArg,
|
2010-01-27 00:07:07 +00:00
|
|
|
bool &isTailCall,
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
2010-07-07 15:54:55 +00:00
|
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
|
|
DebugLoc dl, SelectionDAG &DAG,
|
2010-04-17 15:26:15 +00:00
|
|
|
SmallVectorImpl<SDValue> &InVals) const {
|
2010-01-27 00:07:07 +00:00
|
|
|
// MIPs target does not yet support tail call optimization.
|
|
|
|
isTailCall = false;
|
2007-07-11 23:16:16 +00:00
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
2007-07-11 23:16:16 +00:00
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
2011-05-20 21:39:54 +00:00
|
|
|
const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
|
2009-09-01 17:27:58 +00:00
|
|
|
bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
|
2011-05-20 18:39:33 +00:00
|
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
// Analyze operands of the call, assigning locations to each operand.
|
|
|
|
SmallVector<CCValAssign, 16> ArgLocs;
|
2011-06-08 23:55:35 +00:00
|
|
|
CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
|
|
|
|
getTargetMachine(), ArgLocs, *DAG.getContext());
|
2007-07-11 23:16:16 +00:00
|
|
|
|
2011-10-28 18:47:24 +00:00
|
|
|
if (IsO32)
|
2011-05-19 18:06:05 +00:00
|
|
|
CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
|
2011-05-23 21:13:59 +00:00
|
|
|
else
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
|
2010-11-23 03:31:01 +00:00
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
// Get a count of how many bytes are to be pushed on the stack.
|
2011-06-08 17:39:33 +00:00
|
|
|
unsigned NextStackOffset = CCInfo.getNextStackOffset();
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2011-09-19 20:26:02 +00:00
|
|
|
// Chain is the output chain of the last Load/Store or CopyToReg node.
|
|
|
|
// ByValChain is the output chain of the last Memcpy node created for copying
|
|
|
|
// byval arguments to the stack.
|
|
|
|
SDValue Chain, CallSeqStart, ByValChain;
|
|
|
|
SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
|
|
|
|
Chain = CallSeqStart = DAG.getCALLSEQ_START(InChain, NextStackOffsetVal);
|
|
|
|
ByValChain = InChain;
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2011-05-25 17:32:06 +00:00
|
|
|
// If this is the first call, create a stack frame object that points to
|
2011-06-08 17:39:33 +00:00
|
|
|
// a location to which .cprestore saves $gp.
|
2011-10-28 19:49:00 +00:00
|
|
|
if (IsO32 && IsPIC && !MipsFI->getGPFI())
|
2011-05-20 23:22:14 +00:00
|
|
|
MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true));
|
|
|
|
|
2011-06-21 00:40:49 +00:00
|
|
|
// Get the frame index of the stack frame object that points to the location
|
|
|
|
// of dynamically allocated area on the stack.
|
|
|
|
int DynAllocFI = MipsFI->getDynAllocFI();
|
|
|
|
|
2011-06-08 17:39:33 +00:00
|
|
|
// Update size of the maximum argument space.
|
|
|
|
// For O32, a minimum of four words (16 bytes) of argument space is
|
|
|
|
// allocated.
|
2011-10-28 18:47:24 +00:00
|
|
|
if (IsO32)
|
2011-06-08 17:39:33 +00:00
|
|
|
NextStackOffset = std::max(NextStackOffset, (unsigned)16);
|
|
|
|
|
|
|
|
unsigned MaxCallFrameSize = MipsFI->getMaxCallFrameSize();
|
|
|
|
|
|
|
|
if (MaxCallFrameSize < NextStackOffset) {
|
|
|
|
MipsFI->setMaxCallFrameSize(NextStackOffset);
|
|
|
|
|
2011-06-21 00:40:49 +00:00
|
|
|
// Set the offsets relative to $sp of the $gp restore slot and dynamically
|
|
|
|
// allocated stack space. These offsets must be aligned to a boundary
|
|
|
|
// determined by the stack alignment of the ABI.
|
|
|
|
unsigned StackAlignment = TFL->getStackAlignment();
|
|
|
|
NextStackOffset = (NextStackOffset + StackAlignment - 1) /
|
|
|
|
StackAlignment * StackAlignment;
|
|
|
|
|
2011-10-28 19:49:00 +00:00
|
|
|
if (MipsFI->needGPSaveRestore())
|
2011-06-21 00:40:49 +00:00
|
|
|
MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset);
|
|
|
|
|
|
|
|
MFI->setObjectOffset(DynAllocFI, NextStackOffset);
|
2011-06-08 17:39:33 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// With EABI is it possible to have 16 args on registers.
|
|
|
|
SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
|
|
|
|
SmallVector<SDValue, 8> MemOpChains;
|
|
|
|
|
2011-06-08 23:55:35 +00:00
|
|
|
int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0;
|
2011-05-20 23:22:14 +00:00
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
// Walk the register/memloc assignments, inserting copies/loads.
|
|
|
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
2010-07-07 15:54:55 +00:00
|
|
|
SDValue Arg = OutVals[i];
|
2007-06-06 07:42:06 +00:00
|
|
|
CCValAssign &VA = ArgLocs[i];
|
2011-10-28 19:49:00 +00:00
|
|
|
MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
// Promote the value if needed.
|
|
|
|
switch (VA.getLocInfo()) {
|
2009-07-14 16:55:14 +00:00
|
|
|
default: llvm_unreachable("Unknown loc info!");
|
2010-11-23 03:31:01 +00:00
|
|
|
case CCValAssign::Full:
|
2011-10-28 19:49:00 +00:00
|
|
|
if (VA.isRegLoc()) {
|
|
|
|
if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
|
|
|
|
(ValVT == MVT::f64 && LocVT == MVT::i64))
|
|
|
|
Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg);
|
|
|
|
else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
|
2011-04-15 21:51:11 +00:00
|
|
|
SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
|
|
|
|
Arg, DAG.getConstant(0, MVT::i32));
|
2011-04-15 21:00:26 +00:00
|
|
|
SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
|
|
|
|
Arg, DAG.getConstant(1, MVT::i32));
|
2011-04-15 19:52:08 +00:00
|
|
|
if (!Subtarget->isLittle())
|
|
|
|
std::swap(Lo, Hi);
|
2011-09-23 00:58:33 +00:00
|
|
|
unsigned LocRegLo = VA.getLocReg();
|
|
|
|
unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
|
|
|
|
RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
|
|
|
|
RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
|
2009-03-19 02:12:28 +00:00
|
|
|
continue;
|
2010-11-23 03:31:01 +00:00
|
|
|
}
|
2009-03-19 02:12:28 +00:00
|
|
|
}
|
|
|
|
break;
|
2008-03-17 06:57:02 +00:00
|
|
|
case CCValAssign::SExt:
|
2011-10-28 19:49:00 +00:00
|
|
|
Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg);
|
2008-03-17 06:57:02 +00:00
|
|
|
break;
|
|
|
|
case CCValAssign::ZExt:
|
2011-10-28 19:49:00 +00:00
|
|
|
Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg);
|
2008-03-17 06:57:02 +00:00
|
|
|
break;
|
|
|
|
case CCValAssign::AExt:
|
2011-10-28 19:49:00 +00:00
|
|
|
Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg);
|
2008-03-17 06:57:02 +00:00
|
|
|
break;
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
2010-11-23 03:31:01 +00:00
|
|
|
|
|
|
|
// Arguments that can be passed on register must be kept at
|
2007-11-05 03:02:32 +00:00
|
|
|
// RegsToPass vector
|
2007-06-06 07:42:06 +00:00
|
|
|
if (VA.isRegLoc()) {
|
|
|
|
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
|
2008-03-17 06:57:02 +00:00
|
|
|
continue;
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
2010-11-23 03:31:01 +00:00
|
|
|
|
2009-03-19 02:12:28 +00:00
|
|
|
// Register can't get to this point...
|
2008-03-17 06:57:02 +00:00
|
|
|
assert(VA.isMemLoc());
|
2010-11-23 03:31:01 +00:00
|
|
|
|
2011-06-08 23:55:35 +00:00
|
|
|
// ByVal Arg.
|
2011-05-24 19:18:33 +00:00
|
|
|
ISD::ArgFlagsTy Flags = Outs[i].Flags;
|
|
|
|
if (Flags.isByVal()) {
|
2011-10-28 18:47:24 +00:00
|
|
|
assert(IsO32 &&
|
2011-05-24 19:18:33 +00:00
|
|
|
"No support for ByVal args by ABIs other than O32 yet.");
|
|
|
|
assert(Flags.getByValSize() &&
|
|
|
|
"ByVal args of size 0 should have been ignored by front-end.");
|
2011-09-19 20:26:02 +00:00
|
|
|
WriteByValArg(ByValChain, Chain, dl, RegsToPass, MemOpChains, LastFI, MFI,
|
|
|
|
DAG, Arg, VA, Flags, getPointerTy(), Subtarget->isLittle());
|
2011-05-24 19:18:33 +00:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2008-03-17 06:57:02 +00:00
|
|
|
// Create the frame index object for this incoming parameter
|
2011-10-28 19:49:00 +00:00
|
|
|
LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
|
2011-05-24 00:23:52 +00:00
|
|
|
VA.getLocMemOffset(), true);
|
2011-05-20 23:22:14 +00:00
|
|
|
SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
|
2008-03-17 06:57:02 +00:00
|
|
|
|
2010-11-23 03:31:01 +00:00
|
|
|
// emit ISD::STORE whichs stores the
|
2008-03-17 06:57:02 +00:00
|
|
|
// parameter value to a stack Location
|
2010-09-21 17:50:43 +00:00
|
|
|
MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
|
|
|
|
MachinePointerInfo(),
|
2010-02-15 16:56:10 +00:00
|
|
|
false, false, 0));
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
2011-06-08 17:39:33 +00:00
|
|
|
// Extend range of indices of frame objects for outgoing arguments that were
|
|
|
|
// created during this function call. Skip this step if no such objects were
|
|
|
|
// created.
|
|
|
|
if (LastFI)
|
|
|
|
MipsFI->extendOutArgFIRange(FirstFI, LastFI);
|
|
|
|
|
2011-09-19 20:26:02 +00:00
|
|
|
// If a memcpy has been created to copy a byval arg to a stack, replace the
|
|
|
|
// chain input of CallSeqStart with ByValChain.
|
|
|
|
if (InChain != ByValChain)
|
|
|
|
DAG.UpdateNodeOperands(CallSeqStart.getNode(), ByValChain,
|
|
|
|
NextStackOffsetVal);
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
// Transform all store nodes into one single node because all store
|
|
|
|
// nodes are independent of each other.
|
2010-11-23 03:31:01 +00:00
|
|
|
if (!MemOpChains.empty())
|
|
|
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
2007-06-06 07:42:06 +00:00
|
|
|
&MemOpChains[0], MemOpChains.size());
|
|
|
|
|
2008-09-16 21:48:12 +00:00
|
|
|
// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
|
2010-11-23 03:31:01 +00:00
|
|
|
// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
|
|
|
|
// node so that legalize doesn't hack it.
|
2011-10-28 19:49:00 +00:00
|
|
|
unsigned char OpFlag;
|
|
|
|
bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25
|
2011-04-04 17:11:07 +00:00
|
|
|
bool LoadSymAddr = false;
|
2011-04-07 19:51:44 +00:00
|
|
|
SDValue CalleeLo;
|
2011-04-04 17:11:07 +00:00
|
|
|
|
|
|
|
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
|
2011-10-28 19:49:00 +00:00
|
|
|
if (IsPICCall && G->getGlobal()->hasInternalLinkage()) {
|
|
|
|
OpFlag = IsO32 ? MipsII::MO_GOT : MipsII::MO_GOT_PAGE;
|
|
|
|
unsigned char LoFlag = IsO32 ? MipsII::MO_ABS_LO : MipsII::MO_GOT_OFST;
|
|
|
|
Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0,
|
|
|
|
OpFlag);
|
2011-04-07 19:51:44 +00:00
|
|
|
CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(),
|
2011-10-28 19:49:00 +00:00
|
|
|
0, LoFlag);
|
2011-04-07 19:51:44 +00:00
|
|
|
} else {
|
2011-10-28 19:49:00 +00:00
|
|
|
OpFlag = IsPICCall ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
|
2011-04-07 19:51:44 +00:00
|
|
|
Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
|
|
|
|
getPointerTy(), 0, OpFlag);
|
|
|
|
}
|
|
|
|
|
2011-04-04 17:11:07 +00:00
|
|
|
LoadSymAddr = true;
|
|
|
|
}
|
|
|
|
else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
|
2011-10-28 19:49:00 +00:00
|
|
|
if (IsN64 || (!IsO32 && IsPIC))
|
|
|
|
OpFlag = MipsII::MO_GOT_DISP;
|
|
|
|
else if (!IsPIC) // !N64 && static
|
|
|
|
OpFlag = MipsII::MO_NO_FLAG;
|
|
|
|
else // O32 & PIC
|
|
|
|
OpFlag = MipsII::MO_GOT_CALL;
|
2010-11-23 03:31:01 +00:00
|
|
|
Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
|
2011-10-28 19:49:00 +00:00
|
|
|
getPointerTy(), OpFlag);
|
2011-04-04 17:11:07 +00:00
|
|
|
LoadSymAddr = true;
|
|
|
|
}
|
|
|
|
|
2011-05-20 02:30:51 +00:00
|
|
|
SDValue InFlag;
|
|
|
|
|
2011-04-04 17:11:07 +00:00
|
|
|
// Create nodes that load address of callee and copy it to T9
|
2011-10-28 19:49:00 +00:00
|
|
|
if (IsPICCall) {
|
2011-04-04 17:11:07 +00:00
|
|
|
if (LoadSymAddr) {
|
2011-04-07 19:51:44 +00:00
|
|
|
// Load callee address
|
2011-10-28 19:49:00 +00:00
|
|
|
Callee = DAG.getNode(MipsISD::WrapperPIC, dl, getPointerTy(), Callee);
|
|
|
|
SDValue LoadValue = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
|
|
|
|
Callee, MachinePointerInfo::getGOT(),
|
2011-11-08 18:42:53 +00:00
|
|
|
false, false, false, 0);
|
2011-04-07 19:51:44 +00:00
|
|
|
|
|
|
|
// Use GOT+LO if callee has internal linkage.
|
|
|
|
if (CalleeLo.getNode()) {
|
2011-10-28 19:49:00 +00:00
|
|
|
SDValue Lo = DAG.getNode(MipsISD::Lo, dl, getPointerTy(), CalleeLo);
|
|
|
|
Callee = DAG.getNode(ISD::ADD, dl, getPointerTy(), LoadValue, Lo);
|
2011-04-07 19:51:44 +00:00
|
|
|
} else
|
|
|
|
Callee = LoadValue;
|
2011-04-04 17:11:07 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
// copy to T9
|
2011-10-28 19:49:00 +00:00
|
|
|
unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
|
|
|
|
Chain = DAG.getCopyToReg(Chain, dl, T9Reg, Callee, SDValue(0, 0));
|
2011-04-04 17:11:07 +00:00
|
|
|
InFlag = Chain.getValue(1);
|
2011-10-28 19:49:00 +00:00
|
|
|
Callee = DAG.getRegister(T9Reg, getPointerTy());
|
2011-04-04 17:11:07 +00:00
|
|
|
}
|
2008-09-16 21:48:12 +00:00
|
|
|
|
2011-05-20 02:30:51 +00:00
|
|
|
// Build a sequence of copy-to-reg nodes chained together with token
|
|
|
|
// chain and flag operands which copy the outgoing args into registers.
|
|
|
|
// The InFlag in necessary since all emitted instructions must be
|
|
|
|
// stuck together.
|
|
|
|
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
|
|
|
|
Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
|
|
|
|
RegsToPass[i].second, InFlag);
|
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
}
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
// MipsJmpLink = #chain, #target_address, #opt_in_flags...
|
2010-11-23 03:31:01 +00:00
|
|
|
// = Chain, Callee, Reg#1, Reg#2, ...
|
2007-06-06 07:42:06 +00:00
|
|
|
//
|
|
|
|
// Returns a chain & a flag for retval copy to use.
|
2010-12-21 02:38:05 +00:00
|
|
|
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
|
2008-07-27 21:46:04 +00:00
|
|
|
SmallVector<SDValue, 8> Ops;
|
2007-06-06 07:42:06 +00:00
|
|
|
Ops.push_back(Chain);
|
|
|
|
Ops.push_back(Callee);
|
|
|
|
|
2010-11-23 03:31:01 +00:00
|
|
|
// Add argument registers to the end of the list so that they are
|
2007-06-06 07:42:06 +00:00
|
|
|
// known live into the call.
|
|
|
|
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
|
|
|
|
Ops.push_back(DAG.getRegister(RegsToPass[i].first,
|
|
|
|
RegsToPass[i].second.getValueType()));
|
|
|
|
|
2008-08-28 21:40:38 +00:00
|
|
|
if (InFlag.getNode())
|
2007-06-06 07:42:06 +00:00
|
|
|
Ops.push_back(InFlag);
|
|
|
|
|
2009-02-04 20:06:27 +00:00
|
|
|
Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
|
2007-06-06 07:42:06 +00:00
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
|
2010-01-30 18:32:07 +00:00
|
|
|
// Create the CALLSEQ_END node.
|
2011-06-21 01:02:03 +00:00
|
|
|
Chain = DAG.getCALLSEQ_END(Chain,
|
|
|
|
DAG.getIntPtrConstant(NextStackOffset, true),
|
2010-01-30 18:32:07 +00:00
|
|
|
DAG.getIntPtrConstant(0, true), InFlag);
|
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
// Handle result values, copying them out of physregs into vregs that we
|
|
|
|
// return.
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
|
|
|
|
Ins, dl, DAG, InVals);
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
/// LowerCallResult - Lower the result values of a call into the
|
|
|
|
/// appropriate copies out of appropriate physical registers.
|
|
|
|
SDValue
|
|
|
|
MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
|
2009-09-02 08:44:58 +00:00
|
|
|
CallingConv::ID CallConv, bool isVarArg,
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
|
|
DebugLoc dl, SelectionDAG &DAG,
|
2010-04-17 15:26:15 +00:00
|
|
|
SmallVectorImpl<SDValue> &InVals) const {
|
2007-06-06 07:42:06 +00:00
|
|
|
// Assign locations to each value returned by this call.
|
|
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
2011-06-08 23:55:35 +00:00
|
|
|
CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
|
|
|
|
getTargetMachine(), RVLocs, *DAG.getContext());
|
2007-07-11 23:16:16 +00:00
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
// Copy all of the result registers out of their specified physreg.
|
|
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
2009-02-04 20:06:27 +00:00
|
|
|
Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
RVLocs[i].getValVT(), InFlag).getValue(1);
|
2007-06-06 07:42:06 +00:00
|
|
|
InFlag = Chain.getValue(2);
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
InVals.push_back(Chain.getValue(0));
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
2007-11-05 03:02:32 +00:00
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
return Chain;
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
// Formal Arguments Calling Convention Implementation
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2011-05-24 19:18:33 +00:00
|
|
|
static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl,
|
|
|
|
std::vector<SDValue>& OutChains,
|
|
|
|
SelectionDAG &DAG, unsigned NumWords, SDValue FIN,
|
|
|
|
const CCValAssign &VA, const ISD::ArgFlagsTy& Flags) {
|
|
|
|
unsigned LocMem = VA.getLocMemOffset();
|
|
|
|
unsigned FirstWord = LocMem / 4;
|
|
|
|
|
|
|
|
// copy register A0 - A3 to frame object
|
|
|
|
for (unsigned i = 0; i < NumWords; ++i) {
|
|
|
|
unsigned CurWord = FirstWord + i;
|
|
|
|
if (CurWord >= O32IntRegsSize)
|
|
|
|
break;
|
|
|
|
|
|
|
|
unsigned SrcReg = O32IntRegs[CurWord];
|
|
|
|
unsigned Reg = AddLiveIn(MF, SrcReg, Mips::CPURegsRegisterClass);
|
|
|
|
SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN,
|
|
|
|
DAG.getConstant(i * 4, MVT::i32));
|
|
|
|
SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32),
|
|
|
|
StorePtr, MachinePointerInfo(), false,
|
|
|
|
false, 0);
|
|
|
|
OutChains.push_back(Store);
|
|
|
|
}
|
|
|
|
}
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2010-11-23 03:31:01 +00:00
|
|
|
/// LowerFormalArguments - transform physical registers into virtual registers
|
2010-02-06 19:20:49 +00:00
|
|
|
/// and generate load operations for arguments places on the stack.
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
SDValue
|
|
|
|
MipsTargetLowering::LowerFormalArguments(SDValue Chain,
|
2011-04-15 21:00:26 +00:00
|
|
|
CallingConv::ID CallConv,
|
|
|
|
bool isVarArg,
|
|
|
|
const SmallVectorImpl<ISD::InputArg>
|
|
|
|
&Ins,
|
|
|
|
DebugLoc dl, SelectionDAG &DAG,
|
|
|
|
SmallVectorImpl<SDValue> &InVals)
|
2011-04-15 21:51:11 +00:00
|
|
|
const {
|
2008-08-04 07:12:52 +00:00
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
2007-06-06 07:42:06 +00:00
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
2007-08-28 05:08:16 +00:00
|
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
2007-07-11 23:16:16 +00:00
|
|
|
|
2010-04-17 14:41:14 +00:00
|
|
|
MipsFI->setVarArgsFrameIndex(0);
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2010-02-06 19:20:49 +00:00
|
|
|
// Used with vargs to acumulate store chains.
|
|
|
|
std::vector<SDValue> OutChains;
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
// Assign locations to all of the incoming arguments.
|
|
|
|
SmallVector<CCValAssign, 16> ArgLocs;
|
2011-06-08 23:55:35 +00:00
|
|
|
CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
|
|
|
|
getTargetMachine(), ArgLocs, *DAG.getContext());
|
2007-07-11 23:16:16 +00:00
|
|
|
|
2011-10-28 18:47:24 +00:00
|
|
|
if (IsO32)
|
2011-05-19 18:06:05 +00:00
|
|
|
CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32);
|
2009-03-19 02:12:28 +00:00
|
|
|
else
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
|
2009-03-19 02:12:28 +00:00
|
|
|
|
2011-05-20 23:22:14 +00:00
|
|
|
int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function.
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
|
|
|
CCValAssign &VA = ArgLocs[i];
|
2011-10-28 19:55:48 +00:00
|
|
|
EVT ValVT = VA.getValVT();
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
// Arguments stored on registers
|
|
|
|
if (VA.isRegLoc()) {
|
2009-08-10 22:56:29 +00:00
|
|
|
EVT RegVT = VA.getLocVT();
|
2011-05-24 00:23:52 +00:00
|
|
|
unsigned ArgReg = VA.getLocReg();
|
2008-07-09 05:55:53 +00:00
|
|
|
TargetRegisterClass *RC = 0;
|
2009-03-19 02:12:28 +00:00
|
|
|
|
2009-08-11 20:47:22 +00:00
|
|
|
if (RegVT == MVT::i32)
|
2010-11-23 03:31:01 +00:00
|
|
|
RC = Mips::CPURegsRegisterClass;
|
2011-09-24 01:34:44 +00:00
|
|
|
else if (RegVT == MVT::i64)
|
|
|
|
RC = Mips::CPU64RegsRegisterClass;
|
2010-11-23 03:31:01 +00:00
|
|
|
else if (RegVT == MVT::f32)
|
2009-03-21 00:05:07 +00:00
|
|
|
RC = Mips::FGR32RegisterClass;
|
2011-09-26 21:37:50 +00:00
|
|
|
else if (RegVT == MVT::f64)
|
2011-09-26 21:55:17 +00:00
|
|
|
RC = HasMips64 ? Mips::FGR64RegisterClass : Mips::AFGR64RegisterClass;
|
2011-09-26 21:37:50 +00:00
|
|
|
else
|
2010-02-06 19:20:49 +00:00
|
|
|
llvm_unreachable("RegVT not supported by FormalArguments Lowering");
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2010-11-23 03:31:01 +00:00
|
|
|
// Transform the arguments stored on
|
2007-06-06 07:42:06 +00:00
|
|
|
// physical registers into virtual ones
|
2011-05-24 00:23:52 +00:00
|
|
|
unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC);
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
|
2010-11-23 03:31:01 +00:00
|
|
|
|
|
|
|
// If this is an 8 or 16-bit value, it has been passed promoted
|
|
|
|
// to 32 bits. Insert an assert[sz]ext to capture this, then
|
2007-06-06 07:42:06 +00:00
|
|
|
// truncate to the right size.
|
2009-03-19 02:12:28 +00:00
|
|
|
if (VA.getLocInfo() != CCValAssign::Full) {
|
2009-03-26 05:28:14 +00:00
|
|
|
unsigned Opcode = 0;
|
2009-03-19 02:12:28 +00:00
|
|
|
if (VA.getLocInfo() == CCValAssign::SExt)
|
|
|
|
Opcode = ISD::AssertSext;
|
|
|
|
else if (VA.getLocInfo() == CCValAssign::ZExt)
|
|
|
|
Opcode = ISD::AssertZext;
|
2009-03-26 05:28:14 +00:00
|
|
|
if (Opcode)
|
2010-11-23 03:31:01 +00:00
|
|
|
ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
|
2011-10-28 19:55:48 +00:00
|
|
|
DAG.getValueType(ValVT));
|
|
|
|
ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue);
|
2009-03-19 02:12:28 +00:00
|
|
|
}
|
|
|
|
|
2011-10-28 19:55:48 +00:00
|
|
|
// Handle floating point arguments passed in integer registers.
|
|
|
|
if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
|
|
|
|
(RegVT == MVT::i64 && ValVT == MVT::f64))
|
|
|
|
ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue);
|
|
|
|
else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) {
|
|
|
|
unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
|
|
|
|
getNextIntArgReg(ArgReg), RC);
|
|
|
|
SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
|
|
|
|
if (!Subtarget->isLittle())
|
|
|
|
std::swap(ArgValue, ArgValue2);
|
|
|
|
ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64,
|
|
|
|
ArgValue, ArgValue2);
|
2009-03-19 02:12:28 +00:00
|
|
|
}
|
2007-06-06 07:42:06 +00:00
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
InVals.push_back(ArgValue);
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
} else { // VA.isRegLoc()
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
// sanity check
|
|
|
|
assert(VA.isMemLoc());
|
2010-02-06 19:20:49 +00:00
|
|
|
|
2011-05-24 19:18:33 +00:00
|
|
|
ISD::ArgFlagsTy Flags = Ins[i].Flags;
|
|
|
|
|
|
|
|
if (Flags.isByVal()) {
|
2011-10-28 18:47:24 +00:00
|
|
|
assert(IsO32 &&
|
2011-05-24 19:18:33 +00:00
|
|
|
"No support for ByVal args by ABIs other than O32 yet.");
|
|
|
|
assert(Flags.getByValSize() &&
|
|
|
|
"ByVal args of size 0 should have been ignored by front-end.");
|
|
|
|
unsigned NumWords = (Flags.getByValSize() + 3) / 4;
|
|
|
|
LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(),
|
|
|
|
true);
|
|
|
|
SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
|
|
|
|
InVals.push_back(FIN);
|
|
|
|
ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags);
|
|
|
|
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2010-11-23 03:31:01 +00:00
|
|
|
// The stack pointer offset is relative to the caller stack frame.
|
2011-10-28 19:55:48 +00:00
|
|
|
LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
|
2011-05-24 00:23:52 +00:00
|
|
|
VA.getLocMemOffset(), true);
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
// Create load nodes to retrieve arguments from the stack
|
2011-05-20 23:22:14 +00:00
|
|
|
SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
|
2011-10-28 19:55:48 +00:00
|
|
|
InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN,
|
2011-05-20 23:22:14 +00:00
|
|
|
MachinePointerInfo::getFixedStack(LastFI),
|
2011-11-08 18:42:53 +00:00
|
|
|
false, false, false, 0));
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
}
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
|
|
|
|
// The mips ABIs for returning structs by value requires that we copy
|
|
|
|
// the sret argument into $v0 for the return. Save the argument into
|
|
|
|
// a virtual register so that we can access it from the return points.
|
|
|
|
if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
|
|
|
|
unsigned Reg = MipsFI->getSRetReturnReg();
|
|
|
|
if (!Reg) {
|
2009-08-11 20:47:22 +00:00
|
|
|
Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
MipsFI->setSRetReturnReg(Reg);
|
|
|
|
}
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
|
2009-08-11 20:47:22 +00:00
|
|
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
}
|
|
|
|
|
2011-10-28 18:47:24 +00:00
|
|
|
if (isVarArg && IsO32) {
|
2011-05-24 00:23:52 +00:00
|
|
|
// Record the frame index of the first variable argument
|
2011-06-08 23:55:35 +00:00
|
|
|
// which is a value necessary to VASTART.
|
2011-05-24 00:23:52 +00:00
|
|
|
unsigned NextStackOffset = CCInfo.getNextStackOffset();
|
2011-05-24 19:18:33 +00:00
|
|
|
assert(NextStackOffset % 4 == 0 &&
|
|
|
|
"NextStackOffset must be aligned to 4-byte boundaries.");
|
2011-05-24 00:23:52 +00:00
|
|
|
LastFI = MFI->CreateFixedObject(4, NextStackOffset, true);
|
|
|
|
MipsFI->setVarArgsFrameIndex(LastFI);
|
2011-05-25 17:32:06 +00:00
|
|
|
|
|
|
|
// If NextStackOffset is smaller than o32's 16-byte reserved argument area,
|
|
|
|
// copy the integer registers that have not been used for argument passing
|
|
|
|
// to the caller's stack frame.
|
2011-05-24 00:23:52 +00:00
|
|
|
for (; NextStackOffset < 16; NextStackOffset += 4) {
|
2011-03-09 19:22:22 +00:00
|
|
|
TargetRegisterClass *RC = Mips::CPURegsRegisterClass;
|
2011-05-24 00:23:52 +00:00
|
|
|
unsigned Idx = NextStackOffset / 4;
|
|
|
|
unsigned Reg = AddLiveIn(DAG.getMachineFunction(), O32IntRegs[Idx], RC);
|
|
|
|
SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32);
|
2011-05-23 20:16:59 +00:00
|
|
|
LastFI = MFI->CreateFixedObject(4, NextStackOffset, true);
|
2011-05-24 00:23:52 +00:00
|
|
|
SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
|
|
|
|
OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
|
|
|
|
MachinePointerInfo(),
|
|
|
|
false, false, 0));
|
2010-02-06 19:20:49 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-05-20 23:22:14 +00:00
|
|
|
MipsFI->setLastInArgFI(LastFI);
|
|
|
|
|
2010-11-23 03:31:01 +00:00
|
|
|
// All stores are grouped in one node to allow the matching between
|
2010-02-06 19:20:49 +00:00
|
|
|
// the size of Ins and InVals. This only happens when on varg functions
|
|
|
|
if (!OutChains.empty()) {
|
|
|
|
OutChains.push_back(Chain);
|
|
|
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
|
|
|
&OutChains[0], OutChains.size());
|
|
|
|
}
|
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
return Chain;
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 07:42:06 +00:00
|
|
|
// Return Value Calling Convention Implementation
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 07:42:06 +00:00
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
SDValue
|
|
|
|
MipsTargetLowering::LowerReturn(SDValue Chain,
|
2009-09-02 08:44:58 +00:00
|
|
|
CallingConv::ID CallConv, bool isVarArg,
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
2010-07-07 15:54:55 +00:00
|
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
2010-04-17 15:26:15 +00:00
|
|
|
DebugLoc dl, SelectionDAG &DAG) const {
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
// CCValAssign - represent the assignment of
|
|
|
|
// the return value to a location
|
|
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
|
|
|
|
|
|
|
// CCState - Info about the registers and stack slot.
|
2011-06-08 23:55:35 +00:00
|
|
|
CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
|
|
|
|
getTargetMachine(), RVLocs, *DAG.getContext());
|
2007-06-06 07:42:06 +00:00
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-05 01:29:28 +00:00
|
|
|
// Analize return values.
|
|
|
|
CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
|
2007-06-06 07:42:06 +00:00
|
|
|
|
2010-11-23 03:31:01 +00:00
|
|
|
// If this is the first return lowered for this function, add
|
2007-06-06 07:42:06 +00:00
|
|
|
// the regs to the liveout set for the function.
|
2007-12-31 04:13:23 +00:00
|
|
|
if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
|
2007-06-06 07:42:06 +00:00
|
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i)
|
2007-07-11 23:16:16 +00:00
|
|
|
if (RVLocs[i].isRegLoc())
|
2011-04-15 21:51:11 +00:00
|
|
|
DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
|
|
|
|
2008-07-27 21:46:04 +00:00
|
|
|
SDValue Flag;
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
// Copy the result values into the output registers.
|
|
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
|
|
|
CCValAssign &VA = RVLocs[i];
|
|
|
|
assert(VA.isRegLoc() && "Can only return in registers!");
|
|
|
|
|
2010-11-23 03:31:01 +00:00
|
|
|
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
|
2010-07-07 15:54:55 +00:00
|
|
|
OutVals[i], Flag);
|
2007-06-06 07:42:06 +00:00
|
|
|
|
|
|
|
// guarantee that all emitted copies are
|
|
|
|
// stuck together, avoiding something bad
|
|
|
|
Flag = Chain.getValue(1);
|
|
|
|
}
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
// The mips ABIs for returning structs by value requires that we copy
|
|
|
|
// the sret argument into $v0 for the return. We saved the argument into
|
|
|
|
// a virtual register in the entry block, so now we copy the value out
|
|
|
|
// and into $v0.
|
|
|
|
if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
|
|
|
unsigned Reg = MipsFI->getSRetReturnReg();
|
|
|
|
|
2010-11-23 03:31:01 +00:00
|
|
|
if (!Reg)
|
2009-07-14 16:55:14 +00:00
|
|
|
llvm_unreachable("sret virtual register not created in the entry block");
|
2009-02-04 23:02:30 +00:00
|
|
|
SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
|
2009-02-04 23:02:30 +00:00
|
|
|
Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
Flag = Chain.getValue(1);
|
|
|
|
}
|
|
|
|
|
2007-06-06 07:42:06 +00:00
|
|
|
// Return on Mips is always a "jr $ra"
|
2008-08-28 21:40:38 +00:00
|
|
|
if (Flag.getNode())
|
2010-11-23 03:31:01 +00:00
|
|
|
return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
|
2009-08-11 20:47:22 +00:00
|
|
|
Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
|
2007-06-06 07:42:06 +00:00
|
|
|
else // Return Void
|
2010-11-23 03:31:01 +00:00
|
|
|
return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
|
2009-08-11 20:47:22 +00:00
|
|
|
Chain, DAG.getRegister(Mips::RA, MVT::i32));
|
2007-06-06 07:42:06 +00:00
|
|
|
}
|
2007-08-21 16:09:25 +00:00
|
|
|
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-08-21 16:09:25 +00:00
|
|
|
// Mips Inline Assembly Support
|
2011-04-15 21:51:11 +00:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-08-21 16:09:25 +00:00
|
|
|
|
|
|
|
/// getConstraintType - Given a constraint letter, return the type of
|
|
|
|
/// constraint it is for this target.
|
|
|
|
MipsTargetLowering::ConstraintType MipsTargetLowering::
|
2010-11-23 03:31:01 +00:00
|
|
|
getConstraintType(const std::string &Constraint) const
|
2007-08-21 16:09:25 +00:00
|
|
|
{
|
2010-11-23 03:31:01 +00:00
|
|
|
// Mips specific constrainy
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
// GCC config/mips/constraints.md
|
|
|
|
//
|
2010-11-23 03:31:01 +00:00
|
|
|
// 'd' : An address register. Equivalent to r
|
|
|
|
// unless generating MIPS16 code.
|
|
|
|
// 'y' : Equivalent to r; retained for
|
|
|
|
// backwards compatibility.
|
|
|
|
// 'f' : Floating Point registers.
|
2007-08-21 16:09:25 +00:00
|
|
|
if (Constraint.size() == 1) {
|
|
|
|
switch (Constraint[0]) {
|
|
|
|
default : break;
|
2010-11-23 03:31:01 +00:00
|
|
|
case 'd':
|
|
|
|
case 'y':
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
case 'f':
|
2007-08-21 16:09:25 +00:00
|
|
|
return C_RegisterClass;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return TargetLowering::getConstraintType(Constraint);
|
|
|
|
}
|
|
|
|
|
2010-10-29 17:29:13 +00:00
|
|
|
/// Examine constraint type and operand type and determine a weight value.
|
|
|
|
/// This object must already have been set up with the operand type
|
|
|
|
/// and the current alternative constraint selected.
|
|
|
|
TargetLowering::ConstraintWeight
|
|
|
|
MipsTargetLowering::getSingleConstraintMatchWeight(
|
|
|
|
AsmOperandInfo &info, const char *constraint) const {
|
|
|
|
ConstraintWeight weight = CW_Invalid;
|
|
|
|
Value *CallOperandVal = info.CallOperandVal;
|
|
|
|
// If we don't have a value, we can't do a match,
|
|
|
|
// but allow it at the lowest weight.
|
|
|
|
if (CallOperandVal == NULL)
|
|
|
|
return CW_Default;
|
2011-07-18 04:54:35 +00:00
|
|
|
Type *type = CallOperandVal->getType();
|
2010-10-29 17:29:13 +00:00
|
|
|
// Look at the constraint type.
|
|
|
|
switch (*constraint) {
|
|
|
|
default:
|
|
|
|
weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
|
|
|
|
break;
|
2010-11-23 03:31:01 +00:00
|
|
|
case 'd':
|
|
|
|
case 'y':
|
2010-10-29 17:29:13 +00:00
|
|
|
if (type->isIntegerTy())
|
|
|
|
weight = CW_Register;
|
|
|
|
break;
|
|
|
|
case 'f':
|
|
|
|
if (type->isFloatTy())
|
|
|
|
weight = CW_Register;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return weight;
|
|
|
|
}
|
|
|
|
|
2011-06-29 19:33:04 +00:00
|
|
|
/// Given a register class constraint, like 'r', if this corresponds directly
|
|
|
|
/// to an LLVM register class, return a register of 0 and the register class
|
|
|
|
/// pointer.
|
2007-08-21 16:09:25 +00:00
|
|
|
std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
|
2009-08-10 22:56:29 +00:00
|
|
|
getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
|
2007-08-21 16:09:25 +00:00
|
|
|
{
|
|
|
|
if (Constraint.size() == 1) {
|
|
|
|
switch (Constraint[0]) {
|
2011-06-29 19:04:31 +00:00
|
|
|
case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
|
|
|
|
case 'y': // Same as 'r'. Exists for compatibility.
|
2007-08-21 16:09:25 +00:00
|
|
|
case 'r':
|
|
|
|
return std::make_pair(0U, Mips::CPURegsRegisterClass);
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
case 'f':
|
2009-08-11 20:47:22 +00:00
|
|
|
if (VT == MVT::f32)
|
2009-03-21 00:05:07 +00:00
|
|
|
return std::make_pair(0U, Mips::FGR32RegisterClass);
|
2010-11-23 03:31:01 +00:00
|
|
|
if (VT == MVT::f64)
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-05 19:05:21 +00:00
|
|
|
if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
|
|
|
|
return std::make_pair(0U, Mips::AFGR64RegisterClass);
|
2011-06-29 19:04:31 +00:00
|
|
|
break;
|
2007-08-21 16:09:25 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
|
|
|
|
}
|
|
|
|
|
Teach DAGCombine to fold constant offsets into GlobalAddress nodes,
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)
This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.
This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.
Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.
The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-18 02:06:02 +00:00
|
|
|
bool
|
|
|
|
MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
|
|
|
|
// The Mips target isn't yet aware of offsets.
|
|
|
|
return false;
|
|
|
|
}
|
2009-10-27 19:56:55 +00:00
|
|
|
|
2009-10-28 01:43:28 +00:00
|
|
|
bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
|
|
|
|
if (VT != MVT::f32 && VT != MVT::f64)
|
|
|
|
return false;
|
2011-01-18 19:41:41 +00:00
|
|
|
if (Imm.isNegZero())
|
|
|
|
return false;
|
2009-10-27 19:56:55 +00:00
|
|
|
return Imm.isZero();
|
|
|
|
}
|