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Author SHA1 Message Date
David Blaikie
0becc96b24 Add some missing anchors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145578 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 08:00:17 +00:00
Eli Friedman
522fb8cc01 Pass AVX vectors which are arguments to varargs functions on the stack. <rdar://problem/10463281>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145573 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 04:49:21 +00:00
Pete Cooper
dbaad16959 Removed use of grep from test and moved it to be with other icmp tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145570 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 04:35:26 +00:00
Pete Cooper
65a6b57c33 Added instcombine pattern to spot comparing -val or val against 0. 
(val != 0) == (-val != 0) so "abs(val) != 0" becomes "val != 0"

Fixes <rdar://problem/10482509>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145563 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 03:58:40 +00:00
Chad Rosier
618c1dbd29 Propagate TargetLibraryInfo throughout ConstantFolding.cpp and 
InstructionSimplify.cpp.  Other fixups as needed.
Part of rdar://10500969

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145559 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 03:08:23 +00:00
Nick Lewycky
66d004ef70 Make use of "getScalarType()". No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145556 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 02:39:36 +00:00
Eli Friedman
32e698cc10 Small fix for assembler generation on Darwin PPC64. Patch by Michael Kostylev. PR11437. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145553 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-01 01:43:47 +00:00
Jim Grosbach
4a2242cea0 Replace an assert() with an actual diagnostic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145535 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 23:16:25 +00:00
Kostya Serebryany
af65a8c54b make asan work at -O0, llvm part. Patch by glider@google.com 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145530 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 22:19:26 +00:00
Jan Sjödin
dd649e35e5 Support for encoding all FMA4 instructions and tablegen patterns for all 
remaining FMA4 instructions and intrinsics with tests.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 22:09:42 +00:00
Eli Friedman
3dad610aaa Make GlobalMerge honor the preferred alignment on globals without an explicitly specified alignment. 
<rdar://problem/10497732>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145523 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 21:54:15 +00:00
Bill Wendling
aee0f453c5 More cleanups. No content change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145522 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 21:52:43 +00:00
Bill Wendling
f6cc4c2d60 Minor cleanup. No content change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145521 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 21:43:43 +00:00
Bob Wilson
a97f02c40c Remove the install-clang-c makefile target. 
When I did this before it broke a buildbot that was testing that target, but
we've removed that buildbot now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145519 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 21:06:12 +00:00
Bill Wendling
65fa507e0b Remove an XXX which hasn't been fixed yet. It's too late now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145518 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 20:53:52 +00:00
Matt Beaumont-Gay
7b8e121520 Remove unused variable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145517 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 19:53:11 +00:00
Jim Grosbach
e30171ba0c Add some tests for all-lanes VLD1 parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145512 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 19:37:38 +00:00
Jim Grosbach
096334e25e ARM parsing for VLD1 all lanes, with writeback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145510 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 19:35:44 +00:00
Chad Rosier
8ff4115ef0 Add a few functions to TargetLibraryInfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145508 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 19:19:00 +00:00
Jim Grosbach
13af222bab ARM parsing for VLD1 two register all lanes, no writeback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145504 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 18:21:25 +00:00
Nadav Rotem
78647434ea Add test arch to make it pass on non x86 targets 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145498 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 17:34:28 +00:00
Benjamin Kramer
5f794df76e X86: Turns out bulldozer also supports sse42 and lzcnt. 
While at it remove the barcelona/instanbul/shanghai subtargets, they're
unsupported by GCC and look pretty broken.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145494 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 15:48:16 +00:00
Benjamin Kramer
2a6cf70650 X86: Add subtargets for AMD's bulldozer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145493 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 15:27:46 +00:00
Nadav Rotem
f3993125b1 Add a tripple to the test 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145489 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 11:20:56 +00:00
Nadav Rotem
18197d7425 X86: PerformOrCombine introduced a vselect node with a wrong order of operands. This bug was introduced when a dedicated blend sdnode was replaced with the vselect node (in 139479). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145488 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 10:13:37 +00:00
Craig Topper
b72039cf52 Add instruction selection support for AVX2 horizontal add/sub instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145487 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 09:10:50 +00:00
Duncan Sands
0fcb4318ea Mention that -O4 does result in more optimization when used with 
-fplugin-arg-dragonegg-enable-gcc-optzns, though it usually isn't
a win.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145486 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 08:46:05 +00:00
Craig Topper
ec24e61ab0 Merge VPERM2F128/VPERM2I128 ISD node types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145485 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 07:47:51 +00:00
Andrew Trick
68d1efc616 Better test case found in duplicate PR10570. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145484 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 06:26:42 +00:00
Craig Topper
316cd2a2c5 Merge decoding of VPERMILPD and VPERMILPS shuffle masks. Merge X86ISD node type for VPERMILPD/PS. Add instruction selection support for VINSERTI128/VEXTRACTI128. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145483 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 06:25:25 +00:00
Andrew Trick
553fe05f23 LSR: handle the expansion of phi operands that use postinc forms of the IV. 
Fixes PR11431: SCEVExpander::expandAddRecExprLiterally(const llvm::SCEVAddRecExpr*): Assertion `(!isa<Instruction>(Result) || SE.DT->dominates(cast<Instruction>(Result), Builder.GetInsertPoint())) && "postinc expansion does not dominate use"' failed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145482 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 06:07:54 +00:00
Chad Rosier
caebb1e00b Whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145470 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 01:59:59 +00:00
Chad Rosier
683e47b1dd Alphabetize TargetLibraryInfo enum and fix doxygen comments. No functional 
change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145468 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 01:51:49 +00:00
Jim Grosbach
d4578a4f8d llvm_unreachable() is not for user diagnostics.... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145465 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 01:15:55 +00:00
Jim Grosbach
98b05a57b6 ARM parsing aliases for VLD1 single register all lanes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145464 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-30 01:09:44 +00:00
Chad Rosier
3d925d24e8 Add support for sqrt, sqrtl, and sqrtf in TargetLibraryInfo. Disable 
(fptrunc (sqrt (fpext x))) -> (sqrtf x) transformation if -fno-builtin is 
specified.
rdar://10466410

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145460 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 23:57:10 +00:00
Jim Grosbach
6029b6ddaf Tidy up a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145458 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 23:51:09 +00:00
Jim Grosbach
bd1cff5b2c Add comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145456 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 23:33:40 +00:00
Jim Grosbach
1ec7bf0c0d ARM parsing aliases for data-size suffices on VST1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145454 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 23:21:31 +00:00
Jakob Stoklund Olesen
7c6b2c9a70 FileCheckize. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145452 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 23:09:16 +00:00
Akira Hatanaka
ed2a7d2780 Change names for MIPS "generic" processors defined in Mips.td to match what GNU 
tools use. Patch by Simon Atanasyan.

"mips32r1" => "mips32"
"4ke" => mips32r2"
"mips64r1" => "mips64"



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145451 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 23:08:41 +00:00
Jim Grosbach
4c7edb3ad8 ARM assembly parsing and encoding for four-register VST1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145450 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 22:58:48 +00:00
Daniel Dunbar
2662c83a59 llvm-config: Replace with C++ version (was llvm-config-2). 
- Reapply of r144300, with lots of fixes/migration easement in between.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145449 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 22:56:31 +00:00
Evan Cheng
a3438cf48b Add another missing pattern. llvm-gcc likes f64 but clang likes i64 so it was generating poor code for some SSE builtins. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145448 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 22:48:34 +00:00
Jim Grosbach
ed1f83f9af Enable some VST1 tests and add a few more. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145443 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 22:40:32 +00:00
Jim Grosbach
d5ca201891 ARM assembly parsing and encoding for three-register VST1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145442 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 22:38:04 +00:00
Jakob Stoklund Olesen
0edd83bfff Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions. 
Like V_SET0, these instructions are expanded by ExpandPostRA to xorps /
vxorps so they can participate in execution domain swizzling.

This also makes the AVX variants redundant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145440 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 22:27:25 +00:00
Stepan Dyatkovskiy
be4c844648 Potential bug in RewriteLoopBodyWithConditionConstant: use iterator should not be changed inside the uses enumeration loop. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145432 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 20:34:39 +00:00
Eric Christopher
fe2cb3e37f Update the docs for some of the test-suite configure changes and 
be more clear about what to do and how to do it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145426 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 19:40:56 +00:00
Chad Rosier
ae6f2cb1fc If fast-isel fails, remove dead instructions generated during the failed 
attempt.  

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145425 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 19:40:47 +00:00