Commit Graph

478 Commits

Author SHA1 Message Date
Bob Wilson
0bf7d998b4 Add codegen support for NEON vld3lane intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83585 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 22:27:33 +00:00
Anton Korobeynikov
632606c724 Use lower16 / upper16 imm modifiers to asmprint 32-bit imms splitted via movt/movw pair.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83572 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 20:43:22 +00:00
Bob Wilson
30aea9d96e Add codegen support for NEON vld2lane intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83568 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 18:56:10 +00:00
Bob Wilson
67a6103a34 Convert more NEON tests to use FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83528 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 06:02:10 +00:00
Bob Wilson
deb3141cf5 Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83526 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 05:18:18 +00:00
Bob Wilson
5adf60c03b Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83518 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 00:28:28 +00:00
Bob Wilson
24e04c535f Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83513 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08 00:21:01 +00:00
Bob Wilson
0ea38bb939 Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83508 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 23:54:04 +00:00
Bob Wilson
fe27c512e8 Convert more NEON tests to use FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83507 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 23:47:21 +00:00
Bob Wilson
c67160c010 Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83506 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 23:39:57 +00:00
Bob Wilson
a4288080e6 Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83502 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 22:57:01 +00:00
Bob Wilson
b2cae81ac4 Convert more NEON tests to use FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83497 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 22:30:19 +00:00
Bob Wilson
99c372e723 Convert test to FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83487 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 20:51:42 +00:00
Bob Wilson
63c9063434 Add codegen support for NEON vst4 intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83486 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 20:49:18 +00:00
Bob Wilson
66a70639da Add codegen support for NEON vst3 intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83484 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 20:30:08 +00:00
Bob Wilson
d285575f87 Add codegen support for NEON vst2 intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83482 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 18:47:39 +00:00
Bob Wilson
7708c22baa Add codegen support for NEON vld4 intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83479 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 18:09:32 +00:00
Bob Wilson
ff8952e8a9 Add codegen support for NEON vld3 intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83471 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 17:24:55 +00:00
Bob Wilson
967f87578d Add tests for vld2 of 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83468 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 17:19:13 +00:00
Bob Wilson
ec1d81c389 Update NEON struct names to match llvm-gcc changes.
(This is not required for correctness but might help with sanity.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83415 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-06 21:16:19 +00:00
Evan Cheng
3825ce8c24 Fix tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83241 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-02 06:53:57 +00:00
Evan Cheng
62a1b5db44 Move load / store multiple before post-alloc scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83236 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-02 04:57:15 +00:00
David Goodwin
9843a93e83 Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83218 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01 22:19:57 +00:00
David Goodwin
471850ab84 Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83215 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01 21:46:35 +00:00
David Goodwin
0dad89fa94 Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83122 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30 00:10:16 +00:00
David Goodwin
8971c4a30e Post-RA regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83075 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-29 17:10:26 +00:00
Evan Cheng
fa1be5d991 Fix PR4687. Pre ARMv5te does not support ldrd / strd. Patch by John Tytgat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83058 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-29 07:07:30 +00:00
Evan Cheng
0e6b590b91 Coalescer should not delete extract_subreg, insert_subreg, and subreg_to_reg of
physical registers. This is especially critical for the later two since they
start the live interval of a super-register. e.g.
%DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
If this instruction is eliminated, the register scavenger will not be happy as
D0 is not defined previously.
This fixes PR5055.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82968 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-28 05:28:43 +00:00
Anton Korobeynikov
6a2fa325c1 Use movt/movw pair to materialize 32 bit constants on ARMv6T2+.
This should be better than single load from constpool.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82948 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-27 23:52:58 +00:00
Evan Cheng
2fcf85efe7 Remove this test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82869 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-26 18:51:37 +00:00
Daniel Dunbar
c8e9314a41 "Update" tests for -disable-if-conversion removal. I think branch.ll should just
be removed, but I XFAIL'd it for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82847 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-26 05:29:36 +00:00
Evan Cheng
9fde6ca2c7 Convert test to filecheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82835 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-26 02:41:17 +00:00
Evan Cheng
483011018e Flip -disable-post-RA-scheduler to -post-RA-scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82803 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25 21:38:11 +00:00
Dan Gohman
c76909abfe Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
   This eliminates MachineInstr's std::list member and allows the data to be
   created by isel and live for the remainder of codegen, avoiding a lot of
   copying and unnecessary translation. This also shrinks MemSDNode.
 - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
   fields for MachineMemOperands.
 - Change MemSDNode to have a MachineMemOperand member instead of its own
   fields with the same information. This introduces some redundancy, but
   it's more consistent with what MachineInstr will eventually want.
 - Ignore alignment when searching for redundant loads for CSE, but remember
   the greatest alignment.

Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25 20:36:54 +00:00
Bob Wilson
0035f9c3b9 pr4926: ARM requires the stack pointer to be aligned, even for leaf functions.
For the AAPCS ABI, SP must always be 4-byte aligned, and at any "public
interface" it must be 8-byte aligned.  For the older ARM APCS ABI, the stack
alignment is just always 4 bytes.  For X86, we currently align SP at
entry to a function (e.g., to 16 bytes for Darwin), but no stack alignment
is needed at other times, such as for a leaf function.

After discussing this with Dan, I decided to go with the approach of adding
a new "TransientStackAlignment" field to TargetFrameInfo.  This value
specifies the stack alignment that must be maintained even in between calls.
It defaults to 1 except for ARM, where it is 4.  (Some other targets may
also want to set this if they have similar stack requirements. It's not
currently required for PPC because it sets targetHandlesStackFrameRounding
and handles the alignment in target-specific code.) The existing StackAlignment
value specifies the alignment upon entry to a function, which is how we've
been using it anyway.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82767 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25 14:41:49 +00:00
Bob Wilson
08ae76c042 Convert to FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82710 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-24 20:23:02 +00:00
Evan Cheng
393e277ecd Fix PR5024 with a big hammer: disable the double-def assertion in the scavenger.
LiveVariables add implicit kills to correctly track partial register kills. This works well enough and is fairly accurate. But coalescer can make it impossible to maintain these markers. e.g.

        BL <ga:sss1>, %R0<kill,undef>, %S0<kill>, %R0<imp-def>, %R1<imp-def,dead>, %R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>, %LR<imp-def,dead>, %D0<imp-def>, ...
...
	%reg1031<def> = FLDS <cp#1>, 0, 14, %reg0, Mem:LD4[ConstantPool]
...
   	%S0<def> = FCPYS %reg1031<kill>, 14, %reg0, %D0<imp-use,kill>

When reg1031 and S0 are coalesced, the copy (FCPYS) will be eliminated the the implicit-kill of D0 is lost. In this case it's possible to move the marker to the FLDS. But in many cases, this is not possible. Suppose

	%reg1031<def> = FOO <cp#1>, %D0<imp-def>
...
   	%S0<def> = FCPYS %reg1031<kill>, 14, %reg0, %D0<imp-use,kill>

When FCPYS goes away, the definition of S0 is the "FOO" instruction. However, transferring the D0 implicit-kill to FOO doesn't work since it is the def of D0 itself. We need to fix this in another time by introducing a "kill" pseudo instruction to track liveness.

Disabling the assertion is not ideal, but machine verifier is doing that job now. It's important to know double-def is not a miscomputation since it means a register should be free but it's not tracked as free. It's a performance issue instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82677 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-24 02:27:09 +00:00
Evan Cheng
296925dc16 Fix PR5024. LiveVariables physical register defs should *commit* only after all
of the defs are processed.
Also fix a implicit_def propagation bug: a implicit_def of a physical register
should be applied to uses of the sub-registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82616 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-23 06:28:31 +00:00
Evan Cheng
60c7df2c93 Fix PR5024. LiveVariables::FindLastPartialDef should return a set of sub-registers that were defined by the last partial def, not just a single sub-register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82535 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-22 08:34:46 +00:00
Evan Cheng
014d624a28 Fix a pasto. Also simplify for Bill's benefit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82505 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-22 01:48:19 +00:00
Evan Cheng
cf985a9545 Clean up spill weight computation. Also some changes to give loop induction
variable increment / decrement slighter high priority. 

This has major impact on some micro-benchmarks. On MultiSource/Applications
and spec tests, it's a minor win. It also reduce 256.bzip instruction count
by 8%, 55 on 164.gzip on i386 / Darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82485 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-21 21:12:25 +00:00
Evan Cheng
b0f5973bee Fix PR4986. "r1024 = insert_subreg r1024, undef, 2" cannot be turned in an implicit_def. Instead, it's an identity copy so it should be eliminated. Also make sure to update livevariable kill information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82436 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-21 04:32:32 +00:00
Bob Wilson
9b379dc526 Convert more tests to FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81915 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-15 20:58:02 +00:00
Sandeep Patel
85111a9c07 Fix superreg use in ARMAsmPrinter. Approved by Anton Korobeynikov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81878 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-15 17:53:11 +00:00
Anton Korobeynikov
20c35ec427 Define proper subreg sets for arm - this should fix bunch of subtle problems
with subreg - superreg mapping and also fix PR4965.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81657 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-13 00:59:43 +00:00
Dan Gohman
55a7877cac Remove an unnecessary -f.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81546 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-11 18:41:06 +00:00
Dan Gohman
b7c0b246da Convert more tests to avoid llvm-as.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81545 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-11 18:36:27 +00:00
Bob Wilson
92ad363f58 Don't swap the operands of a subtraction when trying to create a
post-decrement load/store.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81464 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-10 22:09:31 +00:00
Bob Wilson
cd3b9a4f17 Fix pr4939: Change FPCCToARMCC to translate SETOLE to ARMCC::LS.
See the bug report for details.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81397 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-09 23:14:54 +00:00
Dan Gohman
fce288fc91 Eliminate more uses of llvm-as and llvm-dis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-09 00:09:15 +00:00