These checks would often trigger on unreachable statements inserted by
bugpoint, leading it astray.
It would be nice if we could distinguish unreachable blocks from errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91923 91177308-0d34-0410-b5e6-96231b3b80d8
return partial registers. This affected the back-end lowering code some.
Also patch up some places I missed before in the "get" functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91880 91177308-0d34-0410-b5e6-96231b3b80d8
This fixes an in-place update bug where code inserted at the end of basic blocks may not be covered by existing intervals which were live across the entire block. It is also consistent with the way ranges are specified for live intervals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91859 91177308-0d34-0410-b5e6-96231b3b80d8
by allowing backends to override routines that will default
the JIT and Static code generation to an appropriate code model
for the architecture.
Should fix PR 5773.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91824 91177308-0d34-0410-b5e6-96231b3b80d8
- Move DisableScheduling flag into TargetOption.h
- Move SDNodeOrdering into its own header file. Give it a minimal interface that
doesn't conflate construction with storage.
- Move assigning the ordering into the SelectionDAGBuilder.
This isn't used yet, so there should be no functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91727 91177308-0d34-0410-b5e6-96231b3b80d8
contains another loop, or an instruction. The loop form is
substantially more efficient on large loops than the typical
code it replaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91654 91177308-0d34-0410-b5e6-96231b3b80d8
The change in SelectionDAGBuilder is needed to allow using bitcasts to convert
between f64 (the default type for ARM "d" registers) and 64-bit Neon vector
types. Radar 7457110.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91649 91177308-0d34-0410-b5e6-96231b3b80d8
non-landing pad basic block as the successor to a block that ends in an
unconditional jump will cause block folding to remove the added block as a
successor. Thus eventually removing it AND the landing pad entirely. Critical
edge splitting is an optimization, so we can safely turn it off when dealing
with landing pads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91634 91177308-0d34-0410-b5e6-96231b3b80d8
LegalizeDAG.cpp. Unlike the code it replaces, which simply decrements the simple
type by one, getHalfSizedIntegerVT() searches for the smallest simple integer
type that is at least half the size of the type it is called on. This approach
has the advantage that it will continue working if a new value type (such as
i24) is added to MVT.
Also, in preparation for new value types, remove the assertions that
non-power-of-2 8-bit-mutiple types are Extended when legalizing extload and
truncstore operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91614 91177308-0d34-0410-b5e6-96231b3b80d8
Fold (zext (and x, cst)) -> (and (zext x), cst)
DAG combiner likes to optimize expression in the other way so this would end up cause an infinite looping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91574 91177308-0d34-0410-b5e6-96231b3b80d8
Tail duplication produces lots of identical phi nodes in different basic
blocks. Teach PHIElimination to reuse the join registers when lowering a phi
node that is identical to an already lowered node. This saves virtual
registers, and more importantly it avoids creating copies the the coalescer
doesn't know how to eliminate.
Teach LiveIntervalAnalysis about the phi joins with multiple uses.
This patch significantly reduces code size produced by -pre-regalloc-taildup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91549 91177308-0d34-0410-b5e6-96231b3b80d8
