Anton Korobeynikov
0cb2a45cce
Emit the ctors in the proper order on ARM/EABI.
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Maybe some targets should use this as well.
Patch by Evgeniy Stepanov!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145781 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-03 23:49:37 +00:00
Venkatraman Govindaraju
80b1ae9292
Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() since
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AnalyzeBranch doesn't change the successor, just the order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145779 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-03 21:24:48 +00:00
Sanjoy Das
199ce33b3b
Check for stack space more intelligently.
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libgcc sets the stack limit field in TCB to 256 bytes above the actual
allocated stack limit. This means if the function's stack frame needs
less than 256 bytes, we can just compare the stack pointer with the
stack limit. This should result in lesser calls to __morestack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145766 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-03 09:32:07 +00:00
Sanjoy Das
40f8222e1e
Fix a bug in the x86-32 code generated for segmented stacks.
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Currently LLVM pads the call to __morestack with a add and sub of 8
bytes to esp. This isn't correct since __morestack expects the call
to be followed directly by a ret.
This commit also adjusts the relevant test-case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145765 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-03 09:21:07 +00:00
Nick Lewycky
3604924799
Creating multiple JITs on X86 in multiple threads causes multiple writes (of
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the same value) to this variable. This code could be refactored, but it doesn't
matter since the old JIT is going away. Add tsan annotations to ignore the
race.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145745 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-03 02:45:50 +00:00
Chad Rosier
9eff1e33f6
[arm-fast-isel] Unaligned stores of floats require special care.
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rdar://10510150
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145742 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-03 02:21:57 +00:00
Jim Grosbach
587f5062b9
ARM NEON VEXT aliases for data type suffices.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145726 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 23:34:39 +00:00
Jim Grosbach
e40ab244c1
ARM VEXT tighten up operand classes a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145722 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 22:57:57 +00:00
Jim Grosbach
84defb51ca
ARM VST1 single lane assembly parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145718 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 22:34:51 +00:00
Nick Lewycky
8a8d479214
Move global variables in TargetMachine into new TargetOptions class. As an API
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change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.
One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145714 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 22:16:29 +00:00
Jim Grosbach
872eedbb3a
ARM VLD1 single lane assembly parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145712 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 22:01:52 +00:00
Jim Grosbach
204aa64f30
ARM encoder method needs the physical register number, not the enum.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145711 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 22:01:25 +00:00
Chad Rosier
b74c865841
[arm-fast-isel] After promoting a function parameter be sure to update the
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argument value type. Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145701 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 20:25:18 +00:00
Jim Grosbach
dad2f8e7fb
Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
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Add the 16-bit lane variants while I'm at it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145693 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 18:52:30 +00:00
Jan Sjödin
ce25d26b40
Add XOP feature flag.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145682 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 15:14:37 +00:00
Craig Topper
f8363305eb
Reduce duplicate code in isHorizontalBinOp and add some asserts to protect assumptions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145681 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 08:18:41 +00:00
Craig Topper
138a5c66b9
Add instruction selection support for horizontal add/sub of 256-bit floating point vectors. Also add the test case for 256-bit integer vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145680 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 07:16:01 +00:00
Hal Finkel
826941a0af
remove unneeded FIXME comment
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145679 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 04:58:17 +00:00
Hal Finkel
64c34e2535
update PPC 940 hazard rec. to function in postRA mode
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145676 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 04:58:02 +00:00
Jim Grosbach
7636bf6530
ARM start parsing VLD1 single lane instructions.
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The alias pseudos need cleaned up for size suffix handling, but this gets
the basics working. Will be cleaning up and adding more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145655 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 00:35:16 +00:00
Sanjoy Das
fc9261279a
Dummy commit to check commit access.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145619 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-01 19:15:08 +00:00
Chad Rosier
fbd828d8e1
Add missing functions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145608 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-01 18:26:19 +00:00
Chad Rosier
32b6c59ad0
Add a few more functions to TargetLibraryInfo. More of rdar://10500969.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145596 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-01 17:54:37 +00:00
Eric Christopher
7d5a61e975
For 64-bit the rest of the general regs are ok for the q constraint. Make
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sure we can emit both the high and low versions of those registers.
Fixes rdar://10392864
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145579 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-01 08:12:41 +00:00
Eli Friedman
522fb8cc01
Pass AVX vectors which are arguments to varargs functions on the stack. <rdar://problem/10463281>.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145573 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-01 04:49:21 +00:00
Eli Friedman
32e698cc10
Small fix for assembler generation on Darwin PPC64. Patch by Michael Kostylev. PR11437.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145553 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-01 01:43:47 +00:00
Jan Sjödin
dd649e35e5
Support for encoding all FMA4 instructions and tablegen patterns for all
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remaining FMA4 instructions and intrinsics with tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 22:09:42 +00:00
Matt Beaumont-Gay
7b8e121520
Remove unused variable
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 19:53:11 +00:00
Jim Grosbach
096334e25e
ARM parsing for VLD1 all lanes, with writeback.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145510 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 19:35:44 +00:00
Chad Rosier
8ff4115ef0
Add a few functions to TargetLibraryInfo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145508 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 19:19:00 +00:00
Jim Grosbach
13af222bab
ARM parsing for VLD1 two register all lanes, no writeback.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145504 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 18:21:25 +00:00
Benjamin Kramer
5f794df76e
X86: Turns out bulldozer also supports sse42 and lzcnt.
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While at it remove the barcelona/instanbul/shanghai subtargets, they're
unsupported by GCC and look pretty broken.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145494 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 15:48:16 +00:00
Benjamin Kramer
2a6cf70650
X86: Add subtargets for AMD's bulldozer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145493 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 15:27:46 +00:00
Nadav Rotem
18197d7425
X86: PerformOrCombine introduced a vselect node with a wrong order of operands. This bug was introduced when a dedicated blend sdnode was replaced with the vselect node (in 139479).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 10:13:37 +00:00
Craig Topper
b72039cf52
Add instruction selection support for AVX2 horizontal add/sub instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145487 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 09:10:50 +00:00
Craig Topper
ec24e61ab0
Merge VPERM2F128/VPERM2I128 ISD node types.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 07:47:51 +00:00
Craig Topper
316cd2a2c5
Merge decoding of VPERMILPD and VPERMILPS shuffle masks. Merge X86ISD node type for VPERMILPD/PS. Add instruction selection support for VINSERTI128/VEXTRACTI128.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145483 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 06:25:25 +00:00
Chad Rosier
683e47b1dd
Alphabetize TargetLibraryInfo enum and fix doxygen comments. No functional
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change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145468 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 01:51:49 +00:00
Jim Grosbach
98b05a57b6
ARM parsing aliases for VLD1 single register all lanes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145464 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 01:09:44 +00:00
Chad Rosier
3d925d24e8
Add support for sqrt, sqrtl, and sqrtf in TargetLibraryInfo. Disable
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(fptrunc (sqrt (fpext x))) -> (sqrtf x) transformation if -fno-builtin is
specified.
rdar://10466410
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145460 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 23:57:10 +00:00
Jim Grosbach
6029b6ddaf
Tidy up a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145458 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 23:51:09 +00:00
Jim Grosbach
bd1cff5b2c
Add comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145456 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 23:33:40 +00:00
Jim Grosbach
1ec7bf0c0d
ARM parsing aliases for data-size suffices on VST1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145454 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 23:21:31 +00:00
Akira Hatanaka
ed2a7d2780
Change names for MIPS "generic" processors defined in Mips.td to match what GNU
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tools use. Patch by Simon Atanasyan.
"mips32r1" => "mips32"
"4ke" => mips32r2"
"mips64r1" => "mips64"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145451 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 23:08:41 +00:00
Jim Grosbach
4c7edb3ad8
ARM assembly parsing and encoding for four-register VST1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145450 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 22:58:48 +00:00
Evan Cheng
a3438cf48b
Add another missing pattern. llvm-gcc likes f64 but clang likes i64 so it was generating poor code for some SSE builtins.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145448 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 22:48:34 +00:00
Jim Grosbach
d5ca201891
ARM assembly parsing and encoding for three-register VST1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145442 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 22:38:04 +00:00
Jakob Stoklund Olesen
0edd83bfff
Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions.
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Like V_SET0, these instructions are expanded by ExpandPostRA to xorps /
vxorps so they can participate in execution domain swizzling.
This also makes the AVX variants redundant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145440 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 22:27:25 +00:00
Andrew Trick
7d8867d453
comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145422 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 19:33:49 +00:00
Daniel Dunbar
d782bae970
build/CMake: Finish removal of add_llvm_library_dependencies.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145420 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 19:25:30 +00:00