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1427 Commits

Author SHA1 Message Date
Owen Anderson
14090bf263 Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions. 
Fixes a large class of disassembler crashes found by randomized testing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137995 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 22:11:02 +00:00
Jim Grosbach
93b3eff623 Thumb assembly parsing and encoding for LDM instruction. 
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137986 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 21:50:53 +00:00
Owen Anderson
847a7ad800 More Thumb1 decoding tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137974 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 20:05:06 +00:00
Jim Grosbach
1eba8a66b6 Thumb assembly parsing and encoding for EOR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137964 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 18:10:38 +00:00
Jim Grosbach
0d1511c022 Thumb assembly parsing and encoding for CMP. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137963 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 18:08:29 +00:00
James Molloy
dbe46744c5 Test commit; adding test for invalid LDRD which was part of the patch for r137647 but seemingly didn't get svn add'ed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137960 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 18:03:02 +00:00
Jim Grosbach
7750b8df6a Thumb assembly parsing and encoding test for CMN. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137957 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 17:55:03 +00:00
Owen Anderson
7cf6d7a083 Port over BL/BLX to disassembly tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137954 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 17:43:52 +00:00
Jim Grosbach
6ea80e964b ARM assembly parsing and encoding test for BX/BLX (register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137949 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 17:02:28 +00:00
Jim Grosbach
ded439886a ARM assembly parsing and encoding test for BL/BLX (immediate). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137948 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-18 17:00:09 +00:00
Owen Anderson
3230e9537d Port new Thumb1 encoding tests over to decoding tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137902 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 23:37:33 +00:00
Jim Grosbach
37f88c7812 ARM assembly parsing and encoding test for BKPT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137898 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 23:11:13 +00:00
Jim Grosbach
5b657de62b ARM assembly parsing and encoding test for BIC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 23:00:53 +00:00
Jim Grosbach
395b453bed Thumb assembly parsing and encoding for B. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137891 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 22:57:40 +00:00
Jim Grosbach
00f5d98205 Thumb assembly parsing and encoding for ASR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137889 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 22:49:09 +00:00
Jim Grosbach
5a1cd045cd Thumb assembly parsing and encoding for ADR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137864 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 20:37:40 +00:00
Jim Grosbach
53727fc659 Add a couple of FIXMEs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137861 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 20:35:57 +00:00
Owen Anderson
4c81cf5dfc Start building a Thumb1 decoding test file based on the Thumb1 parsing/encoding test file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137840 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 18:21:36 +00:00
Jim Grosbach
358499ea3b Thumb assembly parsing and encoding for ADC(register) instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137833 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 17:55:28 +00:00
Jim Grosbach
b1ee18ee69 Add missing '@' delimiter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137832 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 17:46:01 +00:00
Owen Anderson
83e3f67fb6 Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. 
Patch by James Molloy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137830 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-17 17:44:15 +00:00
Jim Grosbach
89e2aa6afd Thumb ADD(immediate) parsing support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137788 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 23:57:34 +00:00
Jim Grosbach
194bd89829 Thumb parsing diagnostics for low-reg requirements on ADD and MOV. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137779 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 22:20:01 +00:00
Jim Grosbach
3912b73c74 Thumb assembly parsing and encoding for ADD(register) instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137759 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 21:34:08 +00:00
Jim Grosbach
c2408d3ce5 Add testcase for r137746. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137754 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 21:11:21 +00:00
Jim Grosbach
be2ac8ca7b Tidy up formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137747 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 20:55:41 +00:00
Jim Grosbach
47a0d52b69 ARM thumb assembly parsing for arithmetic flag setting instructions. 
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137746 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 20:45:50 +00:00
Jim Grosbach
d0d3f7e01f ARM .align NOP padding uses different encoding pre-ARMv6. 
Patch by Kristof Beyls and James Malloy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137723 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-16 17:06:20 +00:00
Owen Anderson
a9c989d55a Add a test file for Thumb2 NEON. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137687 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 23:42:20 +00:00
Bruno Cardoso Lopes
1deddbbd56 Reorder declarations of vmovmskp* and also put the necessary AVX 
predicate and TB encoding fields. This fix the encoding for the
attached testcase. This fixes PR10625.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137684 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 23:36:45 +00:00
Owen Anderson
c4bda5633a Add some more comprehensive VFP decoding tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137657 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 21:29:01 +00:00
Owen Anderson
c537f3be0c Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact. 
Patch by James Molloy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137647 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 20:51:32 +00:00
Owen Anderson
95d01b8898 Add a test for Thumb1 LDRSH decoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137645 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 20:15:43 +00:00
Owen Anderson
bd37b721c8 Add testcase for STRH. Patch by James Molloy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137644 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 20:12:03 +00:00
Owen Anderson
5df7ef6cdb Fix incorrect encoding of UMAAL and friends. Patch by James Molloy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137641 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 20:08:25 +00:00
Owen Anderson
305e046e53 Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137636 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 19:00:06 +00:00
Owen Anderson
7a2e1770ea Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137635 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-15 18:44:44 +00:00
Owen Anderson
0d09499cf3 Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137502 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 20:36:11 +00:00
Owen Anderson
a211c2c7e9 Port over the basic ARM encodings test file to a decoding test file. Greatly increases our test coverage of basic ARM-mode instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137495 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 19:42:45 +00:00
Jim Grosbach
7a8729effc Tidy up formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137471 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 17:43:31 +00:00
Jim Grosbach
46c38aff89 Tidy up formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137464 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 17:01:02 +00:00
Benjamin Kramer
0d46ccfc5c MachOWriter: Don't crash on fixups with arithmetic, emit a relocation instead. This matches what as does. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137414 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-12 01:51:29 +00:00
Jim Grosbach
29e7b7deb4 Clean up formatting a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137393 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 23:57:17 +00:00
Jim Grosbach
857e1a7b3f ARM vector compare to zero instruction assembly parsing support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137389 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 23:51:13 +00:00
Jim Grosbach
c69c26d95e Fix tests per now-correct encoding as of r137371. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137376 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 22:31:48 +00:00
Jim Grosbach
342ebd5f38 ARM STRT assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137372 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 22:18:00 +00:00
Jim Grosbach
dd32ba337a ARM load shifted register pre-index fix shift value asm parser encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137367 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 22:05:09 +00:00
Jim Grosbach
2ef8241ce7 ARM STRHT assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137358 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:39:41 +00:00
Jim Grosbach
7b8f46cf9e ARM STRH assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137353 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:17:22 +00:00
Owen Anderson
508e1d3db5 Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137347 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:47:56 +00:00
Owen Anderson
9fe72bcd37 Improve operand validation for Thumb2 addressing modes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137344 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:40:40 +00:00
Jim Grosbach
14605d1a67 ARM STRD assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137342 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:28:23 +00:00
Owen Anderson
26d2f0ac91 Continue to tighten decoding by performing more operand validation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137340 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:21:46 +00:00
Jim Grosbach
10348e70d5 ARM STRBT assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137337 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:04:56 +00:00
Jim Grosbach
961afdf1b6 Add FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137336 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 19:43:42 +00:00
Jim Grosbach
534de6cad8 ARM STRB assembly parsing and encoding tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137335 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 19:42:58 +00:00
Jim Grosbach
c15bd92d2f Fix a copy/paste error so that LDRB(register) actually gets tested. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137333 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 19:34:23 +00:00
Jim Grosbach
f91c14920c ARM STR(register) assembly parsing and encoding tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137332 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 19:26:17 +00:00
Jim Grosbach
548340c4bf ARM STR(immediate) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137331 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 19:22:40 +00:00
Owen Anderson
71156a6e00 Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137325 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 19:00:18 +00:00
Owen Anderson
2b7b238e84 Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137323 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 18:55:42 +00:00
Owen Anderson
3dac0bec7e Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137322 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 18:41:59 +00:00
Owen Anderson
ae0bc5deaa Improve error checking in the new ARM disassembler. Patch by James Molloy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137320 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 18:24:51 +00:00
Jim Grosbach
f6713916fb ARM push of a single register encodes as pre-indexed STR. 
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137318 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 18:07:11 +00:00
Jim Grosbach
f8fce711e8 ARM pop of a single register encodes as post-indexed LDR. 
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137316 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 17:35:48 +00:00
Jim Grosbach
64104f48f2 ARM tests for LDRSHT assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137274 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 23:18:30 +00:00
Jim Grosbach
e0109c07ff ARM tests for LDRSH assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137272 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 23:12:25 +00:00
Jim Grosbach
7d179b59cd ARM tests for LDRSBT assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137271 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 23:08:56 +00:00
Jim Grosbach
5e92159400 ARM tests for LDRSB assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137270 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 23:06:44 +00:00
Jim Grosbach
263bb07135 Add FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137265 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 22:56:43 +00:00
Jim Grosbach
de2f526c7c ARM tests for LDRHT assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137263 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 22:55:38 +00:00
Jim Grosbach
46b355479f ARM tests for LDRH(register) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137261 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 22:45:42 +00:00
Jim Grosbach
623a454b0f ARM LDRH(immediate) assembly parsing and encoding support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137260 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 22:42:16 +00:00
Jim Grosbach
c7de52fcff Add FIXME 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137258 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 22:20:38 +00:00
Jim Grosbach
251bf25e7e ARM LDRD(register) assembly parsing and encoding. 
Add support for literal encoding of #-0 along the way.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137254 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 21:56:18 +00:00
Jim Grosbach
2fd2b87ded ARM LDRD(immediate) assembly parsing and encoding support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137244 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 20:29:19 +00:00
Owen Anderson
8533ebad6f Add initial support for decoding NEON instructions in Thumb2 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137236 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 19:01:10 +00:00
Owen Anderson
33e57515b1 Push GPRnopc through a large number of instruction definitions to tighten operand decoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 00:03:03 +00:00
Owen Anderson
de317f40f7 Tighten operand checking of register-shifted-register operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137180 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 23:33:27 +00:00
Owen Anderson
c36481c474 Tighten operand checking on memory barrier instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137176 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 23:25:42 +00:00
Owen Anderson
35008c2f8d Tighten operand checking on CPS instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137172 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 23:05:39 +00:00
Owen Anderson
51c9805c4b Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137168 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:48:45 +00:00
Benjamin Kramer
793b811c50 ARM Disassembler: sign extend branch immediates. 
Not sure about BLXi, but this is what the old disassembler did.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137156 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:02:50 +00:00
Owen Anderson
bd9091c18d Tighten Thumb1 branch predicate decoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137146 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 21:07:45 +00:00
Owen Anderson
8d7d2e1238 Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137144 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 20:55:18 +00:00
Jim Grosbach
3148a65490 ARM parsing and encoding for LDRBT instruction. 
Fix the instruction representation to correctly only allow post-indexed form.
Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137074 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 23:28:47 +00:00
Jim Grosbach
bc6fc20fcc ARM parsing and encoding for LDRB instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137071 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 22:37:06 +00:00
Jim Grosbach
8668a5b0c8 Add FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137070 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-08 22:11:33 +00:00
Jim Grosbach
0d6fac36ed ARM load instruction shifted register index operands. 
Parsing and encoding for shifted index operands for load instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136986 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-05 22:03:36 +00:00
Jim Grosbach
f4fa3d6e46 ARM indexed load assembly parsing and encoding. 
More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136982 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-05 21:28:30 +00:00
Jim Grosbach
6fc1c08635 Add ARM LDR parsing tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136977 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-05 20:33:39 +00:00
Rafael Espindola
5c4e52e496 Fix the bitwidth of the remaining fields. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136884 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 17:00:11 +00:00
Rafael Espindola
251a2bbfb0 print st_shndx with the correct number of bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136880 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 15:50:13 +00:00
Rafael Espindola
67ac0c0d63 print st_other with the correct number of bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136877 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 15:38:19 +00:00
Rafael Espindola
71a8f5ca12 print st_type with the correct number of bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136875 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 15:24:00 +00:00
Rafael Espindola
d7c278326f Print st_bind with the correct number of bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136874 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 15:10:35 +00:00
Rafael Espindola
a83f8ef9b4 Print r_sym with the correct number of bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136873 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 14:48:27 +00:00
Rafael Espindola
f81f6758f3 Print r_type with the correct number of bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136872 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 14:39:30 +00:00
Rafael Espindola
65ad8dc807 Another counter goes decimal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136871 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 14:27:46 +00:00
Rafael Espindola
f7179de2a5 Change anther counter to decimal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136870 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-04 14:01:03 +00:00