Chris Lattner
7e598096ea
Sink noop copies into the basic block that uses them. This reduces the number
...
of cross-block live ranges, and allows the bb-at-a-time selector to always
coallesce these away, at isel time.
This reduces the load on the coallescer and register allocator. For example
on a codec on X86, we went from:
1643 asm-printer - Number of machine instrs printed
419 liveintervals - Number of loads/stores folded into instructions
1144 liveintervals - Number of identity moves eliminated after coalescing
1022 liveintervals - Number of interval joins performed
282 liveintervals - Number of intervals after coalescing
1304 liveintervals - Number of original intervals
86 regalloc - Number of times we had to backtrack
1.90232 regalloc - Ratio of intervals processed over total intervals
40 spiller - Number of values reused
182 spiller - Number of loads added
121 spiller - Number of stores added
132 spiller - Number of register spills
6 twoaddressinstruction - Number of instructions commuted to coalesce
360 twoaddressinstruction - Number of two-address instructions
to:
1636 asm-printer - Number of machine instrs printed
403 liveintervals - Number of loads/stores folded into instructions
1155 liveintervals - Number of identity moves eliminated after coalescing
1033 liveintervals - Number of interval joins performed
279 liveintervals - Number of intervals after coalescing
1312 liveintervals - Number of original intervals
76 regalloc - Number of times we had to backtrack
1.88998 regalloc - Ratio of intervals processed over total intervals
1 spiller - Number of copies elided
41 spiller - Number of values reused
191 spiller - Number of loads added
114 spiller - Number of stores added
128 spiller - Number of register spills
4 twoaddressinstruction - Number of instructions commuted to coalesce
356 twoaddressinstruction - Number of two-address instructions
On this testcase, this change provides a modest reduction in spill code,
regalloc iterations, and total instructions emitted. It increases the number
of register coallesces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28115 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-05 01:04:50 +00:00
Nate Begeman
f4360a4789
Finish up the initial jump table implementation by allowing jump tables to
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not be 100% dense. Increase the minimum threshold for the number of cases
in a switch statement from 4 to 6 in order to create a jump table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28079 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-03 03:48:02 +00:00
Owen Anderson
a69571c799
Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
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This fixes PR 759.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28074 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-03 01:29:57 +00:00
Evan Cheng
55d0fa1bfa
Remove the temporary option: -no-isel-fold-inflight
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28012 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28 18:54:11 +00:00
Evan Cheng
020c41f21e
TargetLowering::LowerArguments should return a VBIT_CONVERT of
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FORMAL_ARGUMENTS SDOperand in the return result vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28009 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28 05:25:15 +00:00
Evan Cheng
552c4a8494
Added a temporary option -no-isel-fold-inflight to control whether a "inflight"
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node can be folded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28003 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28 02:09:19 +00:00
Evan Cheng
f7179bb56e
Insert a VBIT_CONVERT between a FORMAL_ARGUMENT node and its vector uses
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(VAND, VADD, etc.). Legalizer will assert otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27991 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27 08:29:42 +00:00
Evan Cheng
3b0d286d00
Don't forget return void.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27974 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-25 23:03:35 +00:00
Nate Begeman
9453eea49b
Fix the updating of the machine CFG when a PHI node was in a successor of
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the jump table's range check block. This re-enables 100% dense jump tables
by default on PPC & x86
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27952 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-23 06:26:20 +00:00
Nate Begeman
05f9466cf0
Turn of jump tables for a bit, there are still some issues to work out with
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updating the machine CFG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27949 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-22 23:51:56 +00:00
Nate Begeman
37efe67645
JumpTable support! What this represents is working asm and jit support for
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x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27947 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-22 18:53:45 +00:00
Chris Lattner
4a1cd9c61e
The BFS scheduler is apparently nondeterminstic (causes many llvmgcc bootstrap
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miscompares). Switch RISC targets to use the list-td scheduler, which isn't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27933 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-21 17:16:16 +00:00
Chris Lattner
fdfded5588
Implement support for the formal_arguments node. To get this, targets shouldcustom legalize it and remove their XXXTargetLowering::LowerArguments overload
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27604 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-12 16:20:43 +00:00
Chris Lattner
b22e35a3c3
Add code generator support for VSELECT
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27542 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-08 22:22:57 +00:00
Chris Lattner
3e104b1116
Codegen shufflevector as VVECTOR_SHUFFLE
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27529 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-08 04:15:24 +00:00
Chris Lattner
67f1351498
Stub out shufflevector
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27514 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-08 01:19:25 +00:00
Chris Lattner
2e2ef95350
Make a vector live across blocks have the correct Vec type. This fixes
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CodeGen/X86/2006-04-04-CrossBlockCrash.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27436 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-05 06:54:42 +00:00
Chris Lattner
e58a780166
Intrinsics that just load from memory can be treated like loads: they don't
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have to serialize against each other. This allows us to schedule lvx's
across each other, for example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27346 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-02 03:41:14 +00:00
Chris Lattner
5e46a19ec8
Add a new -view-legalize-dags command line option
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27342 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-02 03:07:27 +00:00
Chris Lattner
f8814cf8b8
Prefer larger register classes over smaller ones when a register occurs in
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multiple register classes. This fixes PowerPC/2006-04-01-FloatDoubleExtend.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27334 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-02 00:24:45 +00:00
Chris Lattner
7e02151ce2
Make sure to pass enough values to phi nodes when we are dealing with
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decimated vectors. This fixes UnitTests/Vector/sumarray-dbl.c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27280 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 02:12:18 +00:00
Chris Lattner
70c2a61e0a
Significantly improve handling of vectors that are live across basic blocks,
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handling cases where the vector elements need promotion, expansion, and when
the vector type itself needs to be decimated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27278 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-31 02:06:56 +00:00
Chris Lattner
2bbd81064a
Bug fixes: handle constantexpr insert/extract element operations
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Handle constantpacked vectors with constantexpr elements.
This fixes CodeGen/Generic/vector-constantexpr.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27241 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-29 00:11:43 +00:00
Jim Laskey
bf7637d590
More bulletproofing of llvm.dbg.declare.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27224 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-28 13:45:20 +00:00
Chris Lattner
48b61a729d
Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value. Split them into separate enums.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27201 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-28 00:40:33 +00:00
Jim Laskey
8c39020359
Reactivate llvm.dbg.declare.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27192 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 23:31:10 +00:00
Chris Lattner
67995340fb
Disable dbg_declare, it currently breaks the CFE build
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27182 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 21:36:03 +00:00
Nate Begeman
f15485a8d0
SelectionDAGISel can now natively handle Switch instructions, in the same
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manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks. The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.
This functionality is currently only enabled on x86, but should be safe for
every target. In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27156 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 01:32:24 +00:00
Jim Laskey
fbcf23c3c1
Bullet proof against undefined args produced by upgrading ols-style debug info.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27155 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 22:46:27 +00:00
Chris Lattner
7255a54561
fix inverted conditional
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27089 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 22:49:42 +00:00
Jim Laskey
0892cee81f
Rename for truth in advertising.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27063 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 09:50:27 +00:00
Chris Lattner
0eade319cd
Lower target intrinsics into an INTRINSIC node
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27035 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 02:22:33 +00:00
Jim Laskey
43970fec32
Handle new forms of llvm.dbg intrinsics.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26988 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-23 18:06:46 +00:00
Chris Lattner
7e358908b8
Fix a typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26965 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 22:20:49 +00:00
Chris Lattner
e25ca692c0
Implement simple support for vector casting. This can currently only handle
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casts between legal vector types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26961 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 20:09:35 +00:00
Chris Lattner
384504cea6
add some trivial support for extractelement.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26928 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-21 20:44:12 +00:00
Chris Lattner
1c6191ffe7
Add a hacky workaround for crashes due to vectors live across blocks.
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Note that this code won't work for vectors that aren't legal on the
target. Improvements coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26925 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-21 19:20:37 +00:00
Chris Lattner
2332b9f16f
implement basic support for INSERT_VECTOR_ELT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26849 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-19 01:17:20 +00:00
Chris Lattner
b2827b0901
Rename ConstantVec -> BUILD_VECTOR and VConstant -> VBUILD_VECTOR. Allow*BUILD_VECTOR to take variable inputs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26847 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-19 00:52:58 +00:00
Chris Lattner
23d564c11f
implement vector.ll:test_undef
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26845 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-19 00:20:20 +00:00
Chris Lattner
c7029805ef
Change the structure of lowering vector stuff. Note: This breaks some
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things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26840 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-18 01:44:44 +00:00
Nate Begeman
81e8097377
Remove BRTWOWAY*
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Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26814 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-17 01:40:33 +00:00
Chris Lattner
6cb7004c34
Fix a problem fully scalarizing values.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26811 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-16 23:05:19 +00:00
Chris Lattner
199862b749
Add support for CopyFromReg from vector values. Note: this doesn't support
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illegal vector types yet!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26799 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-16 19:57:50 +00:00
Chris Lattner
3c38449be6
Teach CreateRegForValue how to handle vector types.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26798 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-16 19:51:18 +00:00
Chris Lattner
28b5b1c7b5
add support for vector->vector casts
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26788 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-15 22:19:46 +00:00
Jim Laskey
f4321a3a43
Handle the removal of the debug chain.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26729 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-13 13:07:37 +00:00
Evan Cheng
0937103368
Added a parameter to control whether Constant::getStringValue() would chop
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off the result string at the first null terminator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26704 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-10 23:52:03 +00:00
Chris Lattner
7d74d1145f
scrape out bits of llvm-db
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26701 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-10 22:48:19 +00:00
Chris Lattner
20a4921791
Simplify the interface to the schedulers, to not pass the selected heuristicin.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26692 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-10 07:49:12 +00:00
Chris Lattner
59bcce5ae5
remove dbg_declare, it's not used yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26659 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-09 20:02:42 +00:00
Jim Laskey
21b6c9d647
Get rid of the multiple copies of getStringValue. Now a Constant:: method.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26616 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-08 18:11:07 +00:00
Chris Lattner
b0d21ef20c
Change the interface for getting a target HazardRecognizer to be more clean.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26608 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-08 04:25:59 +00:00
Chris Lattner
03fc53c174
Hoist the HazardRecognizer out of the ScheduleDAGList.cpp file to where
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targets can implement them. Make the top-down scheduler non-g5-specific.
Remove the old testing hazard recognizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26569 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-06 00:22:00 +00:00
Chris Lattner
a5de484bc7
Split the list scheduler into top-down and bottom-up pieces. The priority
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function of the top-down scheduler are completely bogus currently, and
having (future) PPC specific in this file is also wrong, but this is a
small incremental step.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26552 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-05 21:10:33 +00:00
Chris Lattner
a09f848c11
Codegen copysign[f] into a FCOPYSIGN node
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26542 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-05 05:09:38 +00:00
Evan Cheng
3e1ce5a44d
Add more vector NodeTypes: VSDIV, VUDIV, VAND, VOR, and VXOR.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26504 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-03 07:01:07 +00:00
Chris Lattner
41edaa0529
remove the read/write port/io intrinsics.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26479 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-03 00:19:58 +00:00
Chris Lattner
03dd465215
Split memcpy/memset/memmove intrinsics into i32/i64 versions, resolving
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PR709, and paving the way for future progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26476 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-03 00:00:25 +00:00
Evan Cheng
860771d2d8
Vector ops lowering.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26436 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-01 01:09:54 +00:00
Chris Lattner
22873462c9
Add support for output memory constraints.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26410 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-27 23:45:39 +00:00
Jeff Cohen
7e88103cde
Get VC++ building again.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26351 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-24 02:52:40 +00:00
Chris Lattner
0e43f2ba11
Implement (most of) selection of inline asm memory operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26350 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-24 02:13:54 +00:00
Chris Lattner
87bc3bd121
Lower C_Memory operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26346 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-24 01:11:24 +00:00
Chris Lattner
9f6637db10
Fix an endianness problem on big-endian targets with expanded operands
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to inline asms. Mark some methods const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26334 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-23 20:06:57 +00:00
Chris Lattner
c3a9f8d31c
Record all of the expanded registers in the DAG and machine instr, fixing
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several bugs in inline asm expanded operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26332 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-23 19:21:04 +00:00
Chris Lattner
9b6fb5de49
This fixes a couple of problems with expansion
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26318 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-22 23:09:03 +00:00
Chris Lattner
864635ad7b
Change a whole bunch of code to be built around RegsForValue instead of
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a single register number. This fully implements promotion for inline asms,
expand is close but not quite right yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26316 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-22 22:37:12 +00:00
Chris Lattner
1efa40f6a4
split register class handling from explicit physreg handling.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26308 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-22 00:56:39 +00:00
Chris Lattner
0f0b7d4927
Adjust to changes in getRegForInlineAsmConstraint prototype
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26306 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-21 23:12:12 +00:00
Evan Cheng
cffbb5174f
Dumb bug. Code sees a memcpy from X+c so it increments src offset. But it
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turns out not to point to a constant string but it forgot change the offset
back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26242 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-16 23:11:42 +00:00
Evan Cheng
298ebf2bd8
If the false case is the current basic block, then this is a self loop.
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We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop. Instead, invert the condition and emit
"Loop: ... br!cond Loop; br Out.
Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26231 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-16 08:27:56 +00:00
Evan Cheng
a47876d87a
Remove an unused function parameter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26221 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-15 22:12:35 +00:00
Evan Cheng
74d0aa9a4b
Turn a memcpy from string constant into a series of stores of constant values.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26219 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-15 21:59:04 +00:00
Evan Cheng
c080d6fb3d
Lower memcpy with small constant size operand into a series of load / store
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ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26195 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-15 01:54:51 +00:00
Evan Cheng
dea7245997
Doh again!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26188 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-14 23:05:54 +00:00
Evan Cheng
c4f8eee054
Keep to < 80 cols
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26177 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-14 20:12:38 +00:00
Evan Cheng
ac940ab1bf
Missed a break so memcpy cases fell through to memset. Doh.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26176 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-14 19:45:56 +00:00
Evan Cheng
80e89d7d6c
Fixed a build breakage.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26175 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-14 09:11:59 +00:00
Evan Cheng
a03a5dc7ce
Rename maxStoresPerMemSet to maxStoresPerMemset, etc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26174 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-14 08:38:30 +00:00
Evan Cheng
1db92f947c
Expand memset dst, c, size to a series of stores if size falls below the
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target specific theshold, e.g. 16 for x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26171 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-14 08:22:34 +00:00
Chris Lattner
06a248c9b3
now that libcalls don't suck, we can remove this hack
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26164 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-14 05:39:35 +00:00
Jim Laskey
d96185aa62
Rename to better reflect usage (current and planned.)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26145 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-13 12:50:39 +00:00
Jim Laskey
ce72b1755f
Reorg for integration with gcc4. Old style debug info will not be passed though
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to SelIDAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26115 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-11 01:01:30 +00:00
Evan Cheng
cccf1232a6
Get rid of some memory leaks identified by Valgrind
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25960 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-04 06:49:00 +00:00
Chris Lattner
dc19b70d24
Add initial support for immediates. This allows us to compile this:
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int %rlwnm(int %A, int %B) {
%C = call int asm "rlwnm $0, $1, $2, $3, $4", "=r,r,r,n,n"(int %A, int %B, int 4, int 17)
ret int %C
}
into:
_rlwnm:
or r2, r3, r3
or r3, r4, r4
rlwnm r2, r2, r3, 4, 17 ;; note the immediates :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25955 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-04 02:26:14 +00:00
Chris Lattner
3d81fee851
Initial early support for non-register operands, like immediates
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25952 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-04 02:16:44 +00:00
Chris Lattner
7632e2beb4
remove some #ifdef'd out code, which should properly be in the dag combiner anyway.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25941 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-03 20:13:59 +00:00
Chris Lattner
2223aea6ed
Implement matching constraints. We can now say things like this:
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%C = call int asm "xyz $0, $1, $2, $3", "=r,r,r,0"(int %A, int %B, int 4)
and get:
xyz r2, r3, r4, r2
note that the r2's are pinned together. Yaay for 2-address instructions.
2342 ----------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25893 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-02 00:25:23 +00:00
Chris Lattner
4e4b576e2e
Implement simple register assignment for inline asms. This allows us to compile:
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int %test(int %A, int %B) {
%C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
ret int %C
}
into:
(0x8906130, LLVM BB @0x8902220):
%r2 = OR4 %r3, %r3
%r3 = OR4 %r4, %r4
INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
%r3 = OR4 %r2, %r2
BLR
which asmprints as:
_test:
or r2, r3, r3
or r3, r4, r4
xyz $0, $1, $2 ;; need to print the operands now :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 18:59:47 +00:00
Chris Lattner
2cc2f66c25
adjust to changes in InlineAsm interface. Fix a few minor bugs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25865 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-01 01:28:23 +00:00
Chris Lattner
6656dd1a78
Handle physreg input/outputs. We now compile this:
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int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-31 02:03:41 +00:00
Chris Lattner
04c62c78f4
remove method I just added
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25728 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-28 03:43:09 +00:00
Chris Lattner
4f16e70faa
add a new callback
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25727 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-28 03:37:03 +00:00
Nate Begeman
0aed7840ec
Implement Promote for VAARG, and allow it to be custom promoted for people
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who don't want the default behavior (Alpha).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25726 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-28 03:14:31 +00:00
Nate Begeman
ee625573b5
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
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the same functionality. This addresses another piece of bug 680. Next,
on to fixing Alpha VAARG, which I broke last time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25696 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-27 21:09:22 +00:00
Chris Lattner
ce7518ce92
initial selectiondag support for new INLINEASM node. Note that inline asms
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with outputs or inputs are not supported yet. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25664 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-26 22:24:51 +00:00
Nate Begeman
acc398c195
First part of bug 680:
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Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25606 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-25 18:21:52 +00:00
Evan Cheng
3f23952404
If scheduler choice is the default (-sched=default), use target scheduling
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preference to determine which scheduler to use. SchedulingForLatency ==
Breadth first; SchedulingForRegPressure == bottom up register reduction list
scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25599 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-25 09:12:57 +00:00
Jim Laskey
17d52f7234
Typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25545 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-23 13:34:04 +00:00