Commit Graph

50402 Commits

Author SHA1 Message Date
Bill Wendling
3f56d4b957 Simplify check that optional def is there and is CPSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141602 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 00:10:41 +00:00
Lang Hames
bb5b3f3359 Add a natural stack alignment field to TargetData, and prevent InstCombine from
promoting allocas to preferred alignments that exceed the natural
alignment. This avoids some potentially expensive dynamic stack realignments.

The natural stack alignment is set in target data strings via the "S<size>"
option. Size is in bits and must be a multiple of 8. The natural stack alignment
defaults to "unspecified" (represented by a zero value), and the "unspecified"
value does not prevent any alignment promotions. Target maintainers that care
about avoiding promotions should explicitly add the "S<size>" option to their
target data strings.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141599 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 23:42:08 +00:00
Michael J. Spencer
15565ad758 Fix warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141597 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 23:36:56 +00:00
Devang Patel
db7334dbc5 Revert r141569 and r141576.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141594 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 23:18:02 +00:00
Jim Grosbach
f6c35c59f5 Simplify operand Kind checks a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141592 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 23:06:42 +00:00
Bill Wendling
ef2c86f876 Reapply r141365 now that PR11107 is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141591 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 22:59:55 +00:00
Jim Grosbach
38fbe32315 Add a name to sub-operand for clarity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141590 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 22:55:05 +00:00
Bill Wendling
721e1d2669 If the CPSR is defined by a copy, then we don't want to merge it into an IT
block. E.g., if we have:

  movs  r1, r1
  rsb   r1, 0
  movs  r2, r2
  rsb   r2, 0

we don't want this to be converted to:

  movs  r1, r1
  movs  r2, r2
  itt   mi
  rsb   r1, 0
  rsb   r2, 0

PR11107 & <rdar://problem/10259534>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141589 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 22:52:53 +00:00
Eli Friedman
dca62d53b7 Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141585 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 22:28:47 +00:00
Michael J. Spencer
e2f2f07be7 Object: add getSectionAlignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141581 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 21:55:43 +00:00
Jakob Stoklund Olesen
735fe0f9d0 Give targets a chance to expand even standard pseudos.
Allow targets to expand COPY and other standard pseudo-instructions
before they are expanded with copyPhysReg().

This allows the target to examine the COPY instruction for extra
operands indicating it can be widened to a preferable super-register
copy.  See the ARM -widen-vmovs option.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141578 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 20:34:28 +00:00
Devang Patel
6b50bc9d88 If loop header is also loop exiting block then it may not be safe to hoist instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141576 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 20:32:03 +00:00
Benjamin Kramer
717073c237 X86: Add a subtarget definition for core-avx-i, which is GCC's name for ivy bridge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141571 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 19:35:07 +00:00
Nadav Rotem
a7934dd8e4 Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because the
instruction set has no 64-bit SRA support.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141570 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 19:31:45 +00:00
Devang Patel
9ac743a4ee Add dominance check for the instruction being hoisted.
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141569 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 19:09:20 +00:00
Bruno Cardoso Lopes
9d2fa87816 The Mips specific function for instruction cache invalidation cannot be
compiled on mips32r1 processors because it uses synci and rdhwr instructions
which are supported only on mips32r2, so I replaced this function with the
call to function cacheflush which works for both mips32r1 and mips32r2.
Patch by Sasa Stankovic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141564 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 18:41:02 +00:00
Benjamin Kramer
a86a58695d X86: Add patterns for the movbe instruction (mov + bswap, only available on atom)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141563 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 18:34:56 +00:00
Bill Wendling
eba564ceac Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to
hang, and possibly SPEC/CINT2006/464_h264ref.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141560 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 18:27:30 +00:00
Owen Anderson
042aadd8ee MCAtom extending methods need to extend the range of the atom as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141557 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 18:09:38 +00:00
Bill Wendling
8129d21396 When getting the number of bits necessary for addressing mode
ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141529 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 07:24:23 +00:00
Craig Topper
1f104804bf Put a bunch of calls to ToggleFeature behind proper if statements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141527 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 05:34:02 +00:00
Chad Rosier
29b9d7e4ea Fix a regression from r138445. If we're loading from the frame/base pointer
the tADDrSPi instruction can't be used.  Make sure we're updating the opcode
to tADDi3 in all cases.
rdar://10254707

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141523 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-10 01:03:35 +00:00
Justin Holewinski
68226a4d46 PTX: Print .ptr kernel attributes if PTX version >= 2.2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141508 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-09 15:42:02 +00:00
Craig Topper
da394041c4 Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-09 07:31:39 +00:00
Jakob Stoklund Olesen
b7994fedcb Prevent potential NOREX bug.
A GR8_NOREX virtual register is created when extrating a sub_8bit_hi
sub-register:

  %vreg2<def> = COPY %vreg1:sub_8bit_hi; GR8_NOREX:%vreg2 %GR64_ABCD:%vreg1
  TEST8ri_NOREX %vreg2, 1, %EFLAGS<imp-def>; GR8_NOREX:%vreg2

If such a live range is ever split, its register class must not be
inflated to GR8.  The sub-register copy can only target GR8_NOREX.

I dont have a test case for this theoretical bug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141500 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 20:20:03 +00:00
Jakob Stoklund Olesen
ed74482704 Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies.
In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX
instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot
target all GR8 registers, only those in GR8_NOREX.

TO enforce this, we ensure that all instructions using the
EXTRACT_SUBREG are GR8_NOREX constrained.

This fixes PR11088.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141499 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 18:28:28 +00:00
Che-Liang Chiou
3ae9cf5ba4 Revert r141079: tblgen: add preprocessor as a separate mode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141492 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 12:39:26 +00:00
Nicolas Geoffray
f8557957fb Always check if a method or a type exist before trying to create it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141490 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 11:56:36 +00:00
NAKAMURA Takumi
48f248ad5f lib/Object: Suppress warnings on gcc-4.3.4 cygwin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 11:22:53 +00:00
NAKAMURA Takumi
017449d64b lib/DebugInfo/DWARFDebugLine.cpp: De-Unicode-ify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141484 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 11:22:47 +00:00
NAKAMURA Takumi
3a79eac5b8 Whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141483 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 11:22:41 +00:00
Anton Korobeynikov
2d4b60f3a4 Disable ABS optimization for Thumb1 target, we don't have necessary instructions there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141481 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 08:38:45 +00:00
Akira Hatanaka
4391bb75ec Simplify definition of FP move instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141476 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 03:50:18 +00:00
Akira Hatanaka
c9289f6a71 Define classes and multiclasses for FP binary instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141475 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 03:38:41 +00:00
Akira Hatanaka
bfca0798cf Define multiclasses for FP-to-FP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141474 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 03:29:22 +00:00
Akira Hatanaka
a8de1c1be0 Define classes for FP unary instructions and multiclasses for FP-to-fixed point
conversion instructions. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141473 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 03:19:38 +00:00
Akira Hatanaka
cb518ee5dd Add patterns for unaligned load and store instructions and enable the
instruction selector to generate them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141471 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 02:24:10 +00:00
Andrew Trick
94794dd8d3 Add an extra safety check in front of the optimization in r141442.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141470 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 02:16:39 +00:00
Bill Wendling
d5d1700972 Use the code that lowers the arguments and spills any values which are alive
across unwind edges. This is for the back-end which expects such things.

The code is from the original SjLj EH pass.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141463 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 00:56:47 +00:00
Michael J. Spencer
c6500a5d77 Object: Add support for opening stdin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141449 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 00:17:58 +00:00
Michael J. Spencer
5861893c25 Object: constize Archive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141448 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-08 00:17:45 +00:00
Jim Grosbach
460a90540b ARM NEON assembly parsing and encoding for VDUP(scalar).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141446 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 23:56:00 +00:00
Andrew Trick
c570191060 LSR should only reuse phis that match its formula.
Fixes rdar://problem/5064068


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141442 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 23:46:21 +00:00
Eli Friedman
9eb6b4d91b Fix APInt::operator*= so that it computes the correct result for large integers where there is unsigned overflow. Fix APFloat::toString so that it doesn't depend on the incorrect behavior in common cases (and computes the correct result in some rare cases). Fixes PR11086.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141441 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 23:40:49 +00:00
Nick Lewycky
d2fdb4a285 Don't emit the symbol table entry for the .symtab_shndx section either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141440 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 23:29:53 +00:00
Nick Lewycky
4a8d43e9a7 Remove extraneous curlies. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141439 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 23:28:32 +00:00
Jim Grosbach
21ff17ce1b ARM prefix asmparser operand kind enums for readability.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141438 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 23:24:09 +00:00
Bill Wendling
2acf638216 Take all of the invoke basic blocks and make the dispatch basic block their new
successor. Remove the old landing pad from their successor list, because it's
now the successor of the dispatch block. Now that the landing pad blocks are no
longer the destination of invokes, we can mark them as normal basic blocks
instead of landing pads.

This more closely resembles what the CFG is actually doing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141436 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 23:18:02 +00:00
Bill Wendling
f1083d4139 Take the code that was emitted for the llvm.eh.dispatch.setup intrinsic and emit
it with the new SjLj emitter stuff. This way there's no need to emit that
kind-of-hacky intrinsic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141419 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 22:08:37 +00:00
Bill Wendling
ce370cfd89 Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented to
do. This will be useful later on with the new SJLJ stuff.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141416 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 21:25:38 +00:00
Nick Lewycky
b3429d34b6 Don't emit a shstrtabindex in the reserved range. Spotted by inspection and
patch by Cary Coutant!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141413 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 20:58:24 +00:00
Nick Lewycky
aaae3f6bc1 Clarify/fix typo. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141412 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 20:56:23 +00:00
Jakob Stoklund Olesen
b66f18486a Constrain both operands on MOVZX32_NOREXrr8.
This instruction is explicitly encoded without an REX prefix, so both
operands but be *_NOREX.

Also add an assertion to copyPhysReg() that fires when the MOV8rr_NOREX
constraints are not satisfied.

This fixes a miscompilation in 20040709-2 in the gcc test suite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141410 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 20:15:54 +00:00
Michael J. Spencer
01a4db3ed4 Fix GCC again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141389 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 19:46:12 +00:00
Michael J. Spencer
4344b1ef9b Change relocation API to be per section. This time without breaking GCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141385 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 19:25:32 +00:00
Jim Grosbach
186ffac4d3 Improve ARM assembly parser diagnostic for unexpected tokens.
Consider:
  mov r8, r11 fred

Previously, we issued the not very informative:
x.s:6:1: error: unexpected token in argument list

^

Now we generate:
x.s:5:14: error: unexpected token in argument list
  mov r8, r11 fred
              ^


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141380 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 18:27:04 +00:00
Bill Wendling
a48ad13339 Revert 141376 and 141377 due to breaking the build.
--- Reverse-merging r141377 into '.':
U    tools/llvm-objdump/MachODump.cpp
--- Reverse-merging r141376 into '.':
U    include/llvm/Object/COFF.h
U    include/llvm/Object/ObjectFile.h
U    include/llvm-c/Object.h
U    tools/llvm-objdump/llvm-objdump.cpp
U    lib/Object/MachOObjectFile.cpp
U    lib/Object/COFFObjectFile.cpp
U    lib/Object/Object.cpp
U    lib/Object/ELFObjectFile.cpp



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141379 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 18:25:37 +00:00
David Greene
a1b1b79be1 Remove Multidefs
Multidefs are a bit unwieldy and incomplete.  Remove them in favor of
another mechanism, probably for loops.

Revert "Make Test More Thorough"
Revert "Fix a typo."
Revert "Vim Support for Multidefs"
Revert "Emacs Support for Multidefs"
Revert "Document Multidefs"
Revert "Add a Multidef Test"
Revert "Update Test for Multidefs"
Revert "Process Multidefs"
Revert "Parser Multidef Support"
Revert "Lexer Support for Multidefs"
Revert "Add Multidef Data Structures"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141378 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 18:25:05 +00:00
Michael J. Spencer
f1164a2487 Change relocation API to be per section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141376 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 18:15:25 +00:00
Evan Cheng
7c1780c5fe High bits of movmskp{s|d} and pmovmskb are known zero. rdar://10247336
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141371 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 17:21:44 +00:00
Bob Wilson
6d2f9cec71 Reenable tail calls for iOS 5.0 and later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141370 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 17:17:49 +00:00
Bob Wilson
2fef4573df Reenable use of divmod compiler_rt functions for iOS 5.0 and later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141368 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 16:59:21 +00:00
Matt Beaumont-Gay
7761948761 Move default to top of switch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141366 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 16:27:01 +00:00
Anton Korobeynikov
244455e6d6 Peephole optimization for ABS on ARM.
Patch by Ana Pazos!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141365 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 16:15:08 +00:00
Duncan Sands
3f329cb781 Teach GVN to also propagate switch cases. For example, in this code
switch (n) {
    case 27:
      do_something(x);
    ...
  }
the call do_something(x) will be replaced with do_something(27).  In
gcc-as-one-big-file this results in the removal of about 500 lines of
bitcode (about 0.02%), so has about 1/10 of the effect of propagating
branch conditions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141360 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 08:29:06 +00:00
Craig Topper
75fe5f3bab Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141358 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 07:02:24 +00:00
Andrew Trick
e8deca83c1 PostRA scheduler fix. Clear stale loop dependencies.
Fixes <rdar://problem/10235725>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141357 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 06:33:09 +00:00
Andrew Trick
4563bbaba7 whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141356 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 06:27:02 +00:00
Craig Topper
1b526a98e3 Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141354 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 05:53:50 +00:00
Craig Topper
25f6dfd108 Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141353 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 05:35:38 +00:00
Bill Wendling
217f0e9ca4 Use the correct vreg here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141342 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 23:41:14 +00:00
Bill Wendling
083a8eb063 Generate the dispatch code for a 'thumb' function. This is very similar to the
others. They take the call site value. Determine if it's a proper value. And
then jumps to the correct call site via a jump table.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141341 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 23:37:36 +00:00
Owen Anderson
7011eee9b5 Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141339 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 23:33:11 +00:00
Eli Friedman
8540101252 Remove the old atomic instrinsics. autoupgrade functionality is included with this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141333 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 23:20:49 +00:00
Bill Wendling
95ce2e9c52 Generate the dispatch table for ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141327 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 22:53:00 +00:00
Bill Wendling
e29fa1df55 Refactor some of the code that sets up the entry block for SjLj EH. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141323 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 22:18:16 +00:00
Bill Wendling
5e2cbc1133 Use a thumb ORR instead of thumb2 ORR when in thumb-only mode. (Picky! Picky!)
Place the immediate to OR into a register so that it works.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141319 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 21:51:21 +00:00
Bill Wendling
04f15b4f2f * Set the low bit of the return address when we are in thumb mode.
* Some code cleanup.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141317 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 21:29:56 +00:00
David Greene
d2b9f20b18 Fix List-of-List Processing
Fix VarListElementInit::resolveListElementReference to return a
partially resolved VarListElementInint in the case where full
resolution is not possible.  This allows TableGen to make forward
progress resolving certain complex list expressions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141315 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 21:20:46 +00:00
Matt Beaumont-Gay
3ef12348d7 Fix -asserts build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141313 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 20:59:09 +00:00
Justin Holewinski
9a6eba6203 PTX: Implement signed division
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141306 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 20:00:33 +00:00
Benjamin Kramer
ee573189c6 Use StringSwitch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141305 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 18:53:43 +00:00
Benjamin Kramer
37d42af584 Simplify code. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141299 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 18:23:56 +00:00
David Greene
c2d18f8929 Fix Typo
Compare the entire keyword string.



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2011-10-06 14:37:47 +00:00
Torok Edwin
4df1557f40 Don't require C bindings opcode numbers to be kept in sync.
They are not in sync now, for example Bitcast would show up as LLVMCall.
So instead introduce 2 functions that map to and from the opcodes in the C
bindings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141290 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 12:39:34 +00:00
Torok Edwin
ff12c99d13 ocaml/C bindings: type->isSized()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141288 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 12:13:28 +00:00
Torok Edwin
4917ec9ec7 add binding to read icmp predicate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141287 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 12:13:20 +00:00
Torok Edwin
4f661ab0fb ocaml/C bindings: getmdstring, add num_op, get_op should work on metadata too
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141286 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 12:13:11 +00:00
Torok Edwin
c44943ed4f C/OCaml API to retrieve struct name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141285 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 12:12:50 +00:00
Craig Topper
7ea16b01fa Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141274 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 06:44:41 +00:00
Peter Collingbourne
de8f33c199 Build system infrastructure for multiple tblgens.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141266 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 01:51:51 +00:00
Bill Wendling
930193cb55 Add the MBBs before inserting the instructions. Doing it afterwards could lead
to an infinite loop because of the def-use chains.

Also use a frame load instead of store for the LD instruction.


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2011-10-06 00:53:33 +00:00
Cameron Zwarich
8f8aa815b4 Always merge profitable shifts on A9, not just when they have a single use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141248 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 23:39:02 +00:00
Cameron Zwarich
d78ebe1e12 Remove a check from ARM shifted operand isel helper methods, which were blocking
merging an lsl #2 that has multiple uses on A9. This shift is free, so there is
no problem merging it in multiple places. Other unprofitable shifts will not be
merged.

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2011-10-05 23:38:50 +00:00
Bill Wendling
5cbef19a1d Get the proper call site numbers for the landing pads. Also remove a magic
number (18) for the proper addressing mode.


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2011-10-05 23:28:57 +00:00
David Greene
caa25c81cd Prefix Template Arg Names with Multiclass Name
For consistency, prefix multiclass template arg names with the
multiclass name followed by "::" to avoid name clashes among
multiclass arguments and other entities in the multiclass.

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2011-10-05 22:42:54 +00:00
David Greene
a6d442e651 Process Multidefs
Process each multidef declared in a multiclass.  Iterate through the
list and instantiate a def in the multiclass for each item, resolving
the list item to the temporary iterator (possibly) used in the
multidef ObjectBody.  We then process each generated def in the normal
way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141233 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 22:42:45 +00:00
David Greene
6da674cda1 Parser Multidef Support
Add parser support to recognize multidefs.  No processing on the
multidef is done at this point.  The grammar is:

MultiDef = MULTIDEF ObjectName < Value, Declaration, Value > ObjectBody

The first Value must be resolveable to a list and the second Value
must be resolveable to an integer.  The Declaration is a temporary
value used as an iterator to refer to list items during processing.
It may be passed into the ObjectBody where it will be substituted with
the list value used to instantiate each def.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141232 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 22:42:44 +00:00
David Greene
b9c29eaa3d Lexer Support for Multidefs
Add keyword support for multidefs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141231 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 22:42:35 +00:00
David Greene
e499a2df44 Refactor Multiclass Def Processing
Move the code to instantiate a multiclass def, bind its arguments and
resolve its members into three helper functions.  These will be reused
to support a new kind of multiclass def: a multidef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141229 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 22:42:07 +00:00