Commit Graph

375 Commits

Author SHA1 Message Date
Akira Hatanaka
b7656a9cc4 [mips] Custom-legalize BR_JT.
In N64-static, GOT address is needed to compute the branch address.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176580 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-06 21:32:03 +00:00
Akira Hatanaka
508d11b19c [mips] Add a line which checks function name. Rename file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176543 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-06 01:58:03 +00:00
Akira Hatanaka
5ffd24c49f [mips] Remove android calling convention.
This calling convention was added just to handle functions which return vector
of floats. The fix committed in r165585 solves the problem.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176530 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05 23:22:30 +00:00
Akira Hatanaka
1e3e869899 [mips] Fix MipsCC::analyzeReturn so that, in soft-float mode, fp128 gets
returned in registers $2 and $4.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176527 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05 22:54:59 +00:00
Akira Hatanaka
7433b2e114 [mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctly
handle fp128 returns.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176523 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05 22:41:55 +00:00
Akira Hatanaka
cb2eafdfa3 [mips] Fix MipsTargetLowering::LowerCall to pass fp128 arguments in floating
point registers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176521 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05 22:20:28 +00:00
Akira Hatanaka
5fdee6d2b5 [mips] Correct handling of fp128 (long double) formals and read long double
parameters from floating point registers if target is mips64 hard float.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176520 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05 22:13:04 +00:00
NAKAMURA Takumi
a0a790b0b7 llvm/test/CodeGen/Mips/mips64-f128.ll: Add explicit -mtriple=mips64el-unknown-unknown to appease win32.
FIXME: Is it expected for win32 to affect mips targets?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176471 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05 02:18:59 +00:00
Akira Hatanaka
1ae08e0077 [mips] Print move instructions.
"move $4, $5" is printed instead of "or $4, $5, $zero".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176455 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-04 22:25:01 +00:00
Jack Carter
0b9675d631 Mips specific inline assembler constraint 'R'
'R' An address that can be sued in a non-macro load or store.
This patch includes a positive test case.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176452 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-04 21:33:15 +00:00
Akira Hatanaka
ee767fe2d2 [mips] Fix inefficient code generation.
This patch eliminates the need to emit a constant move instruction when this
pattern is matched:

(select (setgt a, Constant), T, F)

The pattern above effectively turns into this:

(conditional-move (setlt a, Constant + 1), F, T)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176384 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01 21:52:08 +00:00
Akira Hatanaka
c3c3810f51 Set properties for f128 type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176378 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01 21:11:44 +00:00
Akira Hatanaka
aa49f35240 [mips] Remove unused option. Fix 80-column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176330 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01 02:17:02 +00:00
Akira Hatanaka
1f0aca857b [mips] Add the capability to search delay slot filling instructions in
successor basic blocks.

Currently this is off by default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176329 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01 02:03:51 +00:00
Akira Hatanaka
e760675b0e [mips] Add capability to search in the forward direction for instructions that
can fill the delay slot.

Currently, this is off by default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176320 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01 00:50:52 +00:00
Akira Hatanaka
a56f411961 [mips] Define class MemDefsUses.
This class tracks dependence between memory instructions using underlying
objects of memory operands. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176313 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01 00:16:31 +00:00
Reed Kotler
50354a3f4a Expand pseudos/macros for Selt. This is the last of the complex
macros.The rest is some small misc. stuff.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175950 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-23 03:09:56 +00:00
Akira Hatanaka
6068932940 [mips] Emit call16 operator instead of got_disp. The former allows lazy binding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175920 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-22 21:10:03 +00:00
Reed Kotler
7617d032ae Expand mips16 SelT form pseudso/macros.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175862 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-22 05:10:51 +00:00
Reed Kotler
ffbe432595 Expand the sel pseudo/macro. This generates basic blocks where previously
there were inline br .+4 instructions. Soon everything can enjoy the
full instruction scheduling experience.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175718 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-21 04:22:38 +00:00
Reed Kotler
65692c809e Expand pseudos/macros:
SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16
$T8 shows up as register $24 when emitted from C++ code so we had
to change some tests that were already there for this functionality.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175593 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-20 05:45:15 +00:00
Reed Kotler
8a20844e27 Expand pseudos/macros BteqzT8SltiX16, BteqzT8SltiuX16,
BtnezT8SltiX16, BtnezT8SltiuX16 .



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175486 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 03:56:57 +00:00
Reed Kotler
f801675207 Expand pseudos BteqzT8CmpiX16 and BtnezT8CmpiX16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175474 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 00:20:58 +00:00
Reed Kotler
bb01b3cb93 Expand macro/pseudo instructions BtnezT8SltX16 and BtnezT8SltuX16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175420 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 05:43:03 +00:00
Reed Kotler
dabfebb5c6 Expand pseudo/macro BteqzT8SltX16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175417 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 04:04:26 +00:00
Reed Kotler
a8601bb4ff Expand macro/pseudo BteqzT8CmpX16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175416 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 03:06:29 +00:00
Reed Kotler
da4afa72f7 Beginning of expanding all current mips16 macro/pseudo instruction sequences.
This expansion will be moved to expandISelPseudos as soon as I can figure
out how to do that. There are other instructions which use this 
ExpandFEXT_T8I816_ins and as soon as I have finished expanding them all,
I will delete the macro asm string text so it has no way to be used
in the future.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175413 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 00:59:04 +00:00
Reed Kotler
5cf38fd763 Fix minor mips16 issues in directives for function prologue. Probably this does
not matter but makes it more gcc compatible which avoids possible subtle
problems. Also, turned back on a disabled check in helloworld.ll. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175237 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 01:04:38 +00:00
Reed Kotler
6b9d461780 For Mips 16, add the optimization where the 16 bit form of addiu sp can be used
if the offset fits in 11 bits. This makes use of the fact that the abi
requires sp to be 8 byte aligned so the actual offset can fit in 8
bits. It will be shifted left and sign extended before being actually used.
The assembler or direct object emitter will shift right the 11 bit
signed field by 3 bits. We don't need to deal with that here.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175073 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 20:28:27 +00:00
Reed Kotler
8080696103 Make jumptables work for -static
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175044 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-13 08:32:14 +00:00
Reed Kotler
b2d1275188 Add the 16 bit version of addiu. To the assembler, the 16 and 32 bit are the
same so we put in the comment field an indicator when we think we are
emitting the 16 bit version. For the direct object emitter, the difference is 
important as well as for other passes which need an accurate count of 
program size. There will be other similar putbacks to this for various
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174747 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-08 21:42:56 +00:00
Reed Kotler
61b97b8c17 When Mips16 frames grow large, the immediate field may exceed the maximum
allowed size for the instruction. This code uses RegScavenger to fix this.
We sometimes need 2 registers for Mips16 so we must handle things
differently than how register scavenger is normally used.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174696 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-08 03:57:41 +00:00
Reed Kotler
24b339dcdc Make sure we call externals from libraries properly when -static.
For example, when we are doing mips16 hard float or soft float.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174583 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07 04:34:51 +00:00
Reed Kotler
6e3443eed4 Enable jumps when in -static mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174580 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07 03:49:51 +00:00
Akira Hatanaka
baabdecbb9 [mips] Do not use function CC_MipsN_VarArg unless the function being analyzed
is a vararg function.

The original code was examining flag OutputArg::IsFixed to determine whether
CC_MipsN_VarArg or CC_MipsN should be called. This is not correct, since this
flag is often set to false when the function being analyzed is a non-variadic
function.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174442 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05 21:18:11 +00:00
Jack Carter
37ef65b9c1 This patch that sets the EmitAlias flag in td files
and enables the instruction printer to print aliased 
instructions. 

Due to usage of RegisterOperands a change in common 
code (utils/TableGen/AsmWriterEmitter.cpp) is required 
to get the correct register value if it is a RegisterOperand.

Contributer: Vladimir Medic
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174358 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05 08:32:10 +00:00
Reed Kotler
63f3312355 Start static relocation implementation for mips16.
This checkin makes hello world work. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174264 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-02 04:07:35 +00:00
Akira Hatanaka
25832e2aa9 [mips] Test case for r173862.
Patch by Sasa Stankovic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173863 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30 00:28:15 +00:00
Akira Hatanaka
d2047c6001 [mips] Set flag neverHasSideEffects flag on some of the floating point instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173401 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25 00:20:39 +00:00
Reed Kotler
8453b3f66a The next phase of Mips16 hard float implementation.
Allow Mips16 routines to call Mips32 routines that have abi requirements
that either arguments or return values are passed in floating point 
registers. This handles only the pic case. We have not done non pic
for Mips16 yet in any form.

The libm functions are Mips32, so with this addition we have a complete
Mips16 hard float implementation.

We still are not able to complete mix Mip16 and Mips32 with hard float.
That will be the next phase which will have several steps. For Mips32
to freely call Mips16 some stub functions must be created.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173320 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-24 04:24:02 +00:00
Akira Hatanaka
a88322c283 [mips] Implement MipsRegisterInfo::getRegPressureLimit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173197 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-22 21:34:25 +00:00
Akira Hatanaka
e13f441e00 [mips] MipsTargetLowering::getSetCCResultType should return a vector type if
vectors are being compared.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171517 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-04 20:06:01 +00:00
Reed Kotler
e30843ded9 Add test case for r170674
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170823 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 00:55:10 +00:00
Reed Kotler
cef95f702a fix most of remaining issues with large frames.
these patches are tested a lot by test-suite but
make check tests are forthcoming once the next
few patches that complete this are committed.
with the next few patches the pass rate for mips16 is
near 100%



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170656 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 04:07:42 +00:00
Akira Hatanaka
68fe665b9a [mips] Use "or $r0, $r1, $zero" instead of "addu $r0, $zero, $r1" to copy
physical register $r1 to $r0.

GNU disassembler recognizes an "or" instruction as a "move", and this change
makes the disassembled code easier to read.

Original patch by Reed Kotler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170655 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 04:06:06 +00:00
Reed Kotler
2c3a4641a7 This patch is needed to make c++ exceptions work for mips16.
Mips16 is really a processor decoding mode (ala thumb 1) and in the same
program, mips16 and mips32 functions can exist and can call each other.

If a jal type instruction encounters an address with the lower bit set, then
the processor switches to mips16 mode (if it is not already in it). If the
lower bit is not set, then it switches to mips32 mode.

The linker knows which functions are mips16 and which are mips32.
When relocation is performed on code labels, this lower order bit is
set if the code label is a mips16 code label.

In general this works just fine, however when creating exception handling
tables and dwarf, there are cases where you don't want this lower order
bit added in.

This has been traditionally distinguished in gas assembly source by using a
different syntax for the label.

lab1:      ; this will cause the lower order bit to be added
lab2=.     ; this will not cause the lower order bit to be added

In some cases, it does not matter because in dwarf and debug tables
the difference of two labels is used and in that case the lower order
bits subtract each other out.

To fix this, I have added to mcstreamer the notion of a debuglabel.
The default is for label and debug label to be the same. So calling
EmitLabel and EmitDebugLabel produce the same result.

For various reasons, there is only one set of labels that needs to be
modified for the mips exceptions to work. These are the "$eh_func_beginXXX" 
labels.

Mips overrides the debug label suffix from ":" to "=." .

This initial patch fixes exceptions. More changes most likely
will be needed to DwarfCFException to make all of this work
for actual debugging. These changes will be to emit debug labels in some
places where a simple label is emitted now.

Some historical discussion on this from gcc can be found at:
http://gcc.gnu.org/ml/gcc-patches/2008-08/msg00623.html
http://gcc.gnu.org/ml/gcc-patches/2008-11/msg01273.html 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170279 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-16 04:00:45 +00:00
Reed Kotler
ed23fa8e55 This code implements most of mips16 hardfloat as it is done by gcc.
In this case, essentially it is soft float with different library routines.
The next step will be to make this fully interoperational with mips32 floating
point and that requires creating stubs for functions with signatures that
contain floating point types.

I have a more sophisticated design for mips16 hardfloat which I hope to
implement at a later time that directly does floating point without the need
for function calls.

The mips16 encoding has no floating point instructions so one needs to
switch to mips32 mode to execute floating point instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170259 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-15 00:20:05 +00:00
Akira Hatanaka
ed185daba7 [mips] Do not copy GOT address to register $gp if the function being called has
internal linkage.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170092 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 03:17:29 +00:00
Evan Cheng
a16e49d56f Fix a logic bug in inline expansion of memcpy / memset with an overlapping
load / store pair. It's not legal to use a wider load than the size of
the remaining bytes if it's the first pair of load / store.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170018 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-12 20:43:23 +00:00
Akira Hatanaka
f09a03776d [mips] Generate big GOT code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168460 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21 20:40:38 +00:00