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1119 Commits

Author SHA1 Message Date
Evan Cheng
23066288fd For now, don't split live intervals around x87 stack register barriers. FpGET_ST0_80 must be right after a call instruction (and ADJCALLSTACKUP) so we need to find a way to prevent reload of x87 registers between them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58230 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-27 07:14:50 +00:00
Evan Cheng
aaf510c932 Do not shrink wrap live interval in a mbb if it's livein any of its successor blocks. The mbb can be revisited again after all of the successors are processed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58184 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-26 07:49:03 +00:00
Evan Cheng
79d5b5acae Handle cases where there aren't uses in the barrier mbb. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58174 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-25 23:49:39 +00:00
Evan Cheng
78dfef771b If val# def is ~0U, meaning it's defined by a PHI, and it's previously split, spill before the barrier because it's impossible to determine if all the defs are spilled in the same spill slot. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58129 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-25 00:52:41 +00:00
Dale Johannesen
47106ba658 Be kind to non-x86 hosts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58113 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-24 21:20:25 +00:00
Duncan Sands
4047f4a0b4 Fix translateX86CC: if SetCCOpcode is SETULE and 
LHS is a foldable load, then LHS and RHS are swapped
and SetCCOpcode is changed to SETUGT.  But the later
code is expecting operands to be the wrong way round
for SETUGT, but they are not in this case, resulting
in an inverted compare.  The solution is to move the
load normalization before the correction for SETUGT.
This bug was tickled by LegalizeTypes which happened
to legalize the testcase slightly differently to
LegalizeDAG.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58092 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-24 13:03:10 +00:00
Evan Cheng
06587497dc Avoid splitting an interval multiple times; avoid splitting re-materializable val# (for now). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58068 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-24 02:05:00 +00:00
Dan Gohman
7ea1ca6229 Fix SelectionDAGBuild lowering of Select instructions to 
handle first-class aggregate values. Also, fix a bug in
the Ret handling for empty aggregates.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57925 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-21 20:00:42 +00:00
Chris Lattner
7fb501c9cd really fix run line 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57889 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-21 03:55:19 +00:00
Chris Lattner
0294ac2e9a fix run line 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57888 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-21 03:54:49 +00:00
Chris Lattner
402135f9e9 remove some unneeded eh generation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57887 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-21 03:49:19 +00:00
Dan Gohman
4401361a2f Don't create TargetGlobalAddress nodes with offsets that don't fit 
in the 32-bit signed offset field of addresses. Even though this
may be intended, some linkers refuse to relocate code where the
relocated address computation overflows.

Also, fix the sign-extension of constant offsets to use the
actual pointer size, rather than the size of the GlobalAddress
node, which may be different, for example on x86-64 where MVT::i32
is used when the address is being fit into the 32-bit displacement
field.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57885 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-21 03:38:42 +00:00
Dan Gohman
279c22e6da Optimized FCMP_OEQ and FCMP_UNE for x86. 
Where previously LLVM might emit code like this:

        ucomisd %xmm1, %xmm0
        setne   %al
        setp    %cl
        orb     %al, %cl
        jne     .LBB4_2

it now emits this:

        ucomisd %xmm1, %xmm0
        jne     .LBB4_2
        jp      .LBB4_2

It has fewer instructions and uses fewer registers, but it does
have more branches. And in the case that this code is followed by
a non-fallthrough edge, it may be followed by a jmp instruction,
resulting in three branch instructions in sequence. Some effort
is made to avoid this situation.

To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and
FCMP_UNE in lowered form, and replace them with code that emits
two branches, except in the case where it would require converting
a fall-through edge to an explicit branch.

Also, X86InstrInfo.cpp's branch analysis and transform code now
knows now to handle blocks with multiple conditional branches. It
uses loops instead of having fixed checks for up to two
instructions. It can now analyze and transform code generated
from FCMP_OEQ and FCMP_UNE.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57873 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-21 03:29:32 +00:00
Dan Gohman
3afda6e9d1 When the coalescer is doing rematerializing, have it remove 
the copy instruction from the instruction list before asking the
target to create the new instruction. This gets the old instruction
out of the way so that it doesn't interfere with the target's
rematerialization code. In the case of x86, this helps it find
more cases where EFLAGS is not live.

Also, in the X86InstrInfo.cpp, teach isSafeToClobberEFLAGS to check
to see if it reached the end of the block after scanning each
instruction, instead of just before. This lets it notice when the
end of the block is only two instructions away, without doing any
additional scanning.

These changes allow rematerialization to clobber EFLAGS in more
cases, for example using xor instead of mov to set the return value
to zero in the included testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57872 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-21 03:24:31 +00:00
Chris Lattner
01426e1a27 Fix gcc.c-torture/compile/920520-1.c by inserting bitconverts 
for strange asm conditions earlier.  In this case, we have a
double being passed in an integer reg class.  Convert to like
sized integer register so that we allocate the right number 
for the class (two i32's for the f64 in this case).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57862 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-21 00:45:36 +00:00
Dan Gohman
6520e20e4f Teach DAGCombine to fold constant offsets into GlobalAddress nodes, 
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)

This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.

This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.

Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.

The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57748 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-18 02:06:02 +00:00
Evan Cheng
af42fe36ac Fix PR2898. Spiller delete a store for reuse before it knows for sure the reuse happened. 
Patch by Lang Hames!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57720 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-17 20:56:41 +00:00
Chris Lattner
3d0c4c4657 Fix a bug where the x86 backend would reject 64-bit r constraints when 
in 32-bit mode instead of assigning a register pair.  This has nothing to
do with PR2356, but I happened to notice it while working on it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57704 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-17 17:59:52 +00:00
Evan Cheng
6784598895 Fix a very subtle spiller bug: UpdateKills should not forget to track defs of aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57673 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-17 06:16:07 +00:00
Dan Gohman
63f97201dc Fun x86 encoding tricks: when adding an immediate value of 128, 
use a SUB instruction instead of an ADD, because -128 can be
encoded in an 8-bit signed immediate field, while +128 can't be.
This avoids the need for a 32-bit immediate field in this case.

A similar optimization applies to 64-bit adds with 0x80000000,
with the 32-bit signed immediate field.

To support this, teach tablegen how to handle 64-bit constants.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57663 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-17 01:33:43 +00:00
Dan Gohman
74feef261a Define patterns for shld and shrd that match immediate 
shift counts, and patterns that match dynamic shift counts
when the subtract is obscured by a truncate node.

Add DAGCombiner support for recognizing rotate patterns
when the shift counts are defined by truncate nodes.

Fix and simplify the code for commuting shld and shrd
instructions to work even when the given instruction doesn't
have a parent, and when the caller needs a new instruction.

These changes allow LLVM to use the shld, shrd, rol, and ror
instructions on x86 to replace equivalent code using two
shifts and an or in many more cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57662 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-17 01:23:35 +00:00
Dan Gohman
c90a5c2878 Fix this test so it actually runs the grep lines. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57653 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-16 23:57:54 +00:00
Duncan Sands
078ae1e6ee Testcase for PR2762. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57633 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-16 08:56:46 +00:00
Evan Cheng
7f04268176 - Add target lowering hooks that specify which setcc conditions are illegal, 
i.e. conditions that cannot be checked with a single instruction. For example,
SETONE and SETUEQ on x86.
- Teach legalizer to implement *illegal* setcc as a and / or of a number of
legal setcc nodes. For now, only implement FP conditions. e.g. SETONE is
implemented as SETO & SETNE, SETUEQ is SETUO | SETEQ.
- Move x86 target over.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57542 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-15 02:05:31 +00:00
Dan Gohman
7b8e96401c When doing the very-late shift-and address-mode optimization, 
create a new DAG node to represent the new shift to keep the
DAG consistent, even though it'll almost always be folded into
the address.

If a user of the resulting address has multiple uses, the
nodes may get revisited by a later MatchAddress call, in which
case DAG inconsistencies do matter.

This fixes PR2849.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57465 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-13 20:52:04 +00:00
Evan Cheng
195cd3a58d Also update sub-register intervals after a trivial computation is rematt'ed for a copy instruction. PR2775. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57458 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-13 18:35:52 +00:00
Evan Cheng
09fd418106 Add a test case for _Complex passed as a FCA. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57456 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-13 18:13:07 +00:00
Chris Lattner
e563bbc312 Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as 
parameters instead of raw Constants.  This prevents the constants from
being selected by the isel pass, fixing PR2735.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57385 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-11 22:08:30 +00:00
Dan Gohman
eb0d6abee3 Remove -disable-fast-isel. Use cl::boolOrDefault with -fast-isel 
instead.

So now: -fast-isel or -fast-isel=true enable fast-isel, and
-fast-isel=false disables it. Fast-isel is also on by default
with -fast, and off by default otherwise.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57270 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-07 23:00:56 +00:00
Dan Gohman
00877fc657 Add a testcase for i256 add. i256 isn't fully supported in 
codegen right now, but add and subtract work.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57260 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-07 20:39:12 +00:00
Anders Carlsson
ae436cecca Certain patterns involving the "movss" instruction were marked as requiring SSE2, when in reality movss is an SSE1 instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57246 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-07 16:14:11 +00:00
Dale Johannesen
2df5eec2ff Be more precise about which conversions of NaNs 
are Inexact.  (These are not Inexact as defined
by IEEE754, but that seems like a reasonable way
to abstract what happens:  information is lost.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57218 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-06 22:59:10 +00:00
Evan Cheng
882cdfde51 Fix PR2850 and PR2863. Only generate movddup for 128-bit SSE vector shuffles. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57210 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-06 21:13:08 +00:00
Anton Korobeynikov
c4e8bec703 Revert r56675 - it breaks unwinding runtime everywhere. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57048 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-04 11:09:36 +00:00
Dan Gohman
022b21ff7c Fix a bug in the local allocator's liveness computation where it 
was setting kill flags on tied uses in two-address instructions.
The kill flags were causing the allocator to think it could
allocate the use and its tied def in different registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57039 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-04 00:31:14 +00:00
Dale Johannesen
48c1bc2ace Handle some 64-bit atomics on x86-32, some of the time. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56963 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-02 18:53:47 +00:00
Dan Gohman
d790a5ceee Fix a think-o in isSafeToMove. This fixes it from thinking that 
volatile memory references are safe to move.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56948 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-02 15:04:30 +00:00
Dan Gohman
0b3baaa7fb Disable fast-isel for this test, as it doesn't emit the same 
number of instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56940 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-01 23:48:35 +00:00
Devang Patel
4ae641f4d1 Remove OptimizeForSize global. Use function attribute optsize. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56937 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-01 23:18:38 +00:00
Dan Gohman
e7aa7baa76 Split this test and move it into target-specific directories. 
This fixes failures on configurations that don't have one or the
other targets enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56926 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-01 19:46:30 +00:00
Dan Gohman
e7891c705c nounwind-ify this test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56918 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-01 15:07:14 +00:00
Bill Wendling
ae595dc9da Moved this option to the front-end. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56901 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-01 01:02:18 +00:00
Dan Gohman
70695fee51 Use explicit target-triples to unbreak this test on non-darwin systems. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56896 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-10-01 00:25:38 +00:00
Bill Wendling
6e08738d4b Just don't transform this memset into "bzero" if no-builtin is specified. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56888 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-30 22:05:33 +00:00
Bill Wendling
fd8ca5a0ef - Initialize "--no-builtin" to "false". 
- Testcase for r56885.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56886 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-30 21:40:30 +00:00
Evan Cheng
dc37786595 Re-apply 56835 along with header file changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56848 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-30 15:44:16 +00:00
Duncan Sands
46292be362 Revert commit 56835 since it breaks the build. 
"If a re-materializable instruction has a register
operand, the spiller will change the register operand's
spill weight to HUGE_VAL to avoid it being spilled.
However, if the operand is already in the queue ready
to be spilled, avoid re-materializing it".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56837 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-30 10:00:30 +00:00
Evan Cheng
d41474d2c0 If a re-materializable instruction has a register operand, the spiller will change the register operand's spill weight to HUGE_VAL to avoid it being spilled. However, if the operand is already in the queue ready to be spilled, avoid re-materializing it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56835 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-30 06:36:58 +00:00
Evan Cheng
d47e0b664f Fix PR2835. Do not change the width of a volatile load. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56792 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-29 17:26:18 +00:00
Evan Cheng
184793fc8a Re-apply 56683 with fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56748 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-27 01:56:22 +00:00
Evan Cheng
b7a75a5a54 Implement "punpckldq %xmm0, $xmm0" as "pshufd $0x50, %xmm0, %xmm" unless optimizing for code size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56711 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-26 23:41:32 +00:00
Bill Wendling
d5d8191b20 Temporarily reverting r56683. This is causing a failure during the build of llvm-gcc: 
/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -mmacosx-version-min=10.4 -O2  -O2 -g -O2  -DIN_GCC    -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition  -isystem ./include  -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED  -I. -I. -I../../llvm-gcc.src/gcc -I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include -I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include  -I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Gir/devel/llvm/clean/llvm.obj/include -I/Volumes/Gir/devel/llvm/clean/llvm.src/include -fexceptions -fvisibility=hidden -DHIDE_EXPORTS -c ../../llvm-gcc.src/gcc/unwind-dw2-fde-darwin.c -o libgcc/./unwind-dw2-fde-darwin.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) && TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"), function runOnMachineFunction, file /Volumes/Gir/devel/llvm/clean/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp, line 311.
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
{standard input}:3521:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
{standard input}:3521:symbol: "_dwarf_reg_size_table" can't be undefined in a subtraction expression
{standard input}:3520:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56703 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-26 22:10:44 +00:00
Evan Cheng
36a55023c1 Fix @llvm.frameaddress codegen. FP elimination optimization should be disabled when frame address is desired. Also add support for depth > 0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56683 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-26 19:48:35 +00:00
Evan Cheng
a67f32abb5 Avoid spilling EBP / RBP twice in the prologue. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56675 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-26 19:14:21 +00:00
Evan Cheng
4dcc8a373d Prefer movlhps over punpcklqdq, etc. in more cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56627 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-25 23:35:16 +00:00
Evan Cheng
0b457f0c3a With sse3 and when the source is a load or has multiple uses, favors movddup over shuffp*, pshufd, etc. Without sse3 or when the source is from a register, make use of movlhps 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56620 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-25 20:50:48 +00:00
Dale Johannesen
c9c6da61ac Accept 'inreg' attribute on x86 functions as 
meaning sse_regparm (i.e. float/double values go
in XMM0 instead of ST0).  Update documentation
to reflect reality.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56619 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-25 20:47:45 +00:00
Evan Cheng
ca57f78332 Fix patterns for SSE4.1 move and sign extend instructions. Also add instructions which fold VZEXT_MOVL and VZEXT_LOAD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56594 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-24 23:27:55 +00:00
Dale Johannesen
8e3455ba17 Remove SelectionDag early allocation of registers 
for earlyclobbers.  Teach Local RA about earlyclobber,
and add some tests for it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56592 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-24 23:13:09 +00:00
Evan Cheng
da43bcf624 Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56526 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-24 00:05:32 +00:00
Evan Cheng
364091e090 Support x86 specific inline asm modifier 'J'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56483 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-22 23:57:37 +00:00
Arnold Schwaighofer
290ae0398e Change the calling convention used when tail call optimization is enabled from CC_X86_32_TailCall to CC_X86_32_FastCC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56436 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-22 14:50:07 +00:00
Evan Cheng
5e8d9def77 Fix PR2808. When regalloc runs out of register, it spill a physical register around the live interval being allocated. Do not continue to try to spill another register, just grab the physical register and move on. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56381 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-20 01:28:05 +00:00
Evan Cheng
4070e60efe Clean up the test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56380 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-20 01:26:27 +00:00
Evan Cheng
91a23c8233 No need to print function stubs for Mac OS X 10.5 and up. Linker will handle it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56378 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-20 00:13:45 +00:00
Dan Gohman
2ff7fd1461 Refactor X86SelectConstAddr, folding it into X86SelectAddress. This 
results in better code for globals. Also, unbreak the local CSE for
GlobalValue stub loads.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56371 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-19 22:16:54 +00:00
Evan Cheng
20580a1cf6 Re-materalized definition instructions may be dead. Whack them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56352 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-19 17:38:47 +00:00
Dale Johannesen
91aac1015e Add a bit to mark operands of asm's that conflict 
with an earlyclobber operand elsewhere.  Propagate
this bit and the earlyclobber bit through SDISel.
Change linear-scan RA not to allocate regs in a way 
that conflicts with an earlyclobber.  See also comments.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56290 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-17 21:13:11 +00:00
Dan Gohman
ad7321f58a Teach LSR to optimize away SMAX operations for tripcounts in common 
cases.  See the comment above OptimizeSMax for the full story, and
the testcase for an example. This cancels out a pessimization
commonly attributed to indvars, and will allow us to lift some of
the artificial throttles in indvars, rather than add new ones.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56230 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-15 21:22:06 +00:00
Arnold Schwaighofer
363f53f3ec Add indirect tail call (function pointer) examples. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56127 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-11 22:24:28 +00:00
Arnold Schwaighofer
1fdc40f062 When tailcallopt is enabled all fastcc calls must have an aligned argument stack size. Add a test case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56119 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-11 20:28:43 +00:00
Evan Cheng
8db866808c Fix PR2748. Avoid coalescing physical register with virtual register which would create illegal extract_subreg. e.g. 
vr1024 = extract_subreg vr1025, 1
...
vr1024 = mov8rr AH
If vr1024 is coalesced with AH, the extract_subreg is now illegal since AH does not have a super-reg whose sub-register 1 is AH.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56118 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-11 20:07:10 +00:00
Evan Cheng
4086906a0f Fix PR2783 - coalescer bug. Missing a TargetRegisterInfo::isVirtualRegister check. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56112 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-11 18:40:32 +00:00
Evan Cheng
d9c553f262 Propagate subreg index when promoting a load to a copy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56085 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-11 01:02:12 +00:00
Evan Cheng
b188dd9c5b Fix a fastcc + sret bug. If fastcc and sret, callee doesn't need to pop the hidden struct ptr; Re-enable fastcc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56061 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-10 18:25:29 +00:00
Evan Cheng
5530216989 Fix PR2757. Ignore liveinterval register allocation preference if the preference register is not in the right register class. This can happen due to sub-register coalescing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56006 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-09 20:22:01 +00:00
Evan Cheng
59fbc80f6b Fix a constant lowering bug. Now we can do load and store instructions with funky getelementptr embedded in the address operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55975 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-09 01:26:59 +00:00
Anton Korobeynikov
369bbbb421 Reapply 55902: Add test for checking proper lowering of eh_return & unwind init intrinsics on 32bit x86 targets 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55960 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-08 21:14:36 +00:00
Anton Korobeynikov
b9fb005246 Reapply 55903: Testcase for 64-bit lowering of eh_return & unwind_init 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55959 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-08 21:14:19 +00:00
Bill Wendling
fdddcc0575 Remove these testcases associated with changes between r 55898 and r 55909. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55931 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-08 18:00:39 +00:00
Bill Wendling
a425e0073d Reverting r55898 to r55909. One of these patches was causing an ICE during the full bootstrap on Darwin: 
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/bin/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/lib/
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/include
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include
-O2  -O2 -g -O2  -DIN_GCC    -W -Wall -Wwrite-strings
-Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition
-isystem ./include  -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2
-D__GCC_FLOAT_NOT_NEEDED  -I. -I. -I../../llvm-gcc.src/gcc
-I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include
-I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include
-I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.obj/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/include
-DSHARED -m64 -DL_negdi2 -c ../../llvm-gcc.src/gcc/libgcc2.c -o
libgcc/x86_64/_negdi2_s.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) &&
TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical
register live information"), function runOnMachineFunction, file
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp,
line 311.
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/bin/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/lib/
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/include
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include
-O2  -O2 -g -O2  -DIN_GCC    -W -Wall -Wwrite-strings
-Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition
-isystem ./include  -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2
-D__GCC_FLOAT_NOT_NEEDED  -I. -I. -I../../llvm-gcc.src/gcc
-I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include
-I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include
-I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.obj/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/include
-DSHARED -m64 -DL_lshrdi3 -c ../../llvm-gcc.src/gcc/libgcc2.c -o
libgcc/x86_64/_lshrdi3_s.o
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
{standard input}:unknown:Undefined local symbol LBB21_11
{standard input}:unknown:Undefined local symbol LBB21_12
{standard input}:unknown:Undefined local symbol LBB21_13
{standard input}:unknown:Undefined local symbol LBB21_8


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55928 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-08 17:59:12 +00:00
Evan Cheng
debdea0a66 Handle calls which produce i1 results: promote to i8 but and it with 1 to get the low bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55925 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-08 17:15:42 +00:00
Anton Korobeynikov
e665c0789e Testcase for 64-bit lowering of eh_return & unwind_init 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55903 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-08 14:23:16 +00:00
Anton Korobeynikov
a8268a77df Add test for checking proper lowering of eh_return & unwind init intrinsics on 32bit x86 targets 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55902 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-08 14:22:57 +00:00
Evan Cheng
98d2d07d41 Correctly handle physical register inputs. They are not explicit input operands in the resulting machine instrs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55893 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-08 08:39:33 +00:00
Evan Cheng
10a8d9c737 Handle x86 truncate to i8 with target hook for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55877 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-07 08:47:42 +00:00
Eli Friedman
d0c0fae63b Fix for PR2687: Add patterns to match sint_to_fp and fp_to_sint for <2 x 
i32>.  This is a little messy, but it works.

We should really get rid of the intrinsics, though, since they map
perfectly well to standard LLVM instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55864 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 23:07:03 +00:00
Evan Cheng
7f132122c8 Fix test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55849 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 20:04:37 +00:00
Evan Cheng
e2471a9169 If SSE2 is available, x86 should pass first 3 f32/f64 arguments in XMM registers for fastcc calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55840 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 17:24:07 +00:00
Evan Cheng
4a03775777 For whatever the reason, x86 CallingConv::Fast (i.e. fastcc) was not passing scalar arguments in registers. This patch defines a new fastcc CC which is slightly different from the FastCall CC. In addition to passing integer arguments in ECX and EDX, it also specify doubles are passed in 8-byte slots which are 8-byte aligned (instead of 4-byte aligned). This avoids a potential performance hazard where doubles span cacheline boundaries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55807 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-04 22:59:58 +00:00
Owen Anderson
79924eb6f5 Fix the ordering of operands to the store (inverted relative to LLVM IR), and fix the testcase. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55777 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-04 16:48:33 +00:00
Owen Anderson
a3971dfbfe Add a first attempt at implementing stores for X86 fast isel using target hooks. 
Dan or Evan, please review.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55764 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-04 07:08:58 +00:00
Evan Cheng
373d50af1d Load from GV stub should be locally CSE'd. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55763 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-04 06:18:33 +00:00
Evan Cheng
c2feb5c262 Remove code that pad number of bytes to pop for X86_FastCall CC. The code doesn't do the "aligning" for Cygwin, Mingw, and Windows. But aligning it on Darwin and Linux breaks gcc compatibility. That ruled out all the platforms we support! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55756 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-04 01:04:15 +00:00
Evan Cheng
8b19e56051 Add X86 target hook to implement load (even from GlobalAddress). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55693 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-03 06:44:39 +00:00
Evan Cheng
cd04708f59 Re-apply 55467 with fix. If copy is being replaced by remat'ed def, transfer the implicit defs onto the remat'ed instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55564 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-30 09:09:33 +00:00
Evan Cheng
eb9f89287e Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55558 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-30 02:03:58 +00:00
Evan Cheng
456704476f Swap fp comparison operands and change predicate to allow load folding (safely this time). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55553 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 23:22:12 +00:00
Evan Cheng
50ead9099d xfail this. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55550 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 22:59:13 +00:00
Evan Cheng
4d46d0af58 Swap fp comparison operands and change predicate to allow load folding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55521 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 23:48:31 +00:00
Dan Gohman
a3f8b7a4ce Optimize DAGCombiner's worklist processing. Previously it started 
its work by putting all nodes in the worklist, requiring a big
dynamic allocation. Now, DAGCombiner just iterates over the AllNodes
list and maintains a worklist for nodes that are newly created or
need to be revisited. This allows the worklist to stay small in most
cases, so it can be a SmallVector.

This has the side effect of making DAGCombine not miss a folding
opportunity in alloca-align-rounding.ll.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55498 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 21:01:56 +00:00
Dan Gohman
f641395435 Revert r55467; it causes regressions in UnitTests/Vector/divides, 
Benchmarks/sim/sim, and others on x86-64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55475 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 17:22:54 +00:00
Evan Cheng
9242cb8b82 If a copy isn't coalesced, but its src is defined by trivial computation. Re-materialize the src to replace the copy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55467 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 07:53:51 +00:00
Dale Johannesen
f2c785edf0 This test crashes on non-x86 host; make SSE explicit. 
Feel free to fix a better way!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55456 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 01:51:09 +00:00
Dan Gohman
10df0fa73e Basic FastISel support for floating-point constants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55401 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-27 01:09:54 +00:00
Chris Lattner
6ba50a9252 If an xmm register is referenced explicitly in an inline asm, make sure to 
assign it to a version of the xmm register with the regclass that matches its
type.  This fixes PR2715, a bug handling some crazy xpcom case in mozilla.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55358 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-26 06:19:02 +00:00
Evan Cheng
ab6c3bb44d Try approach to moving call address load inside of callseq_start. Now it's done during the preprocess of x86 isel. callseq_start's chain is changed to load's chain node; while load's chain is the last of callseq_start or the loads or copytoreg nodes inserted to move arguments to the right spot. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55338 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-25 21:27:18 +00:00
Owen Anderson
6d0c25ec3a Add support for fast isel of (integer) immediate materialization pattens, and use them to support 
bitcast of constants in fast isel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55325 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-25 20:20:32 +00:00
Evan Cheng
e7321441ac Fix asm printing of MOVSDto64mr and MOV64toSDrm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55300 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-25 04:11:42 +00:00
Bill Wendling
3574c2d849 Fix this test. Don't null out the file, just XFAIL it until patch can be fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55296 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-24 21:48:46 +00:00
Bill Wendling
59b63e4a18 Temporarily reverting r55292. It's causing a bootstraping failure: 
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc ... src/libiberty/make-temp-file.c -o make-temp-file.o
Assertion failed: (Node2Index[SU->NodeNum] > Node2Index[I->Dep->NodeNum] && "Wrong topological sorting"), function InitDAGTopologicalSorting, file /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp, line 508.
../../../../llvm-gcc.src/libiberty/hashtab.c:955: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter> for instructions.
make[4]: *** [hashtab.o] Error 1
make[4]: *** Waiting for unfinished jobs....
make[3]: *** [multi-do] Error 1
make[2]: *** [all] Error 2
make[1]: *** [all-target-libiberty] Error 2
make: *** [all] Error 2



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55295 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-24 21:45:30 +00:00
Evan Cheng
32c727cd95 Move callseq_start above the call address load to allow load to be folded into the call node. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55292 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-24 19:19:55 +00:00
Anton Korobeynikov
8ff7ce3dd2 Testcase for 64bit maskmovq 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55239 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-23 15:53:47 +00:00
Dale Johannesen
169b5ed46e Test all currently supported atomic builtins on x86-{32,64}. 
These just test that they go through the BE.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55208 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-22 22:39:21 +00:00
Dan Gohman
22bb31103d Factor out the predicate check code from DAGISelEmitter.cpp 
and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55156 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-22 00:20:26 +00:00
Bill Wendling
403483c200 Testcase for PR2585. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55151 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-21 23:04:49 +00:00
Dan Gohman
c67670b1ae Add -mattr=sse2 so this test doesn't fail on non-x86 hosts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55145 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-21 22:34:25 +00:00
Dale Johannesen
e2122a5e2e Make x86 and sse2 explicit for non-x86 hosts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55141 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-21 21:26:06 +00:00
Evan Cheng
1887c1c2f9 Fix a number of byval / memcpy / memset related codegen issues. 
1. x86-64 byval alignment should be max of 8 and alignment of type. Previously the code was not doing what the commit message was saying.
2. Do not use byte repeat move and store operations. These are slow.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55139 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-21 21:00:15 +00:00
Dan Gohman
5cc101ec89 getelementptr doesn't work on x86-64 yet, because it 
has MOV64ri32 and no plain MOV64ri.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55126 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-21 17:28:42 +00:00
Dan Gohman
7a0e6593d0 MVT::getMVT uses iPTR for pointer types, while we need the actual 
intptr_t type in this case. FastISel can now select simple
getelementptr instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55125 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-21 17:25:26 +00:00
Dan Gohman
d5fe57d2f9 Basic fast-isel support for instructions with constant int operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55099 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-21 01:41:07 +00:00
Dan Gohman
5c6aea9714 Add a -march line for this test, and run it on x86-64 too for fun. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55030 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-20 00:56:07 +00:00
Dan Gohman
8014e86580 Add FastISel support for floating-point operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55021 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-20 00:23:20 +00:00
Dan Gohman
bdedd44773 Add FastISel support for several more binary operators. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55020 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-20 00:11:48 +00:00
Bill Wendling
108ecf3975 Add support for the __sync_sub_and_fetch atomics and friends for X86. The code 
was already present, but not hooked up to anything.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55018 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-19 23:09:18 +00:00
Dan Gohman
d3aedf445c Fast-isel is now *minimally* functional. Add a testcase to 
demonstrate the extent of its capabilities. Note that it
only attempts to operate on one of the blocks in this
testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55016 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-19 22:37:59 +00:00
Dale Johannesen
140be2dfb7 Add support for 8 and 16 bit forms of __sync 
builtins on X86.

Change "lock" instructions to be on a separate line.
This is needed to work around a bug in the Darwin
assembler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54999 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-19 18:47:28 +00:00
Evan Cheng
0ac3fc2a61 Fix a (u)comiss intrinsic lowering bug. It was using anyext which can return junk in higher bits. Patch by Nate Begeman. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54903 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-17 19:22:34 +00:00
Dan Gohman
6ab6422f25 Allow SelectionDAG to create EXTRACT_VECTOR_ELT nodes with 
non-constant indices. Only a few of the peephole checks require
a constant index.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54764 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-13 21:51:37 +00:00
Dan Gohman
00f19b6542 Improve the grep commands for this test to be tolerant of ABI 
differences, and to be more specific.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54648 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-11 20:10:41 +00:00
Dan Gohman
8cea8ff34c Take the FrameOffset into account when computing the alignment 
of stack objects. This fixes PR2656.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54646 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-11 18:27:03 +00:00
Dan Gohman
d9ced09299 Add an EXTRACTPSmr pattern to match the pattern that 
X86ISelLowering creates.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54544 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-08 18:30:21 +00:00
Dan Gohman
e3d920699c Re-enable elimination of unnecessary SUBREG_TO_REG instructions in 
LowerSubregs, and fix an x86-64 isel bug that this exposed.

SUBREG_TO_REG for x86-64 implicit zero extension is only safe for
isel to generate when the source is known to always have zeros in
the high 32 bits. The EXTRACT_SUBREG instruction does not clear
the high 32 bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54444 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-07 02:54:50 +00:00
Dan Gohman
865db4566e Add an extra example that shouldn't get an and instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54443 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-07 02:23:06 +00:00
Dan Gohman
8a1510d192 Re-introduce the 8-bit subreg zext-inreg patterns for x86-32, 
this time using MOV32to32_ and MOV16to16_. Thanks to Evan for
suggesting this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54418 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-06 18:27:21 +00:00
Evan Cheng
e9d5035838 Fix PR2620: Fix X86cmppd selection code so it expects operands to be v2f64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54376 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-05 22:19:15 +00:00
Evan Cheng
e3b8a48d32 Fix PR2596: out of bound reference. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54375 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-05 21:51:46 +00:00
Owen Anderson
b6634e9e27 Update the remaining tests not to use -disable-correct-folding, and remove two 
that couldn't be updated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54359 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-05 18:19:14 +00:00
Owen Anderson
551ddf718c One more -disable-correct-folding case removed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54358 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-05 18:08:56 +00:00
Owen Anderson
2a1f07ea6a Remove another -disable-correct-folding use. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54357 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-05 18:05:58 +00:00
Owen Anderson
d6db225800 Eliminate another use of -disable-correct-folding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54356 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-05 18:03:01 +00:00
Evan Cheng
068b4ff553 Fix PR2568: Fix bug that cause redudant kill marker after its live interval has been extended due to coalescing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54346 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-05 07:10:38 +00:00
Owen Anderson
2b85dc3544 Update these tests to work by disabling the new correct CFG generation. This flag should ONLY be used to for tests like these. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54334 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-04 23:55:29 +00:00
Dan Gohman
6f498b0a8e Fix SDISel lowering of PHI nodes to use ComputeValueVTs. 
This allows it to work correctly on aggregate values.
This fixes PR2623.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54331 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-04 23:42:46 +00:00
Dale Johannesen
3b4c45203e Make sse2 explicit, for non-x86 hosts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54251 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-31 20:16:33 +00:00
Dan Gohman
75dcf08243 Improve dagcombining for sext-loads and sext-in-reg nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54239 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-31 00:50:31 +00:00
Dan Gohman
1053502486 I missed this file in r54223. movzbl is now used instead 
of movzbw here.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54224 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-30 18:23:34 +00:00
Dan Gohman
11ba3b1af6 Reapply r54147 with a constraint to only use the 8-bit 
subreg form on x86-64, to avoid the problem with x86-32
having GPRs that don't have 8-bit subregs.

Also, change several 16-bit instructions to use 
equivalent 32-bit instructions. These have a smaller
encoding and avoid partial-register updates.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54223 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-30 18:09:17 +00:00
Mon P Wang
e3b3a7241c Added support for overloading intrinsics (atomics) based on pointers 
to different address spaces.  This alters the naming scheme for those
intrinsics, e.g., atomic.load.add.i32 => atomic.load.add.i32.p0i32


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54195 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-30 04:36:53 +00:00