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28528 Commits

Author SHA1 Message Date
Daniel Sanders
4134d06487 [mips] Fix emission of '.option pic0' for MIPS-IV.
Summary: This was a case of incorrect usage of hasMips64() vs isABI_N64()

Reviewers: matheusalmeida, dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3398

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206388 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-16 13:58:57 +00:00
Daniel Sanders
849ca451c8 [mips] Correct r206370 to account for non-Linux targets using the small data section.
This should fix the ninja-x64-msvc-RA-centos6 builder.

I suspect the check in MipsSubtarget.cpp is incorrect and is really trying to
check for a bare-metal target rather and anything other than linux. I'll
investigate this.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206385 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-16 12:29:08 +00:00
Tim Northover
1a44333f0e AArch64/ARM64: port across stub handling for ELF C++ exceptions.
The most important part here is that we should actuall emit the stubs we refer
to in the exception table, but as a side issue this uses more sensible & GCC
compatible representations for some of the bits of information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206380 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-16 11:52:55 +00:00
Tim Northover
fef8e383eb ARM64: use 32-bit moves for constants where possible.
If we know that a particular 64-bit constant has all high bits zero, then we
can rely on the fact that 32-bit ARM64 instructions automatically zero out the
high bits of an x-register. This gives the expansion logic less constraints to
satisfy and so sometimes allows it to pick better sequences.

Came up while porting test/CodeGen/AArch64/movw-consts.ll: this will allow a
32-bit MOVN to be used in @test8 soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206379 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-16 11:52:51 +00:00
Tim Northover
ea9988a812 ARM64: use the integrated assembler on ELF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206378 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-16 11:52:40 +00:00
Matheus Almeida
8e0f5768a6 [mips] Emit '.set nomicromips' before a function's entry label
if not in micromips mode.

The test (elf_st_other.ll) was renamed as the name and description didn't
make sense as the test wasn't checking any symbol table entry.

Differential Revision: http://reviews.llvm.org/D3346



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206377 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-16 11:46:59 +00:00
Aaron Ballman
0af5a4e528 Fixing a compile error in debug versions of MSVC. It seems that the range-based for loop is confused by the DEBUG macro expansion unless a compound statement is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206376 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-16 11:15:57 +00:00
Daniel Sanders
b78eac2d4d [mips] Correct callee saved list for the N32 ABI and enable test
Summary: Depends on D3339

Reviewers: matheusalmeida, vmedic

Reviewed By: matheusalmeida

Differential Revision: http://reviews.llvm.org/D3340

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206371 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-16 10:23:37 +00:00
Tim Northover
be50dc8b1f ARM64: mark x7 as used when an i128 gets shunted onto the stack.
The second half of a split i128 was ending up in x7, which is not a good thing.

This is another part of PR19432.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206366 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-16 09:03:25 +00:00
Craig Topper
5422dfb5b0 Convert SelectionDAG::getVTList to use ArrayRef
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206357 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-16 06:10:51 +00:00
Saleem Abdulrasool
eb0eb5dbec Target: whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206353 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-16 04:15:25 +00:00
Matt Arsenault
ff8d7fb136 R600: Expand sign extension of vectors.
Setting vector types to expand will result in scalarization on pre SI hw,
as those gpus don't have vector shifts either.
Expand also i32 vectors, this helps llvm make the correct decision
about scalarizing the vector ops.

v2: move setOperation() calls to R600ISelLowering.cpp.
    cleanup the SI code to make it obvious that this patch does is nop for SI

Patch by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206348 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-16 01:41:30 +00:00
Jim Grosbach
ac261d9585 [ARM64,C++11] Tidy up branch relaxation a bit w/ c++11.
No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206344 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-16 00:42:46 +00:00
Jim Grosbach
e35b6d2695 ARM64: Nuke some dead code.
Missed in previous commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206343 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-16 00:42:43 +00:00
Jim Grosbach
09256c5bb5 [ARM64,C++11] Clean up the ARM64 LOH collection pass.
Range'ify a bunch of loops, mainly. As a result, we have a variety
of objects via reference rather than by pointer, so propogate that
through the various helper functions where it makes sense.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206337 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 22:57:02 +00:00
Matt Arsenault
d66d570796 R600/SI: Print code size along with used registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206336 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 22:40:47 +00:00
Matt Arsenault
bec5c611e1 R600/SI: Print more immediates in hex format
Print in decimal for inline immediates, and hex otherwise. Use hex
always for offsets in addressing offsets.

This approximately matches what the shader compiler does.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206335 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 22:32:49 +00:00
Matt Arsenault
dd368a8755 R600/SI: Cleanup parsing of register names.
Try to figure out the class and number of subregisters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206334 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 22:32:42 +00:00
Matt Arsenault
f8ea0352e0 R600/SI: Fix loads of i1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206330 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 22:28:39 +00:00
Andrea Di Biagio
749e8fee34 [X86] Improve the lowering of packed shifts by constant build_vector.
This patch teaches the backend how to efficiently lower logical and
arithmetic packed shifts on both SSE and AVX/AVX2 machines.

When possible, instead of scalarizing a vector shift, the backend should try
to expand the shift into a sequence of two packed shifts by immedate count
followed by a MOVSS/MOVSD.

Example
  (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))

Can be rewritten as:
  (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))

[with X and Y ConstantInt]

The advantage is that the two new shifts from the example would be lowered into
X86ISD::VSRLI nodes. This is always cheaper than scalarizing the vector into
four scalar shifts plus four pairs of vector insert/extract.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206316 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 19:30:48 +00:00
Quentin Colombet
49ad5d5dd5 [ARM64] Set default CPU to generic instead of cyclone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206313 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 19:08:46 +00:00
NAKAMURA Takumi
9bc7c0707d MipsAsmParser.cpp: Fix vg_leak in MipsOperand::CreateMem(). Mem.Base is managed by k_Memory itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206293 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 14:13:21 +00:00
NAKAMURA Takumi
9bf9a794df MipsAsmParser::ParseRegister(): Be responsible to delete an Operand on a temporary Operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206292 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 14:06:27 +00:00
Tim Northover
5f8234943d AArch64/ARM64: add missing pattern for extending load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206290 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 14:00:19 +00:00
Tim Northover
2a83cb71ad AArch64/ARM64: only mangle MOVZ/MOVN during encoding when needed
Sometimes we need emit the bits that would actually be a MOVN when producing a
relocated MOVZ instruction (don't ask). But not always, a check which ARM64 got
wrong until now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206289 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 14:00:15 +00:00
Tim Northover
5080ae2e21 AArch64/ARM64: add support for large code-model jump tables.
I've left the MachO CodeGen as it is, there's a reasonable chance it should use
the GOT like ConstPools, but I'm not certain.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206288 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 14:00:11 +00:00
Tim Northover
e9cae9b79f AArch64/ARM64: add patterns for various commutations of FNMADD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206287 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 14:00:06 +00:00
Tim Northover
e8bc8a7d58 AArch64/ARM64: add half as a storage type on ARM64.
This brings it into line with the AArch64 behaviour and should open the way for
certain OpenCL features.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206286 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 14:00:03 +00:00
Tim Northover
380fa65d5d AArch64/ARM64: copy patterns for fixed-point conversions
Code is mostly copied directly across, with a slight extension of the
ISelDAGToDAG function so that it can cope with the floating-point constants
being behind a litpool.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206285 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 13:59:57 +00:00
Tim Northover
1291807e03 ARM64: add constraints to various FastISel operations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206284 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 13:59:53 +00:00
Tim Northover
03eecdccff FastISel: constrain the RegClass of operands when emitting instructions.
ARM64 suffered multiple -verify-machineinstr failures (principally over the
xsp/xzr issue) because FastISel was completely ignoring which subset of the
general-purpose registers each instruction required.

More fixes are coming in ARM64 specific FastISel, but this should cover the
generic problems.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206283 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 13:59:49 +00:00
Tim Northover
3f2d713f4d AArch64/ARM64: add dp tests from AArch64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206281 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 13:59:40 +00:00
NAKAMURA Takumi
86a70cd2f5 ARM64AsmParser.cpp: Fix vg_leak in MC/ARM64/fp-encoding.s.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206279 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 13:22:11 +00:00
Stepan Dyatkovskiy
5fba9d3b5e Optional hash symbol feature support for ARM64
http://reviews.llvm.org/D3328



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206276 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 11:43:09 +00:00
Vladimir Medic
09a79dc1a0 Current definition of subtract with immediate instruction aliases uses CodeGenOnly defined instructions and post matcher expansion methods to emit real instructions add with immediate. However, they can directly alias add with immediate instruction and remove unnecessary definitions and code in MipsAsmParser.cpp. This patch makes no change in functionality, just removes unnecessary definitions and code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206272 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 10:14:49 +00:00
NAKAMURA Takumi
2727dbcc37 X86JITInfo: [x86] Rework r206240, X86CompilationCallback_SSE() should be called for SSE-enabled code generator, even if LLVM is not built with -msse.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206261 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 08:28:23 +00:00
Nick Lewycky
d63390cba1 Break PseudoSourceValue out of the Value hierarchy. It is now the root of its own tree containing FixedStackPseudoSourceValue (which you can use isa/dyn_cast on) and MipsCallEntry (which you can't). Anything that needs to use either a PseudoSourceValue* and Value* is strongly encouraged to use a MachinePointerInfo instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206255 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 07:22:52 +00:00
Lang Hames
508bd63046 [MC] Require an MCContext when constructing an MCDisassembler.
This patch re-introduces the MCContext member that was removed from
MCDisassembler in r206063, and requires that an MCContext be passed in at
MCDisassembler construction time. (Previously the MCContext member had been
initialized in an ad-hoc fashion after construction). The MCCContext member
can be used by MCDisassembler sub-classes to construct constant or
target-specific MCExprs.

This patch updates disassemblers for in-tree targets, and provides the
MCRegisterInfo instance that some disassemblers were using through the
MCContext (previously those backends were constructing their own
MCRegisterInfo instances).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206241 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 04:40:56 +00:00
NAKAMURA Takumi
88f353252d X86JITInfo: [x86] Use X86CompilationCallback_SSE() along;
*not* Subtarget->hasSSE1()
  *but* __SSE__, the flag that LLVM libraries are compiled

The callback calls internal LLVM JIT libraries. It may be built with -msse (or above).

FIXME: JIT may use "host" instead of "generic" by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206240 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 04:12:21 +00:00
Jim Grosbach
5a2d3f4c81 [ARM64,C++11]: Range'ify the dead-register-definition pass.
Range-based for loops. No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206239 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 02:14:09 +00:00
Quentin Colombet
b980d6301f [ARM64][MC] Set the default CPU string to generic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206228 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 00:28:39 +00:00
Jim Grosbach
fdf3f439eb X86: Nuke one more CPU autodetect blurb.
Missed one in r206094. This brings MC and TargetMachine back into sync.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206220 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-14 22:23:30 +00:00
David Blaikie
b85c7e569a Change argument order and add explanatory comment to r206130
Changes requested in code review by Eric Christopher of r206130.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206219 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-14 22:23:06 +00:00
Eric Christopher
7c34191683 Use FrameSetup on frame instructions for the Mips port.
I can't seem to get a testcase to show a difference here, but it's
part of the unconditional-br.ll line table weirdness.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206218 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-14 22:21:22 +00:00
Quentin Colombet
05620e5439 [ARM64][MC] Set the default CPU to cyclone when initilizating the MC layer.
This matches that ARM64Subtarget does for now.

This is related to <rdar://problem/16573920>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206211 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-14 21:25:53 +00:00
Louis Gerbarg
261f0df185 Fix for codegen bug that could cause illegal cmn instruction generation
In rare cases the dead definition elimination pass code can cause illegal cmn
instructions when it replaces dead registers on instructions that use
unmaterialized frame indexes. This patch disables the dead definition
optimization for instructions which include frame index operands.

rdar://16438284

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206208 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-14 21:05:05 +00:00
Louis Gerbarg
27539d46cc Add a flag to disable the ARM64DeadRegisterDefinitionsPass
This patch adds a -arm64-dead-def-elimination flag so that it is possible to
disable dead definition elimination. Includes test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206207 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-14 21:05:02 +00:00
James Molloy
b1138a1313 [ARM64] Port over missing subtarget features, and CPU definitions from AArch64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206198 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-14 17:38:00 +00:00
Daniel Sanders
6ede5d24b8 [mips] Fix fcopysign for MIPS-IV and add the test.
Summary:
This was another incorrect use of hasMips64() vs isGP64bit().

Depends on D3344

Reviewers: matheusalmeida, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3347

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206187 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-14 16:24:12 +00:00
Daniel Sanders
327be6483d [mips] Fix more incorrect uses of HasMips64 and isMips64()
Summary:
- Conditional moves acting on 64-bit GPR's should require MIPS-IV rather than MIPS64
- ISD::MUL, and ISD::MULH[US] should be lowered on all 64-bit ISA's

Patch by David Chisnall
His work was sponsored by: DARPA, AFRL

I've added additional testcases to cover as much of the codegen changes
affecting MIPS-IV as I can. Where I've been unable to find an existing
MIPS64 testcase that can be re-used for MIPS-IV (mainly tests covering
ISD::GlobalAddress and similar), I at least agree that MIPS-IV should
behave like MIPS64. Further testcases that are fixed by this patch will follow
in my next commit. The testcases from that commit that fail for MIPS-IV without
this patch are:
    LLVM :: CodeGen/Mips/2010-07-20-Switch.ll
    LLVM :: CodeGen/Mips/cmov.ll
    LLVM :: CodeGen/Mips/eh-dwarf-cfa.ll
    LLVM :: CodeGen/Mips/largeimmprinting.ll
    LLVM :: CodeGen/Mips/longbranch.ll
    LLVM :: CodeGen/Mips/mips64-f128.ll
    LLVM :: CodeGen/Mips/mips64directive.ll
    LLVM :: CodeGen/Mips/mips64ext.ll
    LLVM :: CodeGen/Mips/mips64fpldst.ll
    LLVM :: CodeGen/Mips/mips64intldst.ll
    LLVM :: CodeGen/Mips/mips64load-store-left-right.ll
    LLVM :: CodeGen/Mips/sint-fp-store_pattern.ll

Reviewers: dsanders

Reviewed By: dsanders

CC: matheusalmeida

Differential Revision: http://reviews.llvm.org/D3343

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206183 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-14 15:44:42 +00:00