Craig Topper
b511048cd0
Merge SSE and AVX instruction definitions for scalar forms of SQRT, RSQRT, and RCP.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171351 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-01 20:53:20 +00:00
Craig Topper
117e4d2e19
Remove unused argument from a multiclass.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171340 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-01 03:42:44 +00:00
Craig Topper
76f94fd361
Merge intrinsic instruction definitions for SSE and AVX versions of RCPPS and RSQRTPS.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171339 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-01 03:30:21 +00:00
Craig Topper
42ab0d75ab
Remove 2 unused multiclasses.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171338 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-01 02:02:45 +00:00
Craig Topper
5284f97632
Merge AVX/SSE instruction definitions for SQRTPS/PD, RSQRTPS, RCPPS. No funcitonal change intended.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171337 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-01 00:11:07 +00:00
Craig Topper
dd9ccdb050
Use packed instead of scalar itineraries for SSE1/2 SQRTPS/PD, RCPPS, and RSQRTPS. VEX-encoded forms already use packed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171336 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-31 23:49:05 +00:00
Bill Wendling
9d30e7208e
Remove the getAttributesAtIndex and getNumAttrs methods in favor of using the getAttrSomewhere predicate. This prevents the uses of 'Attribute' as a collection of attributes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171271 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-31 00:49:59 +00:00
Nuno Lopes
98281a2050
convert a bunch of callers from DataLayout::getIndexedOffset() to GEP::accumulateConstantOffset().
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The later API is nicer than the former, and is correct regarding wrap-around offsets (if anyone cares).
There are a few more places left with duplicated code, which I'll remove soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171259 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-30 16:25:48 +00:00
Bill Wendling
94e94b3506
Use the predicate methods off of AttributeSet instead of Attribute.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171257 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-30 13:50:49 +00:00
Bill Wendling
8b62abdd7b
Remove the Function::getRetAttributes method in favor of using the AttributeSet accessor method.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171256 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-30 13:01:51 +00:00
Bill Wendling
39cd0c8e47
Remove Function::getParamAttributes and use the AttributeSet accessor methods instead.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171255 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-30 12:45:13 +00:00
Bill Wendling
831737d329
Remove the Function::getFnAttributes method in favor of using the AttributeSet
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directly.
This is in preparation for removing the use of the 'Attribute' class as a
collection of attributes. That will shift to the AttributeSet class instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171253 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-30 10:32:01 +00:00
Bill Wendling
377660355c
s/hasAttribute/contains/g to be more consistent with other method names.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171252 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-30 09:17:46 +00:00
Craig Topper
22d8f0d685
Remove intrinsic specific instructions for (V)SQRTPS/PD. Instead lower to target-independent ISD nodes and use the existing patterns for those.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171237 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-29 18:18:20 +00:00
Craig Topper
6f57f39e4a
Merge similar functionality using a nested switch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171229 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-29 17:19:06 +00:00
Craig Topper
6d183e4007
Remove intrinsic specific instructions for SSE/SSE2/AVX floating point max/min instructions. Lower them to target specific nodes and use those patterns instead. This also allows them to be commuted if UnsafeFPMath is enabled.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171227 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-29 16:44:25 +00:00
Jakub Staszak
c20323a758
Simplify code, no functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171226 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-29 15:57:26 +00:00
Jakub Staszak
3c0307d760
Delete executive bit on ./lib/Target/Hexagon/HexagonAsmPrinter.h.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171225 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-29 15:23:06 +00:00
Nadav Rotem
ae34b4280e
CostModel: initial checkin for code that estimates the cost of special shuffles.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171180 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-28 08:19:03 +00:00
Nadav Rotem
40ef8b7548
wrap 80-col lines.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171179 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-28 07:28:43 +00:00
Nadav Rotem
0509db2738
AVX: Move the ZEXT/ANYEXT DAGCo optimizations to the lowering of these optimizations. The old test cases still cover all of these lowering/optimizations. The single change that we have is that now anyext does not need to zero a register, because it does not use the exact code path as the zero_extend.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171178 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-28 05:45:24 +00:00
Nadav Rotem
587fb1dd30
Reverse the 'if' condition and reduce the indentation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171172 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-27 23:08:05 +00:00
Craig Topper
cccccabd07
Merge basic_sse12_fp_binop_p_int and basic_sse12_fp_binop_p_y_int multiclasses.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171171 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-27 22:53:47 +00:00
Nadav Rotem
1a330af3b5
AVX/AVX2: Move the SEXT lowering code from a target specific DAGco to a lowering function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171170 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-27 22:47:16 +00:00
Craig Topper
d5fc507ff1
Merge basic_sse12_fp_binop_p and basic_sse12_fp_binop_p_y multiclasses.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171166 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-27 18:51:50 +00:00
Nadav Rotem
d6fb53adb1
On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
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register. In most cases we actually compare or select YMM-sized registers
and mixing the two types creates horrible code. This commit optimizes
some of the transition sequences.
PR14657.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171148 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-27 08:15:45 +00:00
Nadav Rotem
3c22a44400
AVX/AVX2: Move the code that lowers vector-trunc from a DAGCo-hook to custom lowering hook.
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The vector truncs were scalarized during LegalizeVectorOps, later vectorized again by some DAGCombine optimization
and finally, lowered by a dagcombing optimization. Now, they are properly lowered during LegalizeVectorOps.
No new testcase because the original testcases still work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171146 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-27 07:45:10 +00:00
Craig Topper
068aec586d
Add hasSideEffects=0 to some forms of ROUND, RCP, and RSQRT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171143 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-27 07:16:08 +00:00
Craig Topper
d0f28c0958
Move single letter 'P' prefix out of multiclass now that tablegen allows defm to start with #NAME. This makes instruction names more searchable again.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171141 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-27 06:34:54 +00:00
Craig Topper
87073aad8f
Add hasSideEffects=0 to some shift and rotate instructions. None of which are currently used by code generation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171137 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-27 03:35:44 +00:00
Craig Topper
766cbae4b1
Mark the divide instructions as hasSideEffects=0.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171136 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-27 03:01:18 +00:00
Craig Topper
0b9c5e268f
Add hasSideEffects=0 to CMP*rr_REV.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171130 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-27 02:08:46 +00:00
Craig Topper
5e6a86c7f0
Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171128 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-27 02:01:33 +00:00
Craig Topper
e9fd6ad567
Fix operands and encoding form for ARPL instruction. Register form had and reversed. Memory form writes memory, but was marked as MRMSrcMem.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171123 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 23:27:57 +00:00
Craig Topper
ee5b63cb52
Add hasSideEffects=0 to some atomic instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 23:08:12 +00:00
Craig Topper
b87a5b3a1f
Mark the AL/AX/EAX forms of the basic arithmetic operations has never having side effects.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171121 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 22:19:23 +00:00
Craig Topper
37cb8398c8
Mark all the _REV instructions as not having side effects. They aren't really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171118 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 21:30:22 +00:00
Craig Topper
a85cbfeba7
Remove a special conditional setting of neverHasSideEffects if the instruction didn't have a pattern. This was leftover from when tablegen used to complain if things were already inferred from patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171117 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 21:04:30 +00:00
Craig Topper
0a5ead92ff
Merge still more SSE/AVX instruction definitions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171103 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 07:54:43 +00:00
Craig Topper
07555fc640
Merge more SSE/AVX instruction definitions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171102 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 07:20:35 +00:00
Craig Topper
755841d9d7
Fix 80 column violation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171097 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 06:15:53 +00:00
Craig Topper
6f9d44e072
Fix class name in comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171096 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 06:15:09 +00:00
Craig Topper
219bc2db1f
Merge SSE/AVX PCMPEQ/PCMPGT instruction definitions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171095 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 06:14:15 +00:00
Craig Topper
02082efaab
Remove 'v' from mnemonic to fix asm matching failures.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171093 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 06:02:15 +00:00
Craig Topper
3cdc3827ce
Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for a bunch of SSE2 integer arithmetic instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171092 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 05:49:15 +00:00
Nadav Rotem
a05f7cbbde
Reformat the docs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171091 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 04:59:20 +00:00
Craig Topper
09a326d3f0
Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for PAND/POR/PXOR/PANDN
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171087 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 04:36:03 +00:00
Craig Topper
1fe132ae7d
Merge an AVX/SSE 256-bit and 128-bit multiclass.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171086 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 03:56:47 +00:00
Craig Topper
b5c590a586
Mark VANDNPD/VANDNPDS as not commutable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171085 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 03:48:10 +00:00
Craig Topper
174a3d3e63
Remove alignment from a bunch more VEX encoded operations in the folding tables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171082 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 02:44:47 +00:00
Craig Topper
d83a73adf0
Remove alignment from folding table for VMOVUPD as an unaligned instruction it shouldn't require alignment...
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171081 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 02:14:19 +00:00
Craig Topper
1ac0046fa8
Remove alignment requirements from (V)EXTRACTPS. This instruction does 32-bit stores which aren't required to be aligned on SSE or AVX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171080 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 01:47:12 +00:00
Craig Topper
0f77910e6f
Remove alignment requirement from VCVTSS2SD in folding tables. Reverting r171049. This instruction doesn't require alignment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171078 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26 00:35:47 +00:00
Hal Finkel
cd9ea51986
Expand PPC64 atomic load and store
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Use of store or load with the atomic specifier on 64-bit types would
cause instruction-selection failures. As with the 32-bit case, these
can use the default expansion in terms of cmp-and-swap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171072 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-25 17:22:53 +00:00
Benjamin Kramer
99f78061e0
X86: Shave off one shuffle from the pcmpeqq sequence for SSE2 by making use of and commutativity.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171064 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-25 13:09:08 +00:00
Benjamin Kramer
382ed78d3f
X86: Custom lower <2 x i64> eq and ne when SSE41 is not available.
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pcmpeqd, pshufd, pshufd, pand is cheaper than unpack + cmpq, sbbq, cmpq, sbbq + pack.
Small speedup on loop-vectorized viterbi (-march=core2).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171063 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-25 12:54:19 +00:00
Nadav Rotem
a4c8a32a9f
VCVTSS2SD requires a strict alignment. Thanks Elena.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171049 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-25 03:29:18 +00:00
Nick Lewycky
71f30bffcf
Quiet gcc's -Wparenthesis warning. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171044 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-24 19:58:45 +00:00
Benjamin Kramer
791dbb3e5f
Use a std::string rather than a dynamically allocated char* buffer.
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This affords us to use std::string's allocation routines and use the destructor
for the memory management. Switching to that also means that we can use
operator==(const std::string&, const char *) to perform the string comparison
rather than resorting to libc functionality (i.e. strcmp).
Patch by Saleem Abdulrasool!
Differential Revision: http://llvm-reviews.chandlerc.com/D230
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171042 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-24 19:23:30 +00:00
Nadav Rotem
1e1c5f37c3
CostModel: We have API for checking the costs of known shuffles. This patch adds
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support for the insert-subvector and extract-subvector kinds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171027 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-24 10:04:03 +00:00
Nadav Rotem
ace0c2fad7
Some x86 instructions can load/store one of the operands to memory. On SSE, this memory needs to be aligned.
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When these instructions are encoded in VEX (on AVX) there is no such requirement. This changes the folding
tables and removes the alignment restrictions from VEX-encoded instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171024 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-24 09:40:33 +00:00
Nadav Rotem
daf7b5c8f2
Change the codegen Cost Model API for shuffeles. This patch removes the API for broadcast and adds a more general API that accepts an enum of known shuffles.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171022 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-24 08:57:47 +00:00
Nadav Rotem
6f3d81a929
CostModel: Change the default target-independent implementation for finding
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the cost of arithmetic functions. We now assume that the cost of arithmetic
operations that are marked as Legal or Promote is low, but ops that are
marked as custom are higher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171002 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-23 17:31:23 +00:00
Nadav Rotem
40b04a481d
whitespace
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170997 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-23 07:33:44 +00:00
Nadav Rotem
677689cf5d
Rename a function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170996 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-23 07:30:09 +00:00
Nadav Rotem
d54fed2786
Loop Vectorizer: Update the cost model of scatter/gather operations and make
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them more expensive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170995 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-23 07:23:55 +00:00
Benjamin Kramer
2f8a6cdfa3
X86: Turn mul of <4 x i32> into pmuludq when no SSE4.1 is available.
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pmuludq is slow, but it turns out that all the unpacking and packing of the
scalarized mul is even slower. 10% speedup on loop-vectorized paq8p.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170985 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-22 16:07:56 +00:00
Benjamin Kramer
17347912b4
X86: Emit vector sext as shuffle + sra if vpmovsx is not available.
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Also loosen the SSSE3 dependency a bit, expanded pshufb + psra is still better
than scalarized loads. Fixes PR14590.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170984 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-22 11:34:28 +00:00
Nadav Rotem
d0696ef8c3
In some cases, due to scheduling constraints we copy the EFLAGS.
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The only way to read the eflags is using push and pop. If we don't
adjust the stack then we run over the first frame index. This is
not something that we want to do, so we have to make sure that
our machine function does not copy the flags. If it does then
we have to emit the prolog that adjusts the stack.
rdar://12896831
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170961 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 23:48:49 +00:00
Akira Hatanaka
dbf51ee459
[mips] Refactor subword-swap, EXT/INS, load-effective-address and read-hardware
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instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170956 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 23:21:32 +00:00
Akira Hatanaka
e8bc10b902
[mips] Refactor SYNC and multiply/divide instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170955 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 23:17:36 +00:00
Akira Hatanaka
aa7c9cd181
[mips] Refactor BAL instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170954 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 23:15:59 +00:00
Akira Hatanaka
1892253694
[mips] Fix encoding of BAL instruction. Also, fix assembler test case which
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was not catching the error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170953 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 23:13:59 +00:00
Akira Hatanaka
6a8309e62a
[mips] Refactor jump, jump register, jump-and-link and nop instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170952 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 23:03:50 +00:00
Akira Hatanaka
0a57dc1d14
[mips] Refactor load/store left/right and load-link and store-conditional
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instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170950 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 23:01:24 +00:00
Akira Hatanaka
16164657d8
[mips] Refactor load/store instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170948 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 22:58:55 +00:00
Akira Hatanaka
5f5770baae
[mips] Remove unnecessary isPseudo parameter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170947 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 22:57:26 +00:00
Akira Hatanaka
8e719fac46
[mips] Refactor LUI instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170944 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 22:46:07 +00:00
Akira Hatanaka
35242e27c5
[mips] Refactor count leading zero or one instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170942 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 22:43:58 +00:00
Akira Hatanaka
8aaed99a99
[mips] Refactor sign-extension-in-register instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170940 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 22:41:52 +00:00
Akira Hatanaka
7de001b97e
[mips] Refactor instructions which copy from and to HI/LO registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170939 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 22:39:17 +00:00
Akira Hatanaka
2a732ec272
[mips] Refactor logical NOR instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170937 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 22:35:47 +00:00
Akira Hatanaka
a8215f4ec2
[mips] Move instruction definitions in MipsInstrInfo.td.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170936 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 22:33:43 +00:00
Tom Stellard
b06c540f9f
R600: Coding style - remove empty spaces from the beginning of functions
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No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170923 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 20:12:02 +00:00
Tom Stellard
eef0d5a0d6
R600: Fix MAX_UINT definition
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Patch by: Vadim Girlin
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170922 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 20:12:01 +00:00
Tom Stellard
fe13e70f6f
R600: Add SHADOWCUBE to TEX_SHADOW pattern
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Patch by: Vadim Girlin
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170921 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 20:11:59 +00:00
Benjamin Kramer
4e23ebe766
Cleanup compiler warnings on discarding type qualifiers in casts. Switch to C++ style casts.
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Patch by Saleem Abdulrasool!
Differential Revision: http://llvm-reviews.chandlerc.com/D204
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170917 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 19:09:53 +00:00
Benjamin Kramer
2556c6b4b6
X86: Match pmin/pmax as a target specific dag combine. This occurs during vectorization.
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Part of PR14667.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170908 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 17:46:58 +00:00
Roman Divacky
38b06020db
Remove duplicate includes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 17:06:44 +00:00
Tom Stellard
519b456fe1
R600: Expand vec4 INT <-> FP conversions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170901 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 16:33:24 +00:00
Benjamin Kramer
739c7a83e1
X86: Match the SSE/AVX min/max vector ops using a custom node instead of intrinsics
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This is very mechanical, no functionality change. Preparation for PR14667.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 14:04:55 +00:00
Nadav Rotem
042a9a2666
Add a missing "virtual" keyword.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170842 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 05:02:12 +00:00
Quentin Colombet
e0f1d712f6
Add ARM cortex-r5 subtarget.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170840 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 04:35:05 +00:00
Nadav Rotem
f5637c3997
Improve the X86 cost model for loads and stores.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170830 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 01:33:59 +00:00
Nadav Rotem
c2a537bd08
BB-Vectorizer: Check the cost of the store pointer type
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and not the return type, which is void. A number of test
cases fail after adding the assertion in TTImpl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170828 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 01:24:36 +00:00
Reed Kotler
a40ba2b3b2
Call llvm_unreachable instead of assert.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170822 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21 00:44:59 +00:00
Jakob Stoklund Olesen
be06aacaa9
Add an MF argument to MI::copyImplicitOps().
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This function is often used to decorate dangling instructions, so a
context reference is required to allocate memory for the operands.
Also add a corresponding MachineInstrBuilder method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170797 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 22:54:02 +00:00
Jakob Stoklund Olesen
b9efafe54d
MachineInstrBuilderize ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170795 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 22:53:55 +00:00
Jakob Stoklund Olesen
28d53a26cc
MachineInstrBuilderize NVPTX.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170794 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 22:53:53 +00:00
Bob Wilson
103b4a571e
Revert "Adding support for llvm.arm.neon.vaddl[su].* and"
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This reverts r170694. The operations can be represented in IR without
adding any new intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170765 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 21:09:38 +00:00