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Author SHA1 Message Date
Elena Demikhovsky da0ce6eb8b AVX-512: updated the list of high-latency instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189740 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-02 07:41:01 +00:00
Elena Demikhovsky cafcc99857 AVX-512: gather-scatter tests; added foldable instructions; 
Specify GATHER/SCATTER as heavy instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189736 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-02 07:12:29 +00:00
Elena Demikhovsky 4ca0ce2594 llvm interpreter: select, shuffle and insertelement instructions. 
This patch implements vector support for  select instruction and adds specific vector instructions : shuffle and insertelement. (tests are also included)
and functions lle_X_memset, lle_X_memcpy added.

Done by Veselov, Yuri (mailto:Yuri.Veselov@intel.com)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189735 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-02 06:40:09 +00:00
Elena Demikhovsky 6adcd58d3c AVX-512: Added GATHER and SCATTER instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189729 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-01 14:24:41 +00:00
Elena Demikhovsky 4edfa2278a AVX-512: added extend and truncate instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189580 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-29 11:56:53 +00:00
Elena Demikhovsky 2fb982aa72 AVX-512: added SQRT, VRSQRT14, VCOMISS, VUCOMISS, VRCP14, VPABS 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189472 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-28 11:21:58 +00:00
Elena Demikhovsky d371d4f0f4 AVX-512: added conversion instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189349 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-27 13:54:04 +00:00
Elena Demikhovsky 1567abe74f AVX-512: Added FMA instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189326 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-27 08:39:25 +00:00
Elena Demikhovsky 92bfb54770 AVX-512: Added shuffle instructions - 
VPSHUFD, VPERMILPS, VMOVDDUP, VMOVLHPS, VMOVHLPS, VSHUFPS, VALIGN
 single and double forms.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189215 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-26 12:45:35 +00:00
Elena Demikhovsky 41f7baf181 AVX-512: added UNPACK instructions and tests for all-zero/all-ones vectors 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189189 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-25 12:54:30 +00:00
Elena Demikhovsky 1765e74c15 AVX-512: Added masked SHIFT commands, more encoding tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189005 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-22 12:18:28 +00:00
Elena Demikhovsky 8ba76daba0 AVX-512: Added SHIFT instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188899 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-21 09:36:02 +00:00
Elena Demikhovsky 38cd21a3e9 AVX-512: Added more patterns for VMOVSS, VMOVSD, VMOVD, VMOVQ 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188786 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-20 11:00:29 +00:00
Elena Demikhovsky f12df0ad50 AVX-512: added arithmetic and logical operations. 
ADD, SUB, MUL integer and FP types. OR, AND, XOR.
Added embeded broadcast form for these instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188673 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-19 13:26:14 +00:00
Elena Demikhovsky c892bd6a74 AVX-512: compiler intrinsics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188654 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-19 06:55:01 +00:00
Elena Demikhovsky 3491d67d3a AVX-512: Added VMOVD, VMOVQ, VMOVSS, VMOVSD instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188637 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-18 13:08:57 +00:00
Elena Demikhovsky 4d36bd80e6 AVX-512: Added CMP and BLEND instructions. 
Lowering for SETCC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188265 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-13 13:24:07 +00:00
Elena Demikhovsky 55db69c97e AVX-512: Added more tests for BROADCAST 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188148 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-11 12:29:16 +00:00
Elena Demikhovsky fac4a4eb7d AVX-512: Added VPERM* instructons and MOV* zmm-to-zmm instructions. 
Added a test for shuffles using VPERM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188147 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-11 07:55:09 +00:00
Elena Demikhovsky 207600d2cf AVX-512 set: Added BROADCAST instructions 
with lowering logic and a test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187884 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-07 12:34:55 +00:00
Elena Demikhovsky aefdc04b2b LLVM Interpreter: MIPS tests should pass 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187867 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-07 06:13:21 +00:00
Elena Demikhovsky 7398c774f6 LLVM Interpreter: fixed bug 16694 
fix for: Bug 16694 - ExecutionEngine/test-interp-vec-loadstore.ll failing on powerpc-darwin8 (http://llvm.org/bugs/show_bug.cgi?id=16694)
The ExecutionEngine/test-interp-vec-loadstore.ll test has been failing on powerpc-darwin8 (on other platforms it passed)

the reason of fail was wrong output by printf. this output is checked by FileCheck, but on little-endian powerpc the output numeric data were printed inside out and FileCheck reported fail.
the printfs have been replaced by checking data inside test and numeric output has been replaced by the text output like : "int test passed, float test passed". The text output is checked by FileCheck.
the dependency on data layout has been removed.

done by Yuri Veselov (Intel)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187791 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-06 10:40:45 +00:00
Elena Demikhovsky cf21d155ed LLVM Interpreter: This patch implements vector support for cast operations (zext, sext, uitofp, sitofp, trunc, fpext, fptosi, fptrunc, bitcast) and shift operations (shl, ashr, lshr) for integer and floating point data types. 
Added tests.

Done by Yuri Veselov (mailto:Yuri.Veselov@intel.com).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187724 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-05 12:17:06 +00:00
Elena Demikhovsky 13e6e9171f AVX-512 set: added mask operations, lowering BUILD_VECTOR for i1 vector types. 
Added intrinsics and tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187717 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-05 08:52:21 +00:00
Elena Demikhovsky f3e3417e65 AVX-512 set: added VEXTRACTPS instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187705 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-04 10:46:07 +00:00
Elena Demikhovsky 0780179d53 EVEX and compressed displacement encoding for AVX512 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187576 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-01 13:34:06 +00:00
Elena Demikhovsky 093043ce11 Fixed assertion in Extract128BitVector() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187493 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-31 12:03:08 +00:00
Elena Demikhovsky 8395251c0a Added INSERT and EXTRACT intructions from AVX-512 ISA. 
All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms.
Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors.
Added lowering for EXTRACT/INSERT subvector for 512-bit vectors.
Added a test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187491 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-31 11:35:14 +00:00
Elena Demikhovsky dc8a318f44 fixed compilation issue 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187325 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-28 08:45:12 +00:00
Elena Demikhovsky c18f4efc5d Added encoding prefixes for KNL instructions (EVEX). 
Added 512-bit operands printing.
Added instruction formats for KNL instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187324 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-28 08:28:38 +00:00
Elena Demikhovsky e3809eed34 I'm starting to commit KNL backend. I'll push patches one-by-one. This patch includes support for the extended register set XMM16-31, YMM16-31, ZMM0-31. 
The full ISA you can see here: http://software.intel.com/en-us/intel-isa-extensions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187030 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-24 11:02:47 +00:00
Elena Demikhovsky e5cb25f860 Fixed alignment of code sections in the JIT mode. Added a test to the JITMemoryManager. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185421 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-02 12:24:22 +00:00
Elena Demikhovsky d8026708ef Fixed a comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184933 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-26 12:15:53 +00:00
Elena Demikhovsky 87070fe107 Optimized integer vector multiplication operation by replacing it with shift/xor/sub when it is possible. Fixed a bug in SDIV, where the const operand is not a splat constant vector. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184931 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-26 10:55:03 +00:00
Elena Demikhovsky 40e071c1eb Removed PackedDouble domain from scalar instructions. Added more formats for the scalar stuff. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183626 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-09 07:37:10 +00:00
Elena Demikhovsky 0c61b6f7ff removed commented lines 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182377 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-21 13:27:44 +00:00
Elena Demikhovsky f8cd1ee516 Removed SSEPacked domain from all forms (AVX, SSE, signed, unsigned) scalar compare instructions, like COMISS, COMISD. 
No functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182371 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-21 12:04:22 +00:00
Elena Demikhovsky 52981c4b60 I optimized the following patterns: 
sext <4 x i1> to <4 x i64>
 sext <4 x i8> to <4 x i64>
 sext <4 x i16> to <4 x i64>
 
I'm running Combine on SIGN_EXTEND_IN_REG and revert SEXT patterns:
 (sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
 
 The sext_in_reg (v4i32 x) may be lowered to shl+sar operations.
 The "sar" does not exist on 64-bit operation, so lowering sext_in_reg (v4i64 x) has no vector solution.

I also added a cost of this operations to the AVX costs table.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175619 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-20 12:42:54 +00:00
Elena Demikhovsky 58842c4ba1 Moved line-info.ll to DebugInfo\X86 directory 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175150 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-14 09:07:34 +00:00
Elena Demikhovsky c8c82dc1cc The test failed on Windows. I've changed the platform to run to "x86_64-apple-darwin". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175146 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-14 08:23:08 +00:00
Elena Demikhovsky 60b3e18d67 Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure). 
Added a test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175144 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-14 08:20:26 +00:00
Elena Demikhovsky d29804f80d Prevent insertion of "vzeroupper" before call that preserves YMM registers, since a caller uses preserved registers across the call. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175043 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-13 08:02:04 +00:00
Elena Demikhovsky 6c327f92a5 Optimization for the following SIGN_EXTEND pairs: 
v8i8  -> v8i64, 
v8i8  -> v8i32, 
v4i8  -> v4i64, 
v4i16 -> v4i64 
for AVX and AVX2.

Bug 14865.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172708 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-17 09:59:53 +00:00
Elena Demikhovsky ab70320908 Simplified TRUNCATE operation that comes after SETCC. It is possible since SETCC result is 0 or -1. 
Added a test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171467 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-03 08:48:33 +00:00
Elena Demikhovsky 94d7ab7da4 Added 6 more value types: v32i1, v64i1, v32i16, v32i8, v64i8, v8f64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171026 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-24 10:03:57 +00:00
Elena Demikhovsky 4b254679e7 Removed "static" from "__jit_debug_descriptor" because "static" adds C++ mangling prefix to this symbol. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171025 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-24 09:42:27 +00:00
Elena Demikhovsky 4b977312c7 Optimized load + SIGN_EXTEND patterns in the X86 backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170506 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-19 07:50:20 +00:00
Elena Demikhovsky 226e0e6264 Simplified BLEND pattern matching for shuffles. 
Generate VPBLENDD for AVX2 and VPBLENDW for v16i16 type on AVX2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169366 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-05 09:24:57 +00:00
Elena Demikhovsky 8564dc67b5 I changed hasAVX() to hasFp256() and hasAVX2() to hasInt256() in X86IselLowering.cpp. 
The logic was not changed, only names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168875 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-29 12:44:59 +00:00
Elena Demikhovsky 4fe5405bdd Intel OCL built-ins calling conventions now support MacOS 32-bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168359 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-20 09:37:57 +00:00
Elena Demikhovsky c0cd72204d The test avx-intel-ocl.ll failed. I can't reproduce on any of my machines. I added -mcpu flag, may be it will fix the problem 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166669 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-10-25 08:38:42 +00:00
Elena Demikhovsky 3575222175 Special calling conventions for Intel OpenCL built-in library. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166566 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-10-24 14:46:16 +00:00
Elena Demikhovsky 8100d244ff The VPSHUFB 256-bit instruction may be generated when one of input vector is undefined or zeroinitializer. 
I've added the "zeroinitializer" case in this patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163506 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-10 12:13:11 +00:00
Elena Demikhovsky 4178946afb AVX2 optimization. 
Added generation of VPSHUB instruction for <32 x i8> vector shuffle when possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163312 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-06 12:42:01 +00:00
Elena Demikhovsky 3251020738 This patch optimizes shuffle instruction - generates 2 instructions instead of 4. 
Since this specific shuffle is widely used in many workloads we have ~10% performance on them.

shufflevector <8 x float> %A, <8 x float> %B, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>

vmovaps (%rdx), %ymm0
vshufps $8, %ymm0, %ymm0, %ymm0
vmovaps (%rcx), %ymm1
vshufps $8, %ymm0, %ymm1, %ymm1
vunpcklps       %ymm0, %ymm1, %ymm0

vmovaps (%rcx), %ymm0
vmovsldup       (%rdx), %ymm1
vblendps        $85, %ymm0, %ymm1, %ymm0


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163134 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-09-04 12:49:02 +00:00
Elena Demikhovsky 1503aba4a0 Added FMA functionality to X86 target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161110 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-01 12:06:00 +00:00
Elena Demikhovsky 8f40f7b867 Optimization of shuffle node that can fit to the register form of VBROADCAST instruction on AVX2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159504 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-01 06:12:26 +00:00
Elena Demikhovsky fcb0946833 Removed unused variable 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159197 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-26 10:50:07 +00:00
Elena Demikhovsky 1596373671 Shuffle optimization for AVX/AVX2. 
The current patch optimizes frequently used shuffle patterns and gives these instruction sequence reduction.
Before:
      vshufps $-35, %xmm1, %xmm0, %xmm2 ## xmm2 = xmm0[1,3],xmm1[1,3]
       vpermilps       $-40, %xmm2, %xmm2 ## xmm2 = xmm2[0,2,1,3]
       vextractf128    $1, %ymm1, %xmm1
       vextractf128    $1, %ymm0, %xmm0
       vshufps $-35, %xmm1, %xmm0, %xmm0 ## xmm0 = xmm0[1,3],xmm1[1,3]
       vpermilps       $-40, %xmm0, %xmm0 ## xmm0 = xmm0[0,2,1,3]
       vinsertf128     $1, %xmm0, %ymm2, %ymm0
After:
      vshufps $13, %ymm0, %ymm1, %ymm1 ## ymm1 = ymm1[1,3],ymm0[0,0],ymm1[5,7],ymm0[4,4]
      vshufps $13, %ymm0, %ymm0, %ymm0 ## ymm0 = ymm0[1,3,0,0,5,7,4,4]
      vunpcklps       %ymm1, %ymm0, %ymm0 ## ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159188 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-26 08:04:10 +00:00
Elena Demikhovsky 177cf1e1a3 Added FMA3 Intel instructions. 
I disabled FMA3 autodetection, since the result may differ from expected for some benchmarks.
I added tests for GodeGen and intrinsics.
I did not change llvm.fma.f32/64 - it may be done later.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157737 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-31 09:20:20 +00:00
Elena Demikhovsky dd9047815c cleaned line endings in the newly added test file 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155315 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-22 13:22:48 +00:00
Elena Demikhovsky 1da5867236 ZERO_EXTEND/SIGN_EXTEND/TRUNCATE optimization for AVX2 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155309 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-22 09:39:03 +00:00
Elena Demikhovsky 73c504af9d Added VPERM optimization for AVX2 shuffles 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154761 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-15 11:18:59 +00:00
Elena Demikhovsky f602040c49 Fixed a bug in printing "cmp" pseudo ops. 
> This IR code
> %res = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 14)
> fails with assertion:
>
> llc: X86ATTInstPrinter.cpp:62: void llvm::X86ATTInstPrinter::printSSECC(const llvm::MCInst*, unsigned int, llvm::raw_ostream&): Assertion `0 && "Invalid ssecc argument!"' failed.
> 0  llc             0x0000000001355803
> 1  llc             0x0000000001355dc9
> 2  libpthread.so.0 0x00007f79a30575d0
> 3  libc.so.6       0x00007f79a23a1945 gsignal + 53
> 4  libc.so.6       0x00007f79a23a2f21 abort + 385
> 5  libc.so.6       0x00007f79a239a810 __assert_fail + 240
> 6  llc             0x00000000011858d5 llvm::X86ATTInstPrinter::printSSECC(llvm::MCInst const*, unsigned int, llvm::raw_ostream&) + 119

I added the full testing for all possible pseudo-ops of cmp.
I extended X86AsmPrinter.cpp and X86IntelInstPrinter.cpp.

You'l also see lines alignments (unrelated to this fix) in X86IselLowering.cpp from my previous check-in.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150068 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-08 08:37:26 +00:00
Elena Demikhovsky 0f1ead47a0 Minor change in signature of the getZeroVector() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149601 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-02 09:20:18 +00:00
Elena Demikhovsky dcabc7bca9 Optimization for SIGN_EXTEND operation on AVX. 
Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32
extensions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149600 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-02 09:10:43 +00:00
Elena Demikhovsky 1766971769 Passing AVX 256-bit structures in Win64 was wrong. 
Fixed Win64 calling conventions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149494 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-01 10:46:14 +00:00
Elena Demikhovsky 732525758f Shortened code in shuffle masks 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149493 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-01 10:33:05 +00:00
Elena Demikhovsky 3ae98150e3 Optimization for "truncate" operation on AVX. 
Truncating v4i64 -> v4i32 and v8i32 -> v8i16 may be done with set of shuffles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149485 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-01 07:56:44 +00:00
Elena Demikhovsky 28d7e71a30 ZERO_EXTEND operation is optimized for AVX. 
v8i16 -> v8i32, v4i32 -> v4i64 - used vpunpck* instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148803 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-24 13:54:13 +00:00
Elena Demikhovsky 16db710898 Fixed a bug in LowerVECTOR_SHUFFLE caused assertion failure 
lc: X86ISelLowering.cpp:6480: llvm::SDValue llvm::X86TargetLowering::LowerVECTOR_SHUFFLE(llvm::SDValue, llvm::SelectionDAG&) const: Assertion `V1.getOpcode() != ISD::UNDEF&&  "Op 1 of shuffle should not be undef"' failed.
Added a test.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148044 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-12 20:33:10 +00:00
Elena Demikhovsky ce58a03587 Fixed a bug in SelectionDAG.cpp. 
The failure seen on win32, when i64 type is illegal.
It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR.

The failure message is:
llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed.

I added a special test that checks vector shuffle on win32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147445 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-03 11:59:04 +00:00
Elena Demikhovsky ac12855066 Fixed a bug in SelectionDAG.cpp. 
The failure seen on win32, when i64 type is illegal.
It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR.

The failure message is:
llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed.

I added a special test that checks vector shuffle on win32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147399 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-01-01 16:22:47 +00:00
Elena Demikhovsky 021c0a2ee7 Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR. 
Matching MOVLP mask for AVX (265-bit vectors) was wrong.
The failure was detected by conformance tests.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147308 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-28 08:14:01 +00:00
Elena Demikhovsky ba4f83b4e9 This is the second fix related to VZEXT_MOVL node. 
The failure that I see in the current version is:

LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14]
  0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13]
    0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12]
      0x18b9870: v4i64 = undef [ID=4]
      0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10]
        0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
      0x18b9970: i32 = Constant<0> [ID=3]
    0x18b9170: v2i64 = undef [ORD=1] [ID=1]
    0x18b9570: i32 = Constant<2> [ID=5]



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146975 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 13:34:28 +00:00
Elena Demikhovsky f68b214e2d Fixed vsqrt.ss intrinsic usage - order of input operands was wrong. 
Added a test.
Thanks Bruno for reviewing the patch.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145403 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-29 15:00:45 +00:00
Elena Demikhovsky 52a35a89e6 I added several lines in X86 code generator that allow to choose 
VSHUFPS/VSHUFPD instructions while lowering VECTOR_SHUFFLE node. I check a commuted VSHUFP mask.

The patch was reviewed by Bruno.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145099 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-23 10:23:16 +00:00