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4595 Commits

Author SHA1 Message Date
Evan Cheng
a6eb2562b6 Also recognize ARM v4t and v5e variants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133002 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-14 18:08:33 +00:00
Bruno Cardoso Lopes
9a767330f5 Add one more argument to the prefetch intrinsic to indicate whether it's a data 
or instruction cache access. Update the targets to match it and also teach
autoupgrade.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132976 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-14 04:58:37 +00:00
Jim Grosbach
f921c0fe34 Clean up a few 80 column violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132946 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-13 22:54:22 +00:00
Jim Grosbach
7980f61f5f Fix coordination for using R4 in Thumb1 as a scratch for SP restore. 
The logic for reserving R4 for use as a scratch needs to match that for
actually using it. Also, it's not necessary for immediate <=508, so adjust
the value checked.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132934 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-13 21:18:25 +00:00
Cameron Zwarich
a86686e643 Provide an ARMCCState subclass of CCState so that ARM clients will always set 
CallOrPrologue correctly and eliminate the existing setter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132856 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-10 20:59:24 +00:00
Cameron Zwarich
a2e979565b A CCState was being created without setting whether it is in the Call or Prologue state, 
causing an assertion failure downstream. This fixes <rdar://problem/9562908>.

This really seems like it should always be set at CCState creation time, so mistakes like
this can never happen. I'll take a look at doing that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132811 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-09 22:30:07 +00:00
Eric Christopher
471e422480 Add a parameter to CCState so that it can access the MachineFunction. 
No functional change.

Part of PR6965


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132763 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-08 23:55:35 +00:00
Andrew Trick
a1099f184d Fix for setjmp/longjmp exception handling on ARM. setjmp clobbers CPSR. 
rdar://problem/9556069


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132699 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-07 00:08:49 +00:00
Eric Christopher
cf714d44b8 Make the Uv constraint a memory operand. This doesn't solve the 
addressing mode problem mentioned in r132559.

Backend part of rdar://9037836 and part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132561 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-03 17:24:37 +00:00
Eli Friedman
d6412c940e Add ARM fast-isel support for materializing the address of a global in cases where the global uses an indirect symbol. 
rdar://9431157



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132522 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-03 01:13:19 +00:00
Eric Christopher
100c833416 Have LowerOperandForConstraint handle multiple character constraints. 
Part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132510 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 23:16:42 +00:00
Jakob Stoklund Olesen
4f3fb6d08b Flag unallocatable register classes instead of giving them empty 
allocation orders.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132509 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 23:07:24 +00:00
Tanya Lattner
201cfcd6de Fix encoding for VEXTdf. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132486 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 21:25:24 +00:00
Jakob Stoklund Olesen
fa226bccaa Use TRI::has{Sub,Super}ClassEq() where possible. 
No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132455 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 05:43:46 +00:00
Rafael Espindola
cde4ce411b Don't hardcode the %reg format in the streamer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132451 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 02:34:55 +00:00
Bruno Cardoso Lopes
895c1e2dee Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value 
must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132324 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-31 03:33:27 +00:00
Rafael Espindola
6e032942cf Use the dwarf->llvm mapping to print register names in the cfi 
directives.

Fixes PR9826.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132317 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-30 20:20:15 +00:00
John McCall
5f8fd54f08 On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume. 
This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).

Take 2, now with more basic competence.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132295 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-29 19:50:32 +00:00
John McCall
7eebab2a82 I didn't mean to commit these residues of a personal project. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132293 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-29 19:41:56 +00:00
John McCall
832a9d1a76 On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume. 
This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132291 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-29 19:39:04 +00:00
Cameron Zwarich
c152aa6c86 Fix ARM fast isel to correctly flag memory operands to stores. This fixes 
-verify-machineinstrs failures on several tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132268 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-28 20:34:49 +00:00
Bruno Cardoso Lopes
a0112d0c39 Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairs 
to load/store i64 values. Since there's no current support to explicitly
declare such restrictions, implement it by using specific hardcoded register
pairs during isel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132248 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-28 04:07:29 +00:00
Eric Christopher
fea51fc007 This actually starts at offset 0, not 1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132246 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-28 03:16:22 +00:00
Eric Christopher
3c14f24c9d Implement the 'M' output modifier for arm inline asm. This is fairly 
register allocation dependent and will occasionally break. WIP in the
register allocator to model paired/etc registers.

rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132242 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-28 01:40:44 +00:00
Cameron Zwarich
de64aaf6c8 Fix the remaining atomic intrinsics to use the right register classes on Thumb2, 
and add some basic tests for them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132235 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 23:54:00 +00:00
Bruno Cardoso Lopes
be64b39431 ARM asm parser wasn't able to parse a "mov" instruction while in Thumb 
mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode,
default to the Thumb 1 versions/encodings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132233 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 23:46:09 +00:00
Rafael Espindola
5b23b7fe31 Make size computation less brittle. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132222 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 22:05:41 +00:00
Evan Cheng
4abce0c90b Don't use movw / movt for iOS static codegen for now to workaround some tools issues. rdar://9514789 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132211 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 20:11:27 +00:00
Eli Friedman
a4d487fc1e Fix a silly mistake (which trips over an assertion) in r132099. rdar://9515076 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132194 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 18:02:04 +00:00
Eric Christopher
33281b2361 Make the branch encoding for tBcc more obvious that it's a 4-byte opcode 
followed by a conditional and imm8.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132179 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 03:50:53 +00:00
Eric Christopher
86bbcbf4b0 Fix comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132178 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 03:46:51 +00:00
Eric Christopher
32bfb2c513 Reorganize these slightly according to operand type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132128 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-26 18:22:26 +00:00
Cameron Zwarich
421b106872 Mark tBX as an indirect branch rather than a return. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132107 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-26 03:41:12 +00:00
Eli Friedman
76927d7303 Rewrite fast-isel integer cast handling to handle more cases, and to be simpler and more consistent. 
The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts).

rdar://9437928 .



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132099 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 23:49:02 +00:00
Cameron Zwarich
ad70f6d2b1 Convert tBX_CALL / tBXr9_CALL to actual pseudoinstructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132086 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 21:53:50 +00:00
Eric Christopher
7bb1c40549 Clean up comment a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132083 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 21:19:19 +00:00
Eric Christopher
8f89463894 Implement the 'm' modifier. Note that it only works for memory operands. 
Part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132081 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 20:51:58 +00:00
Eli Friedman
783c66414a Prepare ARMFastISel::SelectSIToFP for getRegForValue returning registers for i8 and i16 values. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132073 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 19:09:45 +00:00
Cameron Zwarich
da86a08284 Restore an accidentally removed comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132044 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 04:48:17 +00:00
Cameron Zwarich
8e9bace414 Move some code to a more logical place. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132043 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 04:45:29 +00:00
Cameron Zwarich
106acd4158 Make tTAILJMPr/tTAILJMPrND emit a tBX without a preceding MOV of PC to LR. This 
fixes <rdar://problem/9495913>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132042 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 04:45:27 +00:00
Cameron Zwarich
328634598f Change the order of tBX's operands so that the predicate operands come after the 
target register, matching BX. I filed this bug because I was confused at first:

PR10007 - ARM branch instructions have inconsistent predicate operand placement
<http://llvm.org/bugs/show_bug.cgi?id=10007>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132041 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 04:45:23 +00:00
Cameron Zwarich
8f161c3a95 Rename tBX_Rm to tBX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132040 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 04:45:20 +00:00
Cameron Zwarich
b36c1ae6d5 Rename the existing tBX/tBXr9 instructions to tBX_CALL/tBXr9_CALL to better 
reflect their actual meaning and match the ARM instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132039 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 04:45:14 +00:00
Bruno Cardoso Lopes
56926a3961 Fix PR9762 
Enable the parsing of the operand "cpsr_all" for the ARM msr instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132026 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-25 00:35:03 +00:00
Eric Christopher
4db7dec70b Implement the arm 'L' asm modifier. 
Part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132024 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-24 23:27:13 +00:00
Eric Christopher
e1739d598d Implement the immediate part of the 'B' modifier. 
Part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132023 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-24 23:15:43 +00:00
Eric Christopher
fef50062ea Add more unimplemented asm modifiers and some documentation of what they 
do.

Part of rdar://9119939.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132015 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-24 22:27:43 +00:00
Eric Christopher
0628d38085 Add support for the arm 'y' asm modifier. 
Fixes part of rdar://9444657


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132011 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-24 22:10:34 +00:00
Cameron Zwarich
d34d429401 Fix <rdar://problem/9476260> by having tail calls always generate 32-bit branches 
in Darwin Thumb2 code. Tail calls are already disabled on Thumb1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131894 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-23 01:57:17 +00:00