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329 Commits

Author SHA1 Message Date
Nate Begeman
354df0ae6d Remove some instructions we no longer generate 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22976 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-23 01:16:46 +00:00
Chris Lattner
1f24df6324 Remove some regs that are not used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22975 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-22 22:32:13 +00:00
Chris Lattner
45fcb8f410 Fix operand numbers by marking variable arity nodes as such and by fixing 
the operand lists of a few other nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22883 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 23:25:33 +00:00
Nate Begeman
394cd13ba3 Fix JIT encoding of ppc mfocrf instruction; the operands were reversed 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22707 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-08 20:04:52 +00:00
Nate Begeman
2497e6391f Support building non-PIC 
Remove the LoadHiAddr pseudo-instruction.
Optimization of stores to and loads from statics.
Force JIT to use new non-PIC codepaths.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22494 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-21 20:44:43 +00:00
Nate Begeman
adeb43ddf4 Generate mfocrf when targeting g5. Generate fsqrt/fsqrts when targetin g5. 
8-byte align doubles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22486 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-20 22:42:00 +00:00
Chris Lattner
fc87928ebb PPC "branch and link" instructions are branches in the PPC sense, but not 
in the LLVM code generator sense (they are calls).  Don't mark them as such,
which fixes the regressions on the ppc tester last night


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22065 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-05-15 20:11:44 +00:00
Chris Lattner
14522e31d9 switch over the rest of the formats that use RC to use isDOT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21352 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-19 05:21:30 +00:00
Chris Lattner
883059fb58 Convert the XForm instrs and XSForm instruction over to use isDOT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21351 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-19 05:15:18 +00:00
Chris Lattner
a611ab72ca convert over bform and iform instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21349 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-19 05:00:59 +00:00
Chris Lattner
57226fbc7b Convert over DForm and DSForm instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21348 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-19 04:59:28 +00:00
Chris Lattner
e19d0b1130 Convert XLForm and XForm instructions over to use PPC64 when appropriate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21347 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-19 04:51:30 +00:00
Chris Lattner
5035cef732 Convert XO XS and XFX forms to use isPPC64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21346 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-19 04:40:07 +00:00
Chris Lattner
0bdc6f1fd4 Turn PPC64 and VMX into classes that can be added to instructions instead of 
bits that must be passed up the inheritance hierarchy.  Convert MForm and AForm
instructions over


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21345 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-19 04:32:54 +00:00
Nate Begeman
16ac709c63 Change codegen for setcc to read the bit directly out of the condition 
register.  Added support in the .td file for the g5-specific variant
  of cr -> gpr moves that executes faster, but we currently don't
  generate it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21314 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-18 02:43:24 +00:00
Nate Begeman
7bfba7d5e3 Implement multi-way branches through logical ops on condition registers. 
This can generate considerably shorter code, reducing the size of crafty
by almost 1%.  Also fix the printing of mcrf.  The code is currently
disabled until it gets a bit more testing, but should work as-is.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21298 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-14 09:45:08 +00:00
Nate Begeman
ef7288c824 Add the necessary support to codegen condition register logical ops with 
register allocated condition registers.  Make sure that the printed
  output is gas compatible.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21295 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-14 03:20:38 +00:00
Nate Begeman
7af0248af4 Initial support for allocation condition registers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21246 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-12 07:04:16 +00:00
Nate Begeman
9f833d3085 Implement bitfield clears 
Implement divide by negative power of two


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21240 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-12 00:10:02 +00:00
Chris Lattner
5eef9f3bc9 ORo sets CR0 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21227 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-11 15:03:48 +00:00
Chris Lattner
6b4ea2cfa2 Revert the previous patch, which I didn't mean to check in. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21226 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-11 15:03:41 +00:00
Chris Lattner
26d4fdb968 Fix a minor bug (ORo didn't mark that it set CR0). 
Refactor how . instructions are handled.  In particular, instead of passing
the RC flag all the way up the inheritance hierarchy, just make a new tblgen
class 'DOT' which can be added to an instruction definition.

For example, instead of this:

-def AND  : XForm_6<31,  28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-let Defs = [CR0] in
-def ANDo : XForm_6<31,  28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-                   "and. $rA, $rS, $rB">;

We now have this:

+def AND  : XForm_6<31,  28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
                    "and $rA, $rS, $rB">;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21225 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-11 15:01:39 +00:00
Nate Begeman
c7bd4827cd Add recording variants of ISD::AND and ISD::OR. This kills almost 1000 
(1.5%) instructions in 186.crafty


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21222 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-11 06:34:10 +00:00
Nate Begeman
cd08e4cb7e Add rlwnm instruction for variable rotate 
Generate rotate left/right immediate
Generate code for brcondtwoway
Use new livein/liveout functionality


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21187 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-09 20:09:12 +00:00
Nate Begeman
815d6dac1e Add support for MULHS and MULHU nodes 
Have LegalizeDAG handle SREM and UREM for us
Codegen SDIV and UDIV by constant as a multiply by magic constant instead
of integer divide, which is very slow.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21104 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-06 00:25:27 +00:00
Nate Begeman
178bb34ee5 Add support for multiply-add, multiply-sub, and their negated versions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21089 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-04 23:01:51 +00:00
Nate Begeman
27eeb00a1a Set shift amount to Extend 
Implement ISD::FABS and ISD::FNEG nodes
Implement SHL_PARTS, SRL_PARTS, and SRA_PARTS
Generate PowerPC 'fneg', 'fabs', and 'fnabs' instructions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21018 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-02 05:59:34 +00:00
Nate Begeman
3316252034 Implement SetCC, fix ZERO_EXTEND_INREG 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20933 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-03-29 21:54:38 +00:00
Nate Begeman
ca12a2bd91 Remove fake instruction 'subc' (mnemonic for subfc). 
More pattern isel updates


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20902 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-03-28 22:28:37 +00:00
Chris Lattner
7a823bd01f Fix a problem where the PPC backend lost track of the fact that it had 
to save and restore the LR register on entry and exit of a leaf function
that needed to access globals or the constant pool.  This should hopefully
fix oscar from sending the PPC tester spinning out of control.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20197 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-02-15 20:26:49 +00:00
Chris Lattner
be686a8897 Factor out common .td file chunks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18982 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-12-16 16:31:57 +00:00
Chris Lattner
a1ab451392 Fix encoding of fneg instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18226 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-25 03:53:44 +00:00
Nate Begeman
3b78e3b6a9 Fix encoding of bctrl, and remove some unused instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18192 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-24 00:16:37 +00:00
Chris Lattner
6f407893e2 Fix encoding of blr and bctr 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18178 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-23 22:06:24 +00:00
Chris Lattner
943f45208c Fix encodings 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18164 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-23 19:23:18 +00:00
Chris Lattner
6540c6c344 LA is really addi. Be consistent with operand ordering to avoid confusing the code emitter 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18138 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-23 05:54:25 +00:00
Chris Lattner
dd99885da3 Comment out a couple of unused instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18135 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-22 23:07:01 +00:00
Misha Brukman
145a5a3746 Add BCTR and LWZU instruction opcodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17851 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-15 21:20:09 +00:00
Misha Brukman
40a55e1e29 Add BA, BL, and BLA opcodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17193 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-23 20:29:24 +00:00
Misha Brukman
da8d96d1a1 Fix the SPR field for MTLR, MFLR, MTCTR, and MFCTR instructions. 
The decimal value given in the manual (8 or 9) really needs to be multiplied by
a factor of 32 because of the group of 5 zero bits after the register code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17182 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-23 06:05:49 +00:00
Misha Brukman
15f74b3f4f The value of the XO field for MFLR and MFCTR is 339, not 399 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17181 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-23 05:38:55 +00:00
Nate Begeman
2d4c98d79b Finally fix one of the oldest FIXMEs in the PowerPC backend: correctly 
flag rotate left word immediate then mask insert (rlwimi) as a two-address
instruction, and update the ISel usage of the instruction accordingly.

This will allow us to properly schedule rlwimi, and use it to efficiently
codegen bitfield operations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17068 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-16 20:43:38 +00:00
Nate Begeman
b816f0298d Several fixes and enhancements to the PPC32 backend. 
1. Fix an illegal argument to getClassB when deciding whether or not to
   sign extend a byte load.

2. Initial addition of isLoad and isStore flags to the instruction .td file
   for eventual use in a scheduler.

3. Rewrite of how constants are handled in emitSimpleBinaryOperation so
   that we can emit the PowerPC shifted immediate instructions far more
   often.  This allows us to emit the following code:

int foo(int x) { return x | 0x00F0000; }

_foo:
.LBB_foo_0:     ; entry
        ; IMPLICIT_DEF
        oris r3, r3, 15
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16826 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-07 22:30:03 +00:00
Nate Begeman
a2de102a5b add optimized code sequences for setcc x, 0 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16478 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-22 04:40:25 +00:00
Nate Begeman
20136a21ba Add 64 bit divide instructions, and use them 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16198 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-06 18:46:59 +00:00
Nate Begeman
ed42853be1 All PPC instructions are now auto-printed 
32 and 64 bit AsmWriters unified
Darwin and AIX specific features of AsmWriter split out


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16163 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-04 05:00:00 +00:00
Nate Begeman
b7a8f2cdaa Convert remaining X-Form and Pseudo instructions over to asm writer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16142 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-02 08:13:00 +00:00
Nate Begeman
cc8bd9ca7c convert M and MD form instructions to generated asm writer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16121 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-31 02:28:08 +00:00
Nate Begeman
07aada8b0f Move yet more instructions over to being printed by the generated asm writer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16112 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-30 02:28:06 +00:00
Nate Begeman
6b3dc55ef8 Convert A-Form instructions to auto-generated asm writer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16107 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-29 22:45:13 +00:00
Nate Begeman
d332fd54f5 Improvements to int->float cast code for PPC-64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16105 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-29 22:02:43 +00:00
Nate Begeman
f2f0781a10 Implement the following missing functionality in the PPC backend: 
cast fp->bool
cast ulong->fp
algebraic right shift long by non-constant value
These changes tested across most of the test suite.  Fixes Regression/casts


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16081 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-29 08:19:32 +00:00
Nate Begeman
c3306120cc Move XForm instructions over to the auto-generated asm writer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15962 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-21 05:56:39 +00:00
Nate Begeman
b47321ba2b Implement code to convert SetCC into straight line code where appropriate. Add necessary instructions for this transformation to the .td file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15952 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-20 09:56:22 +00:00
Nate Begeman
81d265d692 Clean up floating point instruction selection. 
Change int->float cast code to put conversion constants in constant pool.
Shorten code sequence for constant pool fp loads.
Remove LOADLoDirect/LOADLoIndirect psuedo instructions and tweak asmwriter


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15913 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-19 05:20:54 +00:00
Chris Lattner
0ea3171fbf Convert all of the DForm_6* operations, which makes all of the Zimm16 users 
dead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15754 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-15 05:46:14 +00:00
Chris Lattner
97b2a2e389 Convert the DForm_4 over to the asmprintergen 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15751 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-15 05:20:16 +00:00
Chris Lattner
7bb424fafc Print mflr using the asmwriter generator 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15749 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-14 23:27:29 +00:00
Nate Begeman
b0b8b93e58 Add indexed forms of load doubleword and load word algebraic for 64 bit targets 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15743 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-14 22:12:20 +00:00
Nate Begeman
244e64ead2 Add some more 64 bit instructions we need for the PowerPC-64 ISel to the tablegen files 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15710 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-13 02:19:26 +00:00
Misha Brukman
55eee3dc7a Fix names of 64-bit CMP*D* opcodes, add LWA and STD* opcodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15668 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-11 23:33:34 +00:00
Misha Brukman
f1f6cef161 Add support for 64-bit CMPDI, CMPLDI, and CMPLD opcodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15667 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-11 20:56:14 +00:00
Misha Brukman
96b6110685 Add doubleword load/store (64-bit only). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15665 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-11 15:54:36 +00:00
Nate Begeman
b64af918cb Fix casts of float to unsigned long 
Replace STDX (store 64 bit int indexed) with STFDX (store double indexed)
Fix latent bug in indexed load generation
Generate indexed loads and stores in many more cases


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15626 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-10 20:42:36 +00:00
Misha Brukman
4ad7d1bee7 Use instruction formats as defined in the PowerPC ISA manual 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15577 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-09 17:24:04 +00:00
Misha Brukman
68f3459994 Remove unused opcodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15447 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-03 20:23:44 +00:00
Misha Brukman
37dcae63eb * Use simpler instruction templates to define instructions 
* Fix several extended opcodes


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15423 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-02 21:58:52 +00:00
Misha Brukman
28791dd17f Separate instruction formats from instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15414 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-02 16:54:54 +00:00
Misha Brukman
8c02c1cbb8 Renamed files: 
* PowerPCReg.td => PowerPCRegisterinfo.td
* PowerPCInstrs.td => PowerPCInstrInfo.td


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15295 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-27 23:29:16 +00:00
Misha Brukman
f228fa0580 Add COND_BRANCH pseudo instruction, patch by Nate Begeman. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15283 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-27 18:35:54 +00:00
Misha Brukman
53f567817c MovePCtoLR (which is `bl' in disguise) modifies LR implicitly 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15272 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-27 17:15:05 +00:00
Misha Brukman
53d9a48855 Add SUBI instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15077 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-21 15:53:04 +00:00
Misha Brukman
86ddcf9d4f Differentiate between global and weak symbol loads 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15037 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-20 15:52:25 +00:00
Misha Brukman
2bf5438931 Add IMPLICIT_DEFS pseudo-instruction; patch by: Nate Begeman 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14895 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-07-16 20:33:41 +00:00
Misha Brukman
c661c3001c * Coalesce the handy CALL* alias opcodes with the standard ones 
* Congregate more branch-and-link opcodes together
* Mark FP, CPR, and special registers as volatile across calls


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14511 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-30 22:00:45 +00:00
Misha Brukman
5fa2b028b8 * Use LA instead of LWZ for LoadLoAddr 
* Specify the isCall bit and caller-save registers for some call instrs


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14501 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-29 23:37:36 +00:00
Misha Brukman
3905b57442 Fix the assembly opcode on LOADLoAddr, courtesy of Nate Begeman. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14470 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-28 18:27:08 +00:00
Misha Brukman
b2edb443e0 Set isBranch and isTerminator bits on all branch instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14469 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-28 18:23:35 +00:00
Misha Brukman
5dfe3a9c3b Initial revision 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14283 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-06-21 16:55:25 +00:00