Commit Graph

23971 Commits

Author SHA1 Message Date
Jim Grosbach
4fd4c91c40 ARM: Allocation hints must make sure to be in the alloc order.
When creating an allocation hint for a register pair, make sure the hint
for the physical register reference is still in the allocation order.

rdar://13240556

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175541 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 18:55:36 +00:00
Jyotsna Verma
383c6fc458 Hexagon: Sync TSFlags in MCTargetDesc/HexagonBaseInfo.h with
HexagonInstrFormats.td.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175537 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 18:18:36 +00:00
Benjamin Kramer
b1e1d5d4a5 Clean up HiPE prologue emission a bit and avoid signed arithmetic tricks.
No intended functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175536 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 17:32:57 +00:00
Rafael Espindola
e5a83d15b2 Move LLVM_LIBRARY_VISIBILITY for consistency with what was done to
PPCJITInfo.cpp in r175394.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175531 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 17:14:33 +00:00
Eli Bendersky
26a5c4dd31 Make ARMAsmPrinter pass name more precise and fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175527 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 16:47:59 +00:00
Eli Bendersky
faec9a3396 Make pass name more precise and fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175525 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 16:38:32 +00:00
Arnold Schwaighofer
2e750c12e9 ARM NEON: Merge a f32 bitcast of a v2i32 extractelt
A vectorized sitfp on doubles will get scalarized to a sequence of an
extract_element of <2 x i32>, a bitcast to f32 and a sitofp.
Due to the the extract_element, and the bitcast we will uneccessarily generate
moves between scalar and vector registers.

The patch fixes this by using a COPY_TO_REGCLASS and a EXTRACT_SUBREG to extract
the element from the vector instead.

radar://13191881

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175520 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 15:27:05 +00:00
Tom Stellard
e5839d0fc9 R600: Add AR_X to the R600_TReg_X register class.
NOTE: This is a candidate for the Mesa stable branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175519 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 15:22:47 +00:00
Tom Stellard
2b4b68d936 R600: Mark all members of the TRegMem register class as reserved
This stops the Machine Verifier from complaining about uses of undefined
physical registers.

NOTE: This is a candidate for the Mesa stable branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175518 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 15:22:45 +00:00
Tom Stellard
23339b68e2 R600: Fix scheduler crash caused by invalid MachinePointerInfo
Kernel function arguments are lowered to loads from the PARAM_I address
space.  When creating these load instructions, we were initializing
their MachinePointerInfo with an Arguement object that was not attached
to any function.  This was causing the MachineScheduler to crash when
it tried to access the parent of the Arguement.

This has been fixed by initializing the MachinePointerInfo with a
UndefValue instead.

NOTE: This is a candidate for the Mesa stable branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175517 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 15:22:44 +00:00
Tom Stellard
403554c658 R600: Fix tracking of implicit defs in the IndirectAddressing pass
In some cases, we were losing track of live implicit registers which
was creating dead defs and causing the scheduler to produce invalid
code.

NOTE: This is a candidate for the Mesa stable branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175516 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 15:22:42 +00:00
Craig Topper
ff3139fe53 Fix capitalization in comment to match function name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175497 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 07:43:59 +00:00
Reed Kotler
8a20844e27 Expand pseudos/macros BteqzT8SltiX16, BteqzT8SltiuX16,
BtnezT8SltiX16, BtnezT8SltiuX16 .



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175486 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 03:56:57 +00:00
Chandler Carruth
2878b7d7ab Remove some unused private fields from the AArch64MCCodeEmitter. These
fields were only ever set in the constructor. The create method retains
its consistent interface so that these bits can be re-threaded through
the emitter if they're ever needed.

This was found by the -Wunused-private-field Clang warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175482 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 02:08:14 +00:00
Reed Kotler
f801675207 Expand pseudos BteqzT8CmpiX16 and BtnezT8CmpiX16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175474 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-19 00:20:58 +00:00
Jakub Staszak
56f58ad0e4 Use array_pod_sort instead of std::sort.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175472 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 23:18:22 +00:00
NAKAMURA Takumi
9d7c53af30 X86FrameLowering.cpp: Fixup. Sorry for the breakage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175467 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 23:15:21 +00:00
David Blaikie
a39058aaed Use LLVM_DELETED_FUNCTION rather than '// do not implement' comments.
Also removes some redundant DNI comments on function declarations already
using the macro.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175466 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 23:11:17 +00:00
NAKAMURA Takumi
82f7815e6f X86FrameLowering.cpp: Fix a warning in -Asserts. [-Wunused-variable]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175464 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 23:08:49 +00:00
Chad Rosier
20ea2bc391 Remove a useless assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175463 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 22:20:16 +00:00
Chad Rosier
848c25ddfa [fast-isel] Remove an invalid assert.
If the memcpy has an odd length with an alignment of 2, this would incorrectly
assert on the last 1 byte copy.
rdar://13202135

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175459 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 21:46:28 +00:00
Benjamin Kramer
6228999d82 Fix a 32/64 bit incompatibility in the HiPE prologue generation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175458 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 21:45:01 +00:00
Benjamin Kramer
98fbe27ac8 Support for HiPE-compatible code emission, patch by Yiannis Tsiouris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175457 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 20:55:12 +00:00
Vincent Lejeune
e3111964a0 R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175446 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 14:11:28 +00:00
Vincent Lejeune
bbbef49118 R600: Support for TBO
NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175445 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 14:11:19 +00:00
Vincent Lejeune
628f6d5820 R600: Increase number of ArrayBase Reg to 32
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175443 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 13:48:09 +00:00
Reed Kotler
bb01b3cb93 Expand macro/pseudo instructions BtnezT8SltX16 and BtnezT8SltuX16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175420 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 05:43:03 +00:00
Reed Kotler
139748f1c1 Expand pseudo/macro BteqzT8SltuX16 . There is no test case because
at this time, llvm is generating a different but equivalent pattern
that would lead to this instruction. I am trying to think of a way
to get it to generate this. If I can't, I may just remove the pseudo.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175419 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 04:55:38 +00:00
Reed Kotler
dabfebb5c6 Expand pseudo/macro BteqzT8SltX16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175417 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 04:04:26 +00:00
Reed Kotler
a8601bb4ff Expand macro/pseudo BteqzT8CmpX16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175416 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 03:06:29 +00:00
Reed Kotler
da4afa72f7 Beginning of expanding all current mips16 macro/pseudo instruction sequences.
This expansion will be moved to expandISelPseudos as soon as I can figure
out how to do that. There are other instructions which use this 
ExpandFEXT_T8I816_ins and as soon as I have finished expanding them all,
I will delete the macro asm string text so it has no way to be used
in the future.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175413 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-18 00:59:04 +00:00
Benjamin Kramer
774ec7ba05 X86: Add a note.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175408 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17 23:34:14 +00:00
Richard Osborne
8dc741e400 [XCore] Add missing 2r instructions.
These instructions are not targeted by the compiler but it is needed for
the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175407 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17 22:38:05 +00:00
Richard Osborne
763c858ede [XCore] Add TSETR instruction.
This instruction is not targeted by the compiler but it is needed for the
MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17 22:32:41 +00:00
Richard Osborne
a970dde906 [XCore] Add missing u10 / lu10 instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175404 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17 20:44:48 +00:00
Richard Osborne
cbe6c88b68 [XCore] Add missing u6 / lu6 instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175403 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17 20:43:17 +00:00
Jakub Staszak
d61932bf84 Return false instead of 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175402 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17 18:35:25 +00:00
Benjamin Kramer
9831bf06e8 AArch64: Avoid shifts by 64, that's undefined behavior.
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175400 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17 17:55:32 +00:00
Benjamin Kramer
a79cbb1232 Make the visibility of LLVMPPCCompilationCallback work with GCC.
GCC warns about the attribute being ignored if it occurs after void*.
There seems to be some kind of incompatibility between clang and gcc here, but
I can't fathom who's right.

void* LLVM_LIBRARY_VISIBILITY foo(); // clang: hidden, gcc: default
LLVM_LIBRARY_VISIBILITY void *bar(); // clang: hidden, gcc: hidden
void LLVM_LIBRARY_VISIBILITY qux();  // clang: hidden, gcc: hidden

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175394 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-17 14:30:32 +00:00
Reed Kotler
5be5fa468a Clean up mips16 td file in preparation for massive pseudo lowering work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175379 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-16 23:39:52 +00:00
Renato Golin
b26f98fa1f Typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175371 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-16 19:14:59 +00:00
Reed Kotler
2de893210b One more try to make this look nice. I have lots of pseudo lowering
as well as 16/32 bit variants to do and so I want this to look nice
when I do it. I've been experimenting with this. No new test cases
are needed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175369 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-16 19:04:29 +00:00
NAKAMURA Takumi
3d6417d170 [msvc x64] Update X86CompilationCallback_Win64.asm corresponding to r175267.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175363 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-16 16:04:29 +00:00
NAKAMURA Takumi
c213366063 Target/R600/CMakeLists.txt: Prune SILowerLiteralConstants.cpp corresponding to r175354.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175361 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-16 15:30:28 +00:00
Jakub Staszak
30fcfc39e2 Minor cleanups. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175359 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-16 13:34:26 +00:00
Christian Konig
ecc571f063 R600/SI: Add pattern to simplify i64 loading
This is a candidate for the stable branch.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175356 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-16 11:28:36 +00:00
Christian Konig
e9ba1830df R600/SI: nuke SReg_1 v3
It's completely unnecessary and can be replace with proper
SReg_64 handling instead.

This actually fixes a piglit test on SI.

v2: use correct register class in addRegisterClass,
    set special classes as not allocatable
v3: revert setting special classes as not allocateable

This is a candidate for the stable branch.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175355 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-16 11:28:30 +00:00
Christian Konig
e25e490793 R600/SI: cleanup literal handling v3
Seems to be allot simpler, and also paves the
way for further improvements.

v2: rebased on master, use 0 in BUFFER_LOAD_FORMAT_XYZW,
    use VGPR0 in dummy EXP, avoid compiler warning, break
    after encoding the first literal.
v3: correctly use V_ADD_F32_e64

This is a candidate for the stable branch.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175354 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-16 11:28:22 +00:00
Christian Konig
8e4eebcecf R600/SI: replace AllReg_* with [SV]Src_* v2
Mark all the operands that can also have an immediate.

v2: SOFFSET is also an SSrc_32 operand

This is a candidate for the stable branch.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175353 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-16 11:28:13 +00:00
Christian Konig
305fefbb65 R600/SI: fix VOPC encoding v2
Previously it only worked because of coincident.

v2: fix 64bit versions, use 0x80 (inline 0) instead of SGPR0
    for the unused SRC2

This is a candidate for the stable branch.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175352 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-16 11:28:07 +00:00