Chris Lattner
a611ab72ca
convert over bform and iform instructions
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21349 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-19 05:00:59 +00:00
Chris Lattner
57226fbc7b
Convert over DForm and DSForm instructions
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21348 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-19 04:59:28 +00:00
Chris Lattner
e19d0b1130
Convert XLForm and XForm instructions over to use PPC64 when appropriate.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21347 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-19 04:51:30 +00:00
Chris Lattner
5035cef732
Convert XO XS and XFX forms to use isPPC64
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21346 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-19 04:40:07 +00:00
Chris Lattner
0bdc6f1fd4
Turn PPC64 and VMX into classes that can be added to instructions instead of
...
bits that must be passed up the inheritance hierarchy. Convert MForm and AForm
instructions over
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21345 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-19 04:32:54 +00:00
Nate Begeman
1cbf3abbb8
Next round of PPC CR optimizations. For the following code:
...
int %bar(float %a, float %b, float %c, float %d) {
entry:
%tmp.1 = setlt float %a, %d
%tmp.2 = setlt float %b, %d
%or = or bool %tmp.1, %tmp.2
%tmp.3 = setgt float %c, %d
%tmp.4 = or bool %or, %tmp.3
%tmp.5 = and bool %tmp.4, true
%retval = cast bool %tmp.5 to int
ret int %retval
}
We now emit:
_bar:
.LBB_bar_0: ; entry
fcmpu cr0, f1, f4
fcmpu cr1, f2, f4
cror 0, 0, 4
fcmpu cr1, f3, f4
cror 28, 0, 5
mfcr r2
rlwinm r3, r2, 29, 31, 31
blr
Instead of:
_bar:
.LBB_bar_0: ; entry
fcmpu cr7, f1, f4
mfcr r2
rlwinm r2, r2, 29, 31, 31
fcmpu cr7, f2, f4
mfcr r3
rlwinm r3, r3, 29, 31, 31
or r2, r2, r3
fcmpu cr7, f3, f4
mfcr r3
rlwinm r3, r3, 30, 31, 31
or r3, r2, r3
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21321 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-18 07:48:09 +00:00
Nate Begeman
16ac709c63
Change codegen for setcc to read the bit directly out of the condition
...
register. Added support in the .td file for the g5-specific variant
of cr -> gpr moves that executes faster, but we currently don't
generate it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21314 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-18 02:43:24 +00:00
Chris Lattner
477d1de9b2
Handle ExternalSymbol operands in the PPC JIT
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21312 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-18 00:46:10 +00:00
Nate Begeman
f8b02949e3
Make pattern isel default for ppc
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Add new ppc beta option related to using condition registers
Make pattern isel control flag (-enable-pattern-isel) global and tristate
0 == off
1 == on
2 == target default
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21309 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-15 22:12:16 +00:00
Nate Begeman
7bfba7d5e3
Implement multi-way branches through logical ops on condition registers.
...
This can generate considerably shorter code, reducing the size of crafty
by almost 1%. Also fix the printing of mcrf. The code is currently
disabled until it gets a bit more testing, but should work as-is.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21298 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-14 09:45:08 +00:00
Nate Begeman
ef7288c824
Add the necessary support to codegen condition register logical ops with
...
register allocated condition registers. Make sure that the printed
output is gas compatible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21295 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-14 03:20:38 +00:00
Nate Begeman
1b7f7fbf95
Start allocating condition registers. Almost all explicit uses of CR0 are
...
now gone. Next step is to get rid of the remaining ones and then start
allocating bools to CRs where appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21294 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-13 23:15:44 +00:00
Nate Begeman
3664ceffdd
Implement the fold shift X, zext(Y) -> shift X, Y at the target level,
...
where it is safe to do so.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21293 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-13 22:14:14 +00:00
Nate Begeman
eea805e74c
Disbale the broken fold of shift + sz[ext] for now
...
Move the transform for select (a < 0) ? b : 0 into the dag from ppc isel
Enable the dag to fold and (setcc, 1) -> setcc for targets where setcc
always produces zero or one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21291 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-13 21:23:31 +00:00
Chris Lattner
519f40ba4e
remove one more occurance of this that snuck in
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21271 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-13 02:46:17 +00:00
Chris Lattner
c951d87fe9
Elimate handling of ZERO_EXTEND_INREG. This causes the PPC backend to emit
...
andi instructions instead of rlwinm instructions for zero extend, but they
seem like they would take the same time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21268 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-13 02:40:26 +00:00
Nate Begeman
b882752bd0
Fold shift by size larger than type size to undef
...
Make llvm undef values generate ISD::UNDEF nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21261 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-12 23:12:17 +00:00
Nate Begeman
9765c25eb7
Implement setcc op, -1 sequences
...
Remove dead setcc op, 0 sequences
Coming later: generalization of op, imm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21260 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-12 21:22:28 +00:00
Nate Begeman
7af0248af4
Initial support for allocation condition registers
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21246 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-12 07:04:16 +00:00
Nate Begeman
9f833d3085
Implement bitfield clears
...
Implement divide by negative power of two
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21240 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-12 00:10:02 +00:00
Nate Begeman
ef9531efed
Update PPC readme. Remove things that are done or aren't ppc specific
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21232 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-11 20:48:57 +00:00
Chris Lattner
5eef9f3bc9
ORo sets CR0
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21227 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-11 15:03:48 +00:00
Chris Lattner
6b4ea2cfa2
Revert the previous patch, which I didn't mean to check in.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21226 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-11 15:03:41 +00:00
Chris Lattner
26d4fdb968
Fix a minor bug (ORo didn't mark that it set CR0).
...
Refactor how . instructions are handled. In particular, instead of passing
the RC flag all the way up the inheritance hierarchy, just make a new tblgen
class 'DOT' which can be added to an instruction definition.
For example, instead of this:
-def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-let Defs = [CR0] in
-def ANDo : XForm_6<31, 28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "and. $rA, $rS, $rB">;
We now have this:
+def AND : XForm_6<31, 28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"and $rA, $rS, $rB">;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21225 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-11 15:01:39 +00:00
Nate Begeman
c7bd4827cd
Add recording variants of ISD::AND and ISD::OR. This kills almost 1000
...
(1.5%) instructions in 186.crafty
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21222 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-11 06:34:10 +00:00
Nate Begeman
709c806a1e
Fix another fixme: factor out the constant fp generation code.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21207 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-10 06:06:10 +00:00
Nate Begeman
c5b1cd22b5
Fix 64 bit argument loading that straddles the args in regs / args on stack
...
boundary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21206 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-10 05:53:14 +00:00
Nate Begeman
340f290783
Remove unnecessary Implicit Defs. Since r0 is not in allocation, we do not
...
have to inform the register allocator it might be stepped on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21202 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-10 03:59:42 +00:00
Nate Begeman
27499e3f1b
Make sure that BRCOND branches can be converted into long branches too.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21198 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-10 01:48:29 +00:00
Nate Begeman
a0e3e9474f
Don't hand ISD::CALL nodes off to SelectExprFP. This fixes siod.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21197 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-10 01:14:13 +00:00
Chris Lattner
51d2ed976f
rename getPPCOpcodeForSetCCNumber -> getPPCOpcodeForSetCCOpode to be more
...
correct. Remove the EmitComparison retvalue, as it is always the first arg.
Fix a place where we incorrectly passed in the setcc opcode instead of the
setcc number, causing us to miscompile crafty. Crafty now works!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21195 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-10 01:03:31 +00:00
Nate Begeman
706471e291
fix ISD::BRCONDTWOWAY codegen to not deference the end() iterator
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21193 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-09 23:35:05 +00:00
Chris Lattner
9184bfbbf4
Fix CodeGen/Generic/2005-05-09-GlobalInPHI.ll, which was reduced from 254.gap.
...
This caused the "use before a def" assertion on some programs.
With this patch, 254.gap now passes with the PPC backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21191 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-09 22:05:17 +00:00
Chris Lattner
91277ea45c
do not set the root to null if an argument is dead
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21188 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-09 21:23:24 +00:00
Nate Begeman
cd08e4cb7e
Add rlwnm instruction for variable rotate
...
Generate rotate left/right immediate
Generate code for brcondtwoway
Use new livein/liveout functionality
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21187 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-09 20:09:12 +00:00
Chris Lattner
27ee3a332d
Fix a crash on 173.applu by asking for a constant bigger than 32-bits.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21185 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-09 19:47:21 +00:00
Chris Lattner
f429a3e0f6
Switch this instruction selector over to using liveins and liveouts, eliminating
...
implicit defs on entry to the function. yaay :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21184 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-09 16:32:30 +00:00
Nate Begeman
af4ab1b103
Optimize FSEL a bit for fneg arguments. This fixes the recently added test
...
case so that we emit
_test_fneg_sel:
.LBB_test_fneg_sel_0: ;
fsel f1, f1, f3, f2
blr
instead of:
_test_fneg_sel:
.LBB_test_fneg_sel_0: ;
fneg f0, f1
fneg f0, f0
fsel f1, f0, f3, f2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21177 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-09 09:33:07 +00:00
Chris Lattner
644db4ec5f
This target does not yet support ISD::BRCONDTWOWAY
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21163 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-09 03:22:30 +00:00
Nate Begeman
e88aa5b4d1
64b: Expand S/UREM
...
32b: No longer pattern match fneg(fsub(fmul)) as fnmsub
Pattern match fsub a, mul(b, c) as fnmsub
Pattern match fadd a, mul(b, c) as fmadd
Those changes speed up hydro2d by 2.5%, distray by 6%, and scimark by 8%
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21161 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-09 03:05:51 +00:00
Nate Begeman
a9532d5dde
Fix 64b shifts
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21159 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-08 23:45:01 +00:00
Nate Begeman
f3f2d6d378
Match Mac OS X 64 bit calling conventions
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21157 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-08 21:26:05 +00:00
Nate Begeman
7e7fadd2ea
Optimized code sequences for setcc reg, 0
...
Optimized code sequence for (a < 0) ? b : 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21150 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-07 20:30:01 +00:00
Chris Lattner
cbd06fc3d7
PowerPC zero extends setcc results
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21147 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-07 19:41:49 +00:00
Nate Begeman
7ddecb4186
Pattern match bitfield insert, which helps shift long by immediate, among
...
other things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21127 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-06 23:51:40 +00:00
Nate Begeman
020ef42c19
Fix some shift bugs
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21126 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-06 22:42:08 +00:00
Nate Begeman
27b4c23b80
Fixed version of optimized integer divide is now fixed. Calculate the
...
quotient, not the remainder. Also, make sure to remove the old div operand
from the ExprMap and let SelectExpr insert the new one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21111 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-06 06:44:57 +00:00
Nate Begeman
8f52980f03
Turn off the div -> mul optimization until it works correctly 100% of the
...
time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21105 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-06 03:36:33 +00:00
Nate Begeman
815d6dac1e
Add support for MULHS and MULHU nodes
...
Have LegalizeDAG handle SREM and UREM for us
Codegen SDIV and UDIV by constant as a multiply by magic constant instead
of integer divide, which is very slow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21104 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-06 00:25:27 +00:00
Nate Begeman
ad5f65c74b
Behold, rlwinm with certain immediate arguments is printed as the much more
...
readable slwi or srwi (shift left/right word immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21099 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-05 18:19:50 +00:00
Nate Begeman
a3829d5580
Fix cut & paste errors (32->64), and codegen float->int more optimally.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21098 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-05 17:32:30 +00:00
Nate Begeman
d3e6b94020
Remove 64 bit simple ISel, it never worked correctly
...
Add initial (buggy) implementation of 64 bit pattern ISel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21096 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-05 08:51:15 +00:00
Nate Begeman
c8c5c8f0fa
Back out the previous change to SelectBranchCC, since there are cases it
...
could miscompile. A correct solution will be found in the near future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21095 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-05 04:32:16 +00:00
Nate Begeman
439b444cad
Rename canUseAsImmediateForOpcode to getImmediateForOpcode to better
...
indicate that it is not a boolean function.
Properly emit the pseudo instruction for conditional branch, so that we
can fix up conditional branches whose displacements are too large.
Reserve the right amount of opcode space for said pseudo instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21094 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-05 04:22:58 +00:00
Nate Begeman
80196b1331
Implement SDIV by power of 2 as srawi/addze rather than load imm, divw
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21091 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-05 00:15:08 +00:00
Nate Begeman
93075ec0a5
Pattern match fp mul-add, mul-sub, neg-mul-add, and neg-mul-sub
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21090 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-04 23:40:36 +00:00
Nate Begeman
178bb34ee5
Add support for multiply-add, multiply-sub, and their negated versions
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21089 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-04 23:01:51 +00:00
Nate Begeman
d860aa62ac
Make sure that arg regs used by the call instruction are marked as such, so
...
that regalloc doesn't cleverly reuse early arg regs loading later arg regs.
This fixes almost all outstanding failures in the pattern isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21086 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-04 22:17:48 +00:00
Nate Begeman
04ec80173b
Remove unnecessary register copy now that regalloc is fixed
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21085 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-04 21:48:13 +00:00
Nate Begeman
c3e2db407e
i1 loads should also be from the low byte of the argument word.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21077 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-04 09:09:00 +00:00
Nate Begeman
e584668f04
Fix i64 return, fix CopyFromReg
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21076 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-04 06:52:38 +00:00
Nate Begeman
6644d4c933
Full varargs support. All of UnitTests now passes
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21070 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-03 23:11:17 +00:00
Nate Begeman
4ec0cbdf15
Pass the correct value for the chain to the store
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21066 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-03 22:22:56 +00:00
Nate Begeman
fa55470e39
Fix SHL_PARTS
...
Start implementation of integer varargs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21065 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-03 22:13:27 +00:00
Nate Begeman
aa73a9f16f
Keeping up with the Joneses.
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Implement not, nor, nand, and eqv
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21060 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-03 11:20:20 +00:00
Nate Begeman
27eeb00a1a
Set shift amount to Extend
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Implement ISD::FABS and ISD::FNEG nodes
Implement SHL_PARTS, SRL_PARTS, and SRA_PARTS
Generate PowerPC 'fneg', 'fabs', and 'fnabs' instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21018 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-02 05:59:34 +00:00
Chris Lattner
43fdea070c
This target doesn't support fabs/fneg yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21010 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-02 05:03:24 +00:00
Nate Begeman
27523a1c92
Fix i64 returns
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Generate PowerPC 'subfic' instruction when appropriate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20995 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-02 00:42:16 +00:00
Nate Begeman
fc1b1dad88
Add ISD::UNDEF node
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Teach the SelectionDAG code how to expand and promote it
Have PPC32 LowerCallTo generate ISD::UNDEF for int arg regs used up by fp
arguments, but not shadowing their value. This allows us to do the right
thing with both fixed and vararg floating point arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20988 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-01 22:34:39 +00:00
Nate Begeman
6cb2e1b124
Fix Olden/bh, CR0 was being set in the wrong order
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LowerCallTo and ISD::CALL are going to need to be modified, regs are being
set in the wrong order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20981 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-01 08:57:43 +00:00
Nate Begeman
31318e4b6c
Also apply Chris's fix to FP select and SETCC
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20979 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-01 07:21:30 +00:00
Chris Lattner
3071019026
Move the selection of the arms of the select operation up to the conditional
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part to make sure we get the side effects and to avoid confusing the CFG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20977 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-01 07:10:02 +00:00
Nate Begeman
a7e11a4bb5
Fix stores to global addresses
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Fix calls with no arguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20975 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-01 05:57:17 +00:00
Nate Begeman
04730361b5
Support indexed loads and stores. This drops Shootout/matrix time from
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18.8 to 14.8 seconds. The Pattern ISel is now often faster than the
Simple ISel, esp. on memory intensive code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20973 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-01 04:45:11 +00:00
Nate Begeman
6b55997df5
Implement FP_TO_SINT and FP_TO_UINT
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20972 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-01 02:59:27 +00:00
Nate Begeman
6d369ccae0
Add support for adding 0.0 and -0.0 to the constant pool, since we lie and
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say that we support them, for the purposes of generating fsel instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20970 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-01 01:08:07 +00:00
Nate Begeman
dffcfccc13
Factor out common code, support FP comparison in folded SetCC
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20969 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-01 00:32:34 +00:00
Nate Begeman
3e89716ad7
fsel generation for f32 and f64 select
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generate compare immediate for integer compare with constant
fold setcc into branch
fold setcc into select
Code generation quality for Shootout is now on par with the Simple ISel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20968 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-31 23:55:40 +00:00
Nate Begeman
96fc681d7e
Pass the correct values to the chain argument for node construction during
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LowerCallTo.
Handle ISD::ADD in SelectAddr, allowing us to have nonzero immediates for
loads and stores, amazing!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20946 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-31 02:05:53 +00:00
Nate Begeman
74d734574e
Rewrite LowerCallTo and Select(ISD::CALL) to properly handle float varargs
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Tell the SelectionDAG ISel to expand SEXTLOAD of i1 and i8, rather than
complicate the code in ISD::SEXTLOAD to do it by hand
Combine the FP and Int ISD::LOAD codegen
Generate better code for constant pool loads
As a result, all of Shootout, and likely many other programs are now
working.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20945 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-31 00:15:26 +00:00
Nate Begeman
fdcf3418e0
Fix calls whose arguments fit entirely in registers to not break the Chain.
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Implement SINT_TO_FP and UINT_TO_FP
Remove some dead code from the simple ISel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20944 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-30 19:38:35 +00:00
Nate Begeman
58f718cd97
Fix frame index code to generate legal PowerPC instructions. About half of
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Shootout now works.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20940 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-30 02:23:08 +00:00
Nate Begeman
01d05266f9
Fix external symbol printing in the AsmPrinter. Tell the ISel that we
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don't support things like memcpy directly. This allows a handful of the
Shootout programs to work, yay!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20939 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-30 01:45:43 +00:00
Nate Begeman
23afcfb063
Fix BranchCC (it's still dumb), and implement FP select (also dumb)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20935 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-29 22:48:55 +00:00
Nate Begeman
74747861b9
Implement integer select and i1 sign extend
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20934 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-29 22:24:51 +00:00
Nate Begeman
3316252034
Implement SetCC, fix ZERO_EXTEND_INREG
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20933 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-29 21:54:38 +00:00
Chris Lattner
848132d671
fix a warning in the optimized build
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20920 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-29 15:13:27 +00:00
Nate Begeman
f3d08f31b3
Implement div, rem, and frameindex
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20907 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-29 00:03:27 +00:00
Nate Begeman
f70b576ccc
Pattern ISel: fix argument loading for i64s (thanks chris)
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Simple ISel: fix i64 subtract
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20903 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-28 23:08:54 +00:00
Nate Begeman
ca12a2bd91
Remove fake instruction 'subc' (mnemonic for subfc).
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More pattern isel updates
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20902 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-28 22:28:37 +00:00
Nate Begeman
9db505ca9d
Implement proper loads and zero-extends of all types
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20897 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-28 19:36:43 +00:00
Nate Begeman
7532e2f555
Fix that pesky floats in integer regs problem by assigning the f32 type to
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the correct register class. Also remove the loading of float data into int
regs part of varargs; it will need to be implemented differently later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20857 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-26 08:25:22 +00:00
Nate Begeman
f7e4338035
Get closer to having varargs working. There's still something strange
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going on with copies between floating point and integer register files
being generated. Once that is solved, varargs will be done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20856 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-26 07:46:36 +00:00
Nate Begeman
f26226155e
Make 64bit args and float args work correct with calls. Thanks to Chris
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for explaining EXTRACT_ELEMENT to me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20847 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-26 02:17:46 +00:00
Nate Begeman
307e7443b8
Next round of pattern isel changes, mostly dealing with calls.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20841 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-26 01:28:53 +00:00
Nate Begeman
c13a7f0eb3
Correct a documention link
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20840 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-26 01:28:05 +00:00
Nate Begeman
c7b09f1f01
Support global addresses and fix call returns. Varargs still aren't
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handled correctly for floating point arguments, or more than 8 arguemnts.
This does however, allow hello world to run.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20832 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-25 08:34:25 +00:00
Nate Begeman
9e3e1b5d44
Implement next round of Pattern ISel fixes
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1. void returns
2. multiplies
3. calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20822 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-24 23:35:30 +00:00
Nate Begeman
7ca541b75a
Fix an incorrect argument being passed to BuildMI for indirect calls.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20821 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-24 23:34:38 +00:00
Nate Begeman
2daec45751
Commit Gabor Greif's patch to use iterators in lowering intrinsics.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20816 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-24 20:07:16 +00:00