Daniel Dunbar
cb8326dc09
MC: Add TargetMachine support for setting the value of MCRelaxAll with
...
-filetype=obj.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 21:48:55 +00:00
Jakob Stoklund Olesen
160a3bf74d
Add StringRef::compare_numeric and use it to sort TableGen register records.
...
This means that our Registers are now ordered R7, R8, R9, R10, R12, ...
Not R1, R10, R11, R12, R2, R3, ...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 21:47:28 +00:00
Dan Gohman
113b3e2c6e
Implement checking of the tail keyword.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104744 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 21:46:36 +00:00
Devang Patel
77051f58e9
There is no need to force an line number entry (using previous location) for a temp label at unknown location.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104740 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 21:23:46 +00:00
Bill Wendling
8d717c7d99
Add "setjmp_syscall", "savectx", "qsetjmp", "vfork", "getcontext" to the list of
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usual suspects that could "return twice".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104737 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 20:39:00 +00:00
Daniel Dunbar
83194de76a
MC: When running with -mc-relax-all, we can eagerly relax instructions and avoid creating unnecessary MCInstFragments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104736 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 20:37:03 +00:00
Daniel Dunbar
2ac0c453b2
MC/Mach-O: Factor out EmitInstTo{Fragment,Data} for emitting MCInst's as MCInstFragments or appending onto an MCDataFragment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104735 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 20:37:00 +00:00
Jim Grosbach
23ff7cff52
Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in
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ISD::. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104734 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 20:22:18 +00:00
Devang Patel
394427b014
Update debug info when live-in reg is copied into a vreg.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104732 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 20:18:50 +00:00
Kevin Enderby
b106543592
Fix the x86 move to/from segment register instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104731 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 20:10:45 +00:00
Bill Wendling
9af7e9a1b5
Move the check for "calls setjmp" to SelectionDAGISel so that it can be used by
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more than just the stack slot coloring algorithm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104722 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 19:46:12 +00:00
Devang Patel
b2b31a6f93
Identify instructions, that needs a label to mark debug info entity, in advance. This simplifies beginScope().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104720 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 19:37:24 +00:00
Dan Gohman
93d3433579
Eliminate the use of PriorityQueue and just use a std::vector,
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implementing pop with a linear search for a "best" element. The priority
queue was a neat idea, but in practice the comparison functions depend
on dynamic information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104718 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 18:52:00 +00:00
Dan Gohman
d89c258051
Delete an unused function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104716 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 18:34:12 +00:00
Daniel Dunbar
95506d40c5
MC: Change RelaxInstruction to only take the input and output instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104713 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 18:15:06 +00:00
Dan Gohman
d9c2af5409
Fix a typo in a comment that Gabor noticed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104711 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 18:03:53 +00:00
Daniel Dunbar
dae5b9f804
MC: Eliminate an unnecessary copy.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104709 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 17:50:16 +00:00
Daniel Dunbar
8488252855
MC: Simplify MayNeedRelaxation to not provide the fixups, so we can query it
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before encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104707 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 17:45:29 +00:00
Devang Patel
b21a758bc2
Remove dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104706 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 17:42:50 +00:00
Devang Patel
e2df84254d
Do not construct location list backword!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104705 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 17:29:32 +00:00
Jakob Stoklund Olesen
ca561ffcf3
Replace the SubRegSet tablegen class with a less error-prone mechanism.
...
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 17:27:12 +00:00
Daniel Dunbar
c90e30aa6f
MC: Eliminate MCAsmFixup, replace with MCFixup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104699 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 15:18:56 +00:00
Daniel Dunbar
482ad802f1
MC: Use accessors for access to MCAsmFixup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104697 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 15:18:31 +00:00
Daniel Dunbar
c9adb8c61e
MC: Change MCInst::dump_pretty to not include a trailing newline.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104696 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 15:18:13 +00:00
Benjamin Kramer
1464c1d60a
Kill unneeded SExt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104692 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 09:45:04 +00:00
Zhongxing Xu
c2798a18a7
SRetReturnReg was set in LowerFormalArguments(). So only assert it here.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104691 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 08:10:02 +00:00
Daniel Dunbar
e614e393c7
MC: Eliminate MCFragment vtable, which was unnecessary.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104689 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 06:50:57 +00:00
Shih-wei Liao
9f3b6a381a
Coding style change (Adding 1 missing space.)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104670 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 04:46:50 +00:00
Shih-wei Liao
45469f38b6
Adding the missing implementation for ARM::SBFX and ARM::UBFX.
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Fixing http://llvm.org/bugs/show_bug.cgi?id=7225 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104667 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 03:21:39 +00:00
Eric Christopher
174e597d46
Temporarily revert r104655 as it's breaking the bots.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104664 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 01:59:55 +00:00
Jim Grosbach
54e13eceff
fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104661 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 01:22:21 +00:00
Jakob Stoklund Olesen
b555609e73
Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."
...
This reverts commit 104654.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 01:21:14 +00:00
Dan Gohman
a4e4ffd389
Change push_all to a non-virtual function and implement it in the
...
base class, since all the implementations are the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104659 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 01:10:55 +00:00
Dan Gohman
5eabaa2d7c
Trim #include.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104657 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 00:55:59 +00:00
Bill Wendling
be22683202
Dale and Evan suggested putting the "check for setjmp" much earlier in the
...
machine code generation. That's a good idea, so I made it so.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104655 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 00:32:40 +00:00
Jakob Stoklund Olesen
6a45d681e5
Replace the SubRegSet tablegen class with a less error-prone mechanism.
...
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 00:28:19 +00:00
Shih-wei Liao
6d37a29588
Adding the missing implementation of Bitfield's "clear" and "insert".
...
Fixing http://llvm.org/bugs/show_bug.cgi?id=7222 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104653 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 00:25:05 +00:00
Shih-wei Liao
5170b71143
To handle s* registers in emitVFPLoadStoreMultipleInstruction().
...
Fixing http://llvm.org/bugs/show_bug.cgi?id=7221 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104652 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 00:02:28 +00:00
Eric Christopher
96ac5156ca
Start adding mach-o tls reloc support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104651 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 00:02:12 +00:00
Jakob Stoklund Olesen
76f0ad7bf5
Drop the SuperregHashTable. It is essentially the same as SubregHashTable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104650 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 23:43:18 +00:00
Devang Patel
c3f5f783a2
First cut at supporting .debug_loc section.
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This is used to track variable information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104649 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 23:40:22 +00:00
Benjamin Kramer
48aefe15d0
Properly promote operands when optimizing a single-character memcmp.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104648 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 22:53:43 +00:00
Bill Wendling
f10bc81b4e
Constify function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104646 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 22:02:22 +00:00
Dan Gohman
eddc114a66
Do one map lookup instead of two.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104645 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 21:59:42 +00:00
Dan Gohman
5b71dcedf0
Fix a missing newline in debug output.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104644 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 21:50:35 +00:00
Eric Christopher
04386ca726
Move the verbose asm output up a bit so it can be used in the special cases
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as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104642 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 21:49:43 +00:00
Bill Wendling
5edfbdc963
Okay, bear with me here...
...
If you have a setjmp/longjmp situation, it's possible for stack slot coloring to
reuse a stack slot before it's really dead. For instance, if we have something
like this:
1: y = g;
x = sigsetjmp(env, 0);
switch (x) {
case 1:
/* ... */
goto run;
case 0:
run:
do_run(); /* marked as "no return" */
break;
case 3:
if (...) {
/* ... */
goto run;
}
/* ... */
break;
}
2: g = y;
"y" may be put onto the stack, so the expression "g = y" is relying upon the
fact that the stack slot containing "y" isn't modified between (1) and (2). But
it can be, because of the "no return" calls in there. A longjmp might come back
with 3, modify the stack slot, and then go to case 0. And it's perfectly
acceptable to reuse the stack slot there because there's no CFG flow from case 3
to (2).
The fix is to disable certain optimizations in these situations. Ideally, we'd
disable them for all "returns twice" functions. But we don't support that
attribute. Check for "setjmp" and "sigsetjmp" instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 21:44:26 +00:00
Eric Christopher
02b46bc942
Add support for initialized global data for darwin tls. Update comments
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and testcases accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104635 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 21:28:50 +00:00
Kevin Enderby
cf50a5390c
Changed the encoding of X86 floating point stack operations where both operands
...
are st(0). These can be encoded using an opcode for storing in st(0) or using
an opcode for storing in st(i), where i can also be 0. To allow testing with
the darwin assembler and get a matching binary the opcode for storing in st(0)
is now used. To do this the same logical trick is use from the darwin assembler
in converting things like this:
fmul %st(0), %st
into this:
fmul %st(0)
by looking for the second operand being X86::ST0 for specific floating point
mnemonics then removing the second X86::ST0 operand. This also has the add
benefit to allow things like:
fmul %st(1), %st
that llvm-mc did not assemble.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104634 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 20:52:34 +00:00
Jakob Stoklund Olesen
b53985239c
Separate unrelated cases that once shared a numeric value
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104629 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 19:49:40 +00:00
Jakob Stoklund Olesen
1fc8e759a7
Print symbolic SubRegIndex names on machine operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104628 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 19:49:38 +00:00
Jakob Stoklund Olesen
4fda9670f0
Remove NumberHack entirely.
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SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104627 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 19:49:33 +00:00
Daniel Dunbar
39e2dd7bab
MC/X86: Add a hack to allow recognizing 'cmpltps' and friends.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104626 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 19:49:32 +00:00
Dale Johannesen
86234c30a7
Fix another variant of PR 7191. Also add a testcase
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Mon Ping provided; unfortunately bugpoint failed to
reduce it, but I think it's important to have a test for
this in the suite. 8023512.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104624 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 18:47:23 +00:00
Daniel Dunbar
79373680ed
MC/X86: Define explicit immediate forms of cmp{ss,sd,ps,pd}.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104622 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 18:40:53 +00:00
Kevin Enderby
04ac770be9
The BT64ri8 record in X86Instr64bit.td was missing a REX_W which is required
...
for the 64-bit version of the Bit Test instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104621 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 18:16:58 +00:00
Dale Johannesen
61734eb117
Fix PR 7191. I have been unable to create a .ll file that fails, sorry.
...
(oye, a word which should be better known to people writing tree
traversals, means grandchild.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104619 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 17:50:03 +00:00
Eric Christopher
7e2f5aaa67
Make sure aeskeygenassist uses an unsigned immediate field.
...
Fixes rdar://8017638
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104617 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 17:33:22 +00:00
Jakob Stoklund Olesen
48d0c163fb
Ignore NumberHack and give each SubRegIndex instance a unique enum value instead.
...
This passes lit tests, but I'll give it a go through the buildbots to smoke out
any remaining places that depend on the old SubRegIndex numbering.
Then I'll remove NumberHack entirely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104615 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 17:21:04 +00:00
Jakob Stoklund Olesen
c159fba712
Use enums instead of literals for SystemZ subregisters
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104612 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 17:04:18 +00:00
Jakob Stoklund Olesen
22c0e97c56
Use enums instead of literals for X86 subregisters.
...
The cases in getMatchingSuperRegClass cannot be broken up until the enums have
unique values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104611 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 17:04:16 +00:00
Zonr Chang
f3c770a2cb
Add missing implementation to the materialization of VFP misc. instructions (vmrs, vmsr and vmov (immediate))
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104588 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 10:23:52 +00:00
Zonr Chang
f86399be0c
Add support to MOVimm32 using movt/movw for ARM JIT
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104587 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 08:42:45 +00:00
Bob Wilson
a85df80ed7
Allow t2MOVsrl_flag and t2MOVsra_flag instructions to be predicated.
...
I don't know of any particular reason why that would be important, but
neither can I see any reason to disallow it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104583 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 04:51:47 +00:00
Bob Wilson
4876bdb69e
Fix up instruction classes for Thumb2 RSB instructions to be consistent with
...
Thumb2 ADD and SUB instructions: allow RSB instructions be changed to set the
condition codes, and allow RSBS instructions to be predicated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104582 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 04:43:08 +00:00
Bob Wilson
ab3912e3ce
Clean up indentation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104580 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 03:36:52 +00:00
Jakob Stoklund Olesen
b7a3170917
Disable invalid coalescer assertion.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104574 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 00:15:18 +00:00
Jakob Stoklund Olesen
e00fa64c16
Use enums instead of literals in the ARM backend.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104573 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 00:15:15 +00:00
Bill Wendling
ef473bfc44
Print out the name of the function during SSC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104572 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 23:16:04 +00:00
Jakob Stoklund Olesen
33276d95ef
Switch SubRegSet to using symbolic SubRegIndices
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104571 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 23:03:18 +00:00
Bob Wilson
c21763fd99
Allow Thumb2 MVN instructions to set condition codes. The immediate operand
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version of t2MVN already allowed that, but not the register versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 22:41:19 +00:00
Jakob Stoklund Olesen
f27462eb29
Lose the dummies
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104564 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 21:47:01 +00:00
Jakob Stoklund Olesen
09bc029865
Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
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structure that represents a mapping without any dependencies on SubRegIndex
numbering.
This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 21:46:58 +00:00
Evan Cheng
3946043a80
Avoid adding duplicate function live-in's.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104560 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 21:33:37 +00:00
Dan Gohman
e350690e3b
Fix an mmx movd encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104552 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 20:51:08 +00:00
Kevin Enderby
ca956dc0f6
MC/X86: Add aliases for CMOVcc variants.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104549 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 20:32:23 +00:00
Bob Wilson
d303846e16
Clean up some extra whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104544 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 20:08:34 +00:00
Bob Wilson
bb7ecb2bf5
Thumb2 RSBS instructions were being printed without the 'S' suffix.
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Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 18:44:06 +00:00
Devang Patel
295cdf8b82
Do not emit line number entries for unknown debug values.
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This fixes recent regression in store.exp from gdb testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104524 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 18:26:49 +00:00
Evan Cheng
c7cf10c97e
LR is in GPR, not tGPR even in Thumb1 mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104518 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 18:00:18 +00:00
Jakob Stoklund Olesen
a1132276e7
Add SubRegIndex defs to PowerPC. It looks like the CR subregister indices are
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never used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104517 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 17:55:38 +00:00
Jakob Stoklund Olesen
d6be874e8c
Use SubRegIndex in SystemZ.
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Anton, please review the change to SystemZAsmPrinter.cpp. It could be a bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104515 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 17:43:01 +00:00
Jakob Stoklund Olesen
fff916a960
SubRegIndex'ize Mips
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104514 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 17:42:58 +00:00
Jakob Stoklund Olesen
59f7199e16
SubRegIndex'ize MSP430
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 17:42:55 +00:00
Jakob Stoklund Olesen
7bb31e3187
Fix a few places that depended on the numeric value of subreg indices.
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Add assertions in places that depend on consecutive indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104510 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 17:13:28 +00:00
Jakob Stoklund Olesen
558661d271
Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums
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from ARMRegisterInfo.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104508 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 16:54:32 +00:00
Jakob Stoklund Olesen
3458e9e4df
Rename X86 subregister indices to something shorter.
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Use the tablegen-produced enums.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104493 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 14:48:17 +00:00
Jakob Stoklund Olesen
73ea7bf450
Add the SubRegIndex TableGen class.
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This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104492 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 14:48:12 +00:00
Nicolas Geoffray
3816c25fdc
Encode the Caml frametable by following what the comment says: the number of descriptors
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is first emitted, and StackOffsets are emitted in 16 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104488 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 12:24:11 +00:00
Daniel Dunbar
414c0c43d3
llvm-mc: Use EmitIntValue where possible, which makes the API calls from the AsmParser and CodeGen line up better.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104467 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-23 18:36:38 +00:00
Daniel Dunbar
01777ff094
llvm-mc: Use AddBlankLine in asm parser. This makes transliteration match the input much more closely, and also makes the API calls from the AsmParser and CodeGen line up better.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104466 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-23 18:36:34 +00:00
Daniel Dunbar
fdb5a86179
MC: Add an MCLoggingStreamer, for use in debugging integrated-as mismatches.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104463 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-23 17:44:06 +00:00
Bob Wilson
069e434868
VDUP doesn't support vectors with 64-bit elements.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104455 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-23 05:42:31 +00:00
Daniel Dunbar
62e4c671b6
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example:
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addw $0xFFFF, %ax
should match the same as
addw $-1, %ax
but we used to match it to the longer encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 21:02:33 +00:00
Daniel Dunbar
54ddf3d9c7
tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104452 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 21:02:29 +00:00
Daniel Dunbar
4c361972fd
MC/X86: Add alias for setz, setnz, jz, jnz.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 06:37:33 +00:00
Evan Cheng
2457f2c661
Implement @llvm.returnaddress. rdar://8015977.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 01:47:14 +00:00
Jim Grosbach
5eb1951539
Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.
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Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104419 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 01:06:18 +00:00
Bob Wilson
be751cfe9c
Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by
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copying VFP subregs. This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104415 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 00:23:12 +00:00
Eric Christopher
8116ca5134
Add full bss data support for darwin tls variables.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104414 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 00:10:22 +00:00