Commit Graph

4455 Commits

Author SHA1 Message Date
Owen Anderson
654d5440a4 Add a subtarget hook for reporting the misprediction penalty. Use this to provide more precise
cost modeling for if-conversion.  Now if only we had a way to estimate the misprediction probability.

Adjsut CodeGen/ARM/ifcvt10.ll.  The pipeline on Cortex-A8 is long enough that it is still profitable
to predicate an ldm, but the shorter pipeline on Cortex-A9 makes it unprofitable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114995 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 21:57:50 +00:00
Anton Korobeynikov
4f922f2cca User proper libcall names & condcodes while compiling for ARM EABI.
Patch by Evzen Muller!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 21:39:26 +00:00
Owen Anderson
b20b85168c Part one of switching to using a more sane heuristic for determining if-conversion profitability.
Rather than having arbitrary cutoffs, actually try to cost model the conversion.

For now, the constants are tuned to more or less match our existing behavior, but these will be
changed to reflect realistic values as this work proceeds.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114973 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 18:32:13 +00:00
Bob Wilson
02aba73a9e Add a command line option "-arm-strict-align" to disallow unaligned memory
accesses for ARM targets that would otherwise allow it.  Radar 8465431.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-28 04:09:35 +00:00
Jakob Stoklund Olesen
08342f2d11 Revert "Disable codegen prepare critical edge splitting. Machine instruction passes now"
This reverts revision 114633. It was breaking llvm-gcc-i386-linux-selfhost.

It seems there is a downstream bug that is exposed by
-cgp-critical-edge-splitting=0. When that bug is fixed, this patch can go back
in.

Note that the changes to tailcallfp2.ll are not reverted. They were good are
required.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114859 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 18:43:48 +00:00
Jakob Stoklund Olesen
b53afc6a12 Explicitly disable CGP critical edge splitting for this test so it won't break
by reenabling it temporarily.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114858 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 18:43:43 +00:00
Jakob Stoklund Olesen
4c2c865a51 Don't depend on basic block numbering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114857 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 18:43:40 +00:00
Chris Lattner
8048ebe91d the latest assembler that runs on powerpc 10.4 machines doesn't
support aligned comm.  Detect when compiling for 10.4 and don't
emit an alignment for comm.  THis will hopefully fix PR8198.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114817 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-27 06:44:54 +00:00
Che-Liang Chiou
8db2defa83 Add test case for PTX ret instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114789 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-25 07:49:54 +00:00
Che-Liang Chiou
f9930da2ef Add ret instruction to PTX backend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114788 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-25 07:46:17 +00:00
Evan Cheng
fff606d7b2 Enable code placement optimization pass for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-24 19:07:23 +00:00
Bob Wilson
2a6e616142 Set alignment operand for NEON VST instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114709 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 23:42:37 +00:00
Bob Wilson
40ff01a030 Set alignment operand for NEON VLD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114696 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 21:43:54 +00:00
Evan Cheng
dd3a41a6b3 Disable codegen prepare critical edge splitting. Machine instruction passes now
break critical edges on demand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114633 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 06:55:34 +00:00
Owen Anderson
ed1088afb5 A select between a constant and zero, when fed by a bit test, can be efficiently
lowered using a series of shifts.
Fixes <rdar://problem/8285015>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114599 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 22:58:22 +00:00
Cameron Esfahani
4af1eaee70 Fix PR8201: Update the code to call via X86::CALL64pcrel32 in the 64-bit case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114597 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 22:35:21 +00:00
Chris Lattner
1eb1b68e3a Fix an inconsistency in the x86 backend that led it to reject "calll foo" on
x86-32: 32-bit calls were named "call" not "calll".  64-bit calls were correctly
named "callq", so this only impacted x86-32.

This fixes rdar://8456370 - llvm-mc rejects 'calll'

This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call,
I will file a bugzilla.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114534 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 05:49:14 +00:00
Chris Lattner
f93b90c5df reimplement elf TLS support in terms of addressing modes, eliminating SegmentBaseAddress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114529 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 04:39:11 +00:00
Chris Lattner
40d66052f4 linux has a different stack alignment than the mac, relax this a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114519 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 00:46:26 +00:00
Chris Lattner
8864155a35 give VZEXT_LOAD a memory operand, it now works with segment registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114515 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 00:34:38 +00:00
Chris Lattner
0b79cfee15 revert r114386 now that address modes work correctly, we get a nice
call through gs-relative memory now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114510 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 00:11:31 +00:00
Chris Lattner
93c4a5bef7 give LCMPXCHG_DAG[8] a memory operand, allowing it to work with addrspace 256/257
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114508 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 23:59:42 +00:00
Chris Lattner
b72d53d8ef filecheckize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114507 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 23:57:27 +00:00
Evan Cheng
691e64a54c OptimizeCompareInstr should avoid iterating pass the beginning of the MBB when the 'and' instruction is after the comparison.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114506 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 23:49:07 +00:00
Owen Anderson
8614167572 Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes
irrelevant, but add a new test for the new, improved functionality.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114494 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 22:51:46 +00:00
Devang Patel
161f0caaf9 Use FileCheck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114475 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 20:50:32 +00:00
Owen Anderson
c004eec71b When adding the carry bit to another value on X86, exploit the fact that the carry-materialization
(sbbl x, x) sets the registers to 0 or ~0.  Combined with two's complement arithmetic, we can fold
the intermediate AND and the ADD into a single SUB.

This fixes <rdar://problem/8449754>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114460 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 18:41:19 +00:00
Chris Lattner
08bad54baf fix rdar://8453210, a crash handling a call through a GS relative load.
For now, just disable folding the load into the call.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114386 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 03:37:00 +00:00
Evan Cheng
44be1a8d66 Enable machine sinking critical edge splitting. e.g.
define double @foo(double %x, double %y, i1 %c) nounwind {
  %a = fdiv double %x, 3.2
  %z = select i1 %c, double %a, double %y
  ret double %z
}

Was:
_foo:
        divsd   LCPI0_0(%rip), %xmm0
        testb   $1, %dil
        jne     LBB0_2
        movaps  %xmm1, %xmm0
LBB0_2:
        ret

Now:
_foo:
        testb   $1, %dil
        je      LBB0_2
        divsd   LCPI0_0(%rip), %xmm0
        ret
LBB0_2:
        movaps  %xmm1, %xmm0
        ret

This avoids the divsd when early exit is taken.
rdar://8454886


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114372 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-20 22:52:00 +00:00
Owen Anderson
765fd9c62d CombinerAA is now reordering these stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114354 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-20 20:56:29 +00:00
Owen Anderson
4a9f150926 When TCO is turned on, it is possible to end up with aliasing FrameIndex's. Therefore,
CombinerAA cannot assume that different FrameIndex's never alias, but can instead use
MachineFrameInfo to get the actual offsets of these slots and check for actual aliasing.

This fixes CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll and CodeGen/X86/tailcallstack64.ll
when CombinerAA is enabled, modulo a different register allocation sequence.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-20 20:39:59 +00:00
Jim Grosbach
1dc335a79f Simplify ARM callee-saved register handling by removing the distinction
between the high and low registers for prologue/epilogue code. This was
a Darwin-only thing that wasn't providing a realistic benefit anymore.
Combining the save areas simplifies the compiler code and results in better
ARM/Thumb2 codegen.

For example, previously we would generate code like:
        push    {r4, r5, r6, r7, lr}
        add     r7, sp, #12
        stmdb   sp!, {r8, r10, r11}
With this change, we combine the register saves and generate:
        push    {r4, r5, r6, r7, r8, r10, r11, lr}
        add     r7, sp, #12

rdar://8445635



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114340 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-20 19:32:20 +00:00
NAKAMURA Takumi
e6af80d11d test/CodeGen/X86: Add explicit triplet -mtriple=i686-linux to 3 tests incompatible to Win32 codegen.
r114297 raises 3 failures. They might fail also on mingw.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114317 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-19 21:58:55 +00:00
Eric Christopher
50880d08ec Add the exit instruction to the PTX target.
Patch by Che-Liang Chiou <clchiou@gmail.com>!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114294 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 18:52:28 +00:00
Owen Anderson
14ac1dd2be Invert the logic of reachesChainWithoutSideEffects(). What we want to check is that there is
NO path to the destination containing side effects, not that SOME path contains no side effects.
In  practice, this only manifests with CombinerAA enabled, because otherwise the chain has little
to no branching, so "any" is effectively equivalent to "all".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114268 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 04:45:14 +00:00
Bob Wilson
75f0288b7d Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64
value should be in GPRs when it's going to be used as a scalar, and we use
VMOVRRD to make that happen, but if the value is converted back to a vector
we need to fold to a simple bit_convert.  Radar 8407927.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 22:59:05 +00:00
Jim Grosbach
e6be85e9ff Teach the (non-MC) instruction printer to use the cannonical names for push/pop,
and shift instructions on ARM. Update the tests to match.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114230 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 22:36:38 +00:00
Evan Cheng
6edb0eac87 Teach machine sink to
1) Do forward copy propagation. This makes it easier to estimate the cost of the
   instruction being sunk.
2) Break critical edges on demand, including cases where the value is used by
   PHI nodes.
Critical edge splitting is not yet enabled by default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114227 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 22:28:18 +00:00
Jim Grosbach
9ce75625eb Update tests to handle MC-inst instruction printing of shift operations. The
legacy asm printer uses instructions of the form, "mov r0, r0, lsl #3", while
the MC-instruction printer uses the form "lsl r0, r0, #3". The latter mnemonic
is correct and preferred according the ARM documentation (A8.6.98). The former
are pseudo-instructions for the latter.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114221 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 21:58:46 +00:00
Jim Grosbach
db664ad71e FileCheck-ize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114218 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 21:46:16 +00:00
Jim Grosbach
1aaf4cb393 Move thumb2 tests to the thumb2 directory
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114206 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 20:34:09 +00:00
Jim Grosbach
c0911c3b3e tweak test to check instructions rather than relying on the comment string
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 20:27:26 +00:00
Dan Gohman
d8c0a51362 Avoid emitting a PIC base register if no PIC addresses are needed.
This fixes rdar://8396318.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114201 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 20:24:24 +00:00
Jim Grosbach
d4ef24344a tweak test to check instructions rather than relying on the comment string
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114200 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 20:21:03 +00:00
Jim Grosbach
48afc24274 tweak test to check instructions rather than relying on the comment string
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114199 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 20:17:41 +00:00
Dale Johannesen
677c6ecd08 When substituting sunkaddrs into indirect arguments an asm, we were
walking the asm arguments once and stashing their Values.  This is
wrong because the same memory location can be in the list twice, and
if the first one has a sunkaddr substituted, the stashed value for the
second one will be wrong (use-after-free).  PR 8154.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114104 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 18:30:55 +00:00
Kalle Raiskila
1cd1b0b283 Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction.
This cleans up after the mess r108567 left in the CellSPU backend.
ORCvt-instruction were used to reinterpret registers, and the ORs were then
removed by isMoveInstr(). This patch now removes 350 instrucions of format:
	or $3, $3, $3
(from the 52 testcases in CodeGen/CellSPU). One case of a nonexistant or is
checked for.

Some moves of the form 'ori $., $., 0' and 'ai $., $., 0' still remain.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114074 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 12:29:33 +00:00
Bob Wilson
3a951829fe Reapply Gabor's 113839, 113840, and 113876 with a fix for a problem
encountered while building llvm-gcc for arm.  This is probably the same issue
that the ppc buildbot hit. llvm::prior works on a MachineBasicBlock::iterator,
not a plain MachineInstr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113983 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 17:12:08 +00:00
Gabor Greif
7602993f2d the darwin9-powerpc buildbot keeps consistently crashing,
backing out following to get it back to green,
so I can investigate in peace:

svn merge -c -113840  llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
svn merge -c -113876 -c -113839 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113980 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 16:53:07 +00:00
Gabor Greif
6f9eea87f7 forgot the testcase change for r113839
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113840 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14 09:30:17 +00:00