Chris Lattner
3ee9ffb0e5
Add a bunch of notes from my journey thus far.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27170 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 07:41:00 +00:00
Chris Lattner
b86bd2cee2
Split out altivec notes into their own README
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27168 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 07:04:16 +00:00
Chris Lattner
fb143ce459
Fix the JIT encoding of VSEL
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27160 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 03:34:17 +00:00
Chris Lattner
eeaf72af39
Fix the JIT encoding of VSPLTI*
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27159 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 03:28:57 +00:00
Nate Begeman
f15485a8d0
SelectionDAGISel can now natively handle Switch instructions, in the same
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manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks. The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.
This functionality is currently only enabled on x86, but should be safe for
every target. In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27156 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-27 01:32:24 +00:00
Chris Lattner
bd6be6f52d
add vsel
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27153 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 22:38:43 +00:00
Chris Lattner
6d92caddc4
Codegen vector predicate compares.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27151 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 10:06:40 +00:00
Evan Cheng
5b6a01b59c
Remove PPC:isZeroVector, use ISD::isBuildVectorAllZeros instead
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27149 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 09:52:32 +00:00
Chris Lattner
b8a45c2798
Add all of the altivec comparison instructions. Add patterns for the
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non-predicate altivec compare intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27143 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 04:57:17 +00:00
Chris Lattner
5d72907e00
Add and 8/16-bit adds, add all integer subtracts, add saturating subtract
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intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27142 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 02:39:02 +00:00
Chris Lattner
e7d959c069
implement the vsldoi intrinsic.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27139 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-26 00:41:48 +00:00
Chris Lattner
af9136bc0c
fix the pattern for vandc, it's NOT vnand
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27136 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 23:10:40 +00:00
Chris Lattner
6509ae859a
add patterns for VANDC/VNOR, implementing
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CodeGen/PowerPC/eqv-andc-orc-nor.ll:VNOR/VANDC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27135 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 23:05:29 +00:00
Chris Lattner
2430a5f0c7
Add some logical operations
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27127 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 22:16:05 +00:00
Chris Lattner
984f38bf4f
implement a bunch of intrinsics
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27118 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 08:01:02 +00:00
Chris Lattner
b22a04d881
Move all Altivec stuff out into a new PPCInstrAltivec.td file.
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Add a bunch of patterns for different datatypes, e.g. bit_convert, undef and
zero vector support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27117 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 07:51:43 +00:00
Chris Lattner
8d052bc711
Add some basic patterns for other datatypes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27116 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 07:39:07 +00:00
Chris Lattner
150ffa7842
add all supported formats to the vector register file
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27115 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 07:36:56 +00:00
Chris Lattner
5a2025465b
Add support for __builtin_altivec_vnmsubfp /vmaddfp
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27112 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 07:05:55 +00:00
Chris Lattner
420736dc85
#include Intrinsics.h into all dag isels
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27109 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 06:47:10 +00:00
Chris Lattner
9c61dcf1aa
Codegen things like:
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<int -1, int -1, int -1, int -1>
and
<int 65537, int 65537, int 65537, int 65537>
Using things like:
vspltisb v0, -1
and:
vspltish v0, 1
instead of using constant pool loads.
This implements CodeGen/PowerPC/vec_splat.ll:splat_imm_i{32|16}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27106 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-25 06:12:06 +00:00
Jim Laskey
47622e3721
Add dwarf register numbering to register data.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27081 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 21:15:58 +00:00
Chris Lattner
057f09bc0b
add another note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27077 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 20:04:27 +00:00
Chris Lattner
8edd11f33d
Fix a bad JIT encoding of VPERM. Why is VPERM D,A,B,C but vfmadd is D,A,C,B ??
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27069 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 18:24:43 +00:00
Chris Lattner
54e869e18c
Like the comment says, prefer to use the implicit add done by [r+r] addressing
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modes than emitting an explicit add and using a base of r0. This implements
Regression/CodeGen/PowerPC/mem-rr-addr-mode.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27068 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 17:58:06 +00:00
Chris Lattner
7fbcef7102
Disable the i32->float G5 optimization. It is unsafe, as documented in the
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comment.
This fixes 177.mesa, and McCat/09-vor with the td scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27060 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 07:53:47 +00:00
Chris Lattner
64b3a08bc6
add support for using vxor to build zero vectors. This implements
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Regression/CodeGen/PowerPC/vec_zero.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27059 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 07:48:08 +00:00
Chris Lattner
9d5da1d96c
Gabor points out that we can't spell. :)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27049 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 07:12:19 +00:00
Chris Lattner
716aefcd91
add a note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27000 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-23 21:28:44 +00:00
Chris Lattner
dc6af72781
Add PPC vector bit-convert support
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26995 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-23 19:54:27 +00:00
Jim Laskey
f1d78e8335
Add support to locate local variables in frames (early version.)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26994 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-23 18:12:57 +00:00
Jim Laskey
99db0442f0
Change interface to DwarfWriter.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26991 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-23 18:09:44 +00:00
Chris Lattner
bc641b9d8b
Eliminate IntrinsicLowering from TargetMachine.
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Make the CBE and V9 backends create their own, since they're the only ones that use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26974 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-23 05:43:16 +00:00
Chris Lattner
9d86a9dff2
This has been implemented. Tweak it into another note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26944 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 05:33:23 +00:00
Chris Lattner
ecfe55e65b
When possible, custom lower 32-bit SINT_TO_FP to this:
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_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr
instead of this:
_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr
This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26943 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 05:30:33 +00:00
Chris Lattner
e5ba580ab0
Add support for "ri" addressing modes where the immediate is a 14-bit field
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which is shifted left two bits before use. Instructions like STD use this
addressing mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26942 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 05:26:03 +00:00
Chris Lattner
eb8b09f69f
Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26935 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-22 01:44:36 +00:00
Chris Lattner
9b3bd467d0
These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26930 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-21 20:51:05 +00:00
Chris Lattner
f3ce43210a
Don't emit pseudo instructions!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26926 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-21 20:19:37 +00:00
Nate Begeman
c0a8b6df2a
Update readme
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26924 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-21 18:58:20 +00:00
Chris Lattner
13feb58aa1
Print absolute memory references like this:
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lwz r2, 8(0)
instead of this:
lwz r2, 8(r0)
This fixes the llc/llc-beta failures on PPC last night.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26922 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-21 17:21:13 +00:00
Chris Lattner
8151914321
With Evan's latest tblgen patch, this code is obsolete, thanks Evan!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26917 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-21 06:37:40 +00:00
Chris Lattner
8593f9891d
When codegen'ing vector MUL using VFMADD, *add* the 0, don't *mul* the 0.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26913 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-21 00:51:38 +00:00
Chris Lattner
ef040dd4a3
minor note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26912 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-21 00:47:09 +00:00
Chris Lattner
d97964457e
Handle constant addresses more efficiently, folding the low bits into the
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disp field of the load/store if possible. This compiles
CodeGen/PowerPC/load-constant-addr.ll to:
_test:
lis r2, 2838
lfs f1, 26848(r2)
blr
instead of:
_test:
lis r2, 2838
ori r2, r2, 26848
lfs f1, 0(r2)
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26908 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-20 22:38:22 +00:00
Chris Lattner
23baa1b310
remove dead variable
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26907 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-20 22:37:23 +00:00
Chris Lattner
bd83afd3cd
Fix a couple of bugs in permute/splat generate, thanks to Nate for actually
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figuring these out! :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26904 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-20 18:26:51 +00:00
Chris Lattner
e376e00247
reenable this hack, the tblgen version isn't quite ready
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26902 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-20 17:54:43 +00:00
Chris Lattner
32f57d9e26
Fix the pattern for VADDUWM, add i32 splat
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26901 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-20 17:51:58 +00:00
Evan Cheng
e63d746ef6
Use tblgen'd VECTOR_SHUFFLE selection code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26900 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-20 08:14:16 +00:00