Commit Graph

5596 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
74dad551d8 Add a DAGCombine for transforming 128->256 casts into a simple
vxorps + vinsertf128 pair of instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135727 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 00:15:00 +00:00
Bruno Cardoso Lopes
dbd4fe2b0a - Register v16i16 as valid VR256 register class
- Add more bitcasts for v16i16
- Since 135661 and 135662 already added the splat logic,
just add one more splat test for v16i16

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135663 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 02:24:08 +00:00
Bruno Cardoso Lopes
65b74e1d00 Add support for 256-bit versions of VPERMIL instruction. This is a new
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:

Instead of:
  vextractf128  $0, %ymm0, %xmm0
  punpcklbw %xmm0, %xmm0
  punpckhbw %xmm0, %xmm0
  vinsertf128 $0, %xmm0, %ymm0, %ymm1
  vinsertf128 $1, %xmm0, %ymm1, %ymm0
  vextractf128  $1, %ymm0, %xmm1
  shufps  $1, %xmm1, %xmm1
  movss %xmm1, 28(%rsp)
  movss %xmm1, 24(%rsp)
  movss %xmm1, 20(%rsp)
  movss %xmm1, 16(%rsp)
  vextractf128  $0, %ymm0, %xmm0
  shufps  $1, %xmm0, %xmm0
  movss %xmm0, 12(%rsp)
  movss %xmm0, 8(%rsp)
  movss %xmm0, 4(%rsp)
  movss %xmm0, (%rsp)
  vmovaps (%rsp), %ymm0
We get:
  vextractf128  $0, %ymm0, %xmm0
  punpcklbw %xmm0, %xmm0
  punpckhbw %xmm0, %xmm0
  vinsertf128 $0, %xmm0, %ymm0, %ymm1
  vinsertf128 $1, %xmm0, %ymm1, %ymm0
  vpermilps $85, %ymm0, %ymm0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135662 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 01:55:47 +00:00
Devang Patel
4ec14b0dee While emitting constant value, look through derived type and use underlying basic type to determine size and signness of the constant value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135627 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 21:57:04 +00:00
Eli Friedman
0381c21d2d PR10421: Fix a straightforward bug in the widening logic for CONCAT_VECTORS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135595 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 18:14:33 +00:00
Evan Cheng
e76a33b956 Add MCObjectFileInfo and sink the MCSections initialization code from
TargetLoweringObjectFileImpl down to MCObjectFileInfo.

TargetAsmInfo is done to one last method. It's *almost* gone!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135569 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 05:58:47 +00:00
Eric Christopher
03c45f60f3 New pointer rotate test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135562 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 03:09:11 +00:00
Akira Hatanaka
db54826f20 Lower memory barriers to sync instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135537 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 23:30:50 +00:00
Evan Cheng
70955c2d12 Fix an obvious typo that's preventing x86 (32-bit) from using .literal16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135535 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 23:14:32 +00:00
Akira Hatanaka
cc7ecc7290 Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or
ANDi, when the instruction does not have any immediate operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135520 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 20:34:00 +00:00
Akira Hatanaka
70564a9c19 Remove redundant instructions.
- In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the
  instruction being expanded, instead of masking it in thisMBB. 
- Remove redundant Or in EmitAtomicCmpSwap. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135495 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 18:14:26 +00:00
Richard Osborne
c8007ab582 Add intrinsics for the zext / sext instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135476 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 13:28:50 +00:00
Richard Osborne
829bef1a46 Add intrinsics for the testct, testwct instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135475 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 13:00:40 +00:00
Richard Osborne
dee3dd9129 Add intrinsics for the peek and endin instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135474 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 12:50:25 +00:00
Evan Cheng
439661395f Introduce MCCodeGenInfo, which keeps information that can affect codegen
(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135468 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 06:37:02 +00:00
Devang Patel
497a397f3e Revert r135423.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135454 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 00:28:24 +00:00
Eli Friedman
3a594f4876 FileCheck-ize a couple tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135427 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18 21:23:42 +00:00
Devang Patel
1360bc8eb0 During bottom up fast-isel, instructions emitted to materalize registers are at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases.
[take 2]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135423 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18 20:55:23 +00:00
Akira Hatanaka
a921164f39 Do not treat atomic.load.sub differently than other atomic binary intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135418 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18 19:58:59 +00:00
Akira Hatanaka
0d7d0b5cb7 Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from
moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135415 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18 18:52:12 +00:00
Jakob Stoklund Olesen
fc47933db5 Fix a crash when building 177.mesa for armv6.
When splitting a live range immediately before an LDR_POST instruction
that redefines the address register, make sure to use the correct value
number in leaveIntvBefore.

We need the value number entering the instruction.

<rdar://problem/9793765>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135413 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18 18:47:13 +00:00
Bruno Cardoso Lopes
3aaa010ece Add AVX 128-bit sqrt versions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135404 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18 17:51:40 +00:00
Nick Lewycky
b8c129ea66 Delete empty unused file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135379 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18 05:54:06 +00:00
Bruno Cardoso Lopes
4201ecae92 Add AVX 128-bit patterns for sint_to_fp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135332 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-16 00:50:20 +00:00
Bruno Cardoso Lopes
5bc37dd131 Fix a couple of things:
1) Make non-legal 256-bit loads to be promoted to v4i64. This lets us
canonize the loads and handle things the same way we use to handle
for 128-bit registers. Despite of what one of the removed comments
explained, the load promotion would not mess with VPERM, it's only a
matter of doing the appropriate bitcasts when this instructions comes
to be introduced. Also make LOAD v8i32 legal.

2) Doing 1) exposed two bugs:
- v4i64 was being promoted to itself for several opcodes (introduced
in r124447 by David Greene) causing endless recursion and the stack to
explode.
- there was no support for allOnes BUILD_VECTORs and ANDNP would fail to
match because it was generating early target constant pools during
lowering.

3) The testcases are already checked-in, doing 1) exposed the
bugs in the current testcases.

4) Tidy up code to be more clear and explicit about AVX.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135313 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-15 22:24:33 +00:00
Owen Anderson
43967a97cf Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135290 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-15 18:46:47 +00:00
Eric Christopher
5427edeb68 Check register class matching instead of width of type matching
when determining validity of matching constraint. Allow i1
types access to the GR8 reg class for x86.

Fixes PR10352 and rdar://9777108

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135180 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 20:13:52 +00:00
Bruno Cardoso Lopes
62f67f86fe Add 256-bit load/store recognition and matching in several places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135171 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 18:50:58 +00:00
Eric Christopher
2b88e8fbfe Add a testcase for r135123.
Part of rdar://9761830

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135133 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 06:23:09 +00:00
Benjamin Kramer
3ff25514ce Don't emit a bit test if there is only one case the test can yield false. A simple SETNE is sufficient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135126 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 01:38:42 +00:00
Bruno Cardoso Lopes
53c95880f0 We already support 256-bit packed ADD, SUB, DIV, MUL. Add testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135099 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:28:55 +00:00
Bruno Cardoso Lopes
466b022c99 Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A more
general version of X86ISD::ANDNP also opened the room for a little bit
of refactoring.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135088 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 21:36:51 +00:00
Eli Friedman
2a01946de4 Make sure we don't combine a large displacement and a frame index in the same addressing mode on x86-64. It can overflow, leading to a crash/miscompile.
<rdar://problem/9763308>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135084 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 21:29:53 +00:00
Bruno Cardoso Lopes
61905f0139 AVX Codegen support for 256-bit versions of vandps, vandpd, vorps, vorpd, vxorps, vxorpd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135023 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 01:15:33 +00:00
Evan Cheng
e721f5c8d3 Improve codegen for select's:
if (x != 0) x = 1
if (x == 1) x = 1

Previous codegen looks like this:
        mov     r1, r0
        cmp     r1, #1
        mov     r0, #0
        moveq   r0, #1

The naive lowering select between two different values. It should recognize the
test is equality test so it's more a conditional move rather than a select:
        cmp     r0, #1
        movne   r0, #0

rdar://9758317


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135017 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 00:42:17 +00:00
Jim Grosbach
92bf81ddd0 Improve test cases from r134746.
Use memory barriers to force if-conversion off for these tests instead of
the internal llc command line option ifcvt-limit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-12 16:06:01 +00:00
Andrew Trick
b9484cafcc Comment correction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134958 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-12 03:39:22 +00:00
Jim Grosbach
589130fac1 Simplify printing of ARM shifted immediates.
Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
 displayed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134902 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 16:48:36 +00:00
NAKAMURA Takumi
fecdc98390 test/CodeGen/PowerPC/vector.ll: Tweak redirection >%t >%t to >%t >>%t. See also r134814 (test/CodeGen/X86/vector.ll).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134900 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 16:21:52 +00:00
Cameron Zwarich
ce3a9f51ce Add a missing test for r134882.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134889 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 08:35:17 +00:00
Chris Lattner
1afcace3a3 Land the long talked about "type system rewrite" patch. This
patch brings numerous advantages to LLVM.  One way to look at it
is through diffstat:
 109 files changed, 3005 insertions(+), 5906 deletions(-)

Removing almost 3K lines of code is a good thing.  Other advantages
include:

1. Value::getType() is a simple load that can be CSE'd, not a mutating
   union-find operation.
2. Types a uniqued and never move once created, defining away PATypeHolder.
3. Structs can be "named" now, and their name is part of the identity that
   uniques them.  This means that the compiler doesn't merge them structurally
   which makes the IR much less confusing.
4. Now that there is no way to get a cycle in a type graph without a named
   struct type, "upreferences" go away.
5. Type refinement is completely gone, which should make LTO much MUCH faster
   in some common cases with C++ code.
6. Types are now generally immutable, so we can use "Type *" instead 
   "const Type *" everywhere.

Downsides of this patch are that it removes some functions from the C API,
so people using those will have to upgrade to (not yet added) new API.  
"LLVM 3.0" is the right time to do this.

There are still some cleanups pending after this, this patch is large enough
as-is.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134829 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 17:41:24 +00:00
Chris Lattner
5445ecdf69 more tests not making the jump into the brave new world.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134820 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 16:57:10 +00:00
NAKAMURA Takumi
9eb36758ac test/CodeGen/X86/vector.ll: Tweak temporary output to appease Win32 hosts.
With Lit (not bash) in a test, multiple redirects >%t might open(%t, "w") multiple. It can be avoided if latter redirect is >>%t.

It might work even if ">/dev/null" were used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134814 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 10:22:28 +00:00
Jakob Stoklund Olesen
56573cc1ae Hoist spills within a basic block.
Try to move spills as early as possible in their basic block. This can
help eliminate interferences by shortening the live range being
spilled.

This fixes PR10221.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134776 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 00:25:03 +00:00
Evan Cheng
f0b3c12919 Fix broken x86_64 tests which specify non-64-bit cpu's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134756 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 22:29:33 +00:00
Eli Friedman
f06ff4eae3 Default 64-bit target features and SSE2 on when a triple specifies x86-64. Clean up all the other hacks which are now unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134753 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 22:16:47 +00:00
Jim Grosbach
25e6d48220 Make tBX_RET and tBX_RET_vararg predicable.
The normal tBX instruction is predicable, so there's no reason the
pseudos for using it as a return shouldn't be. Gives us some nice code-gen
improvements as can be seen by the test changes. In particular, several
tests now have to disable if-conversion because it works too well and defeats
the test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134746 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 21:50:04 +00:00
Julien Lerouge
f29608267b Add _allrem, _aullrem and _allmul to the runtime for MSVC.
http://llvm.org/bugs/show_bug.cgi?id=10305


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134744 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 21:40:25 +00:00
Cameron Zwarich
33390848a7 Add an intrinsic and codegen support for fused multiply-accumulate. The intent
is to use this for architectures that have a native FMA instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134742 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 21:39:21 +00:00
Jakob Stoklund Olesen
51458ed09e Be more aggressive about following hints.
RAGreedy::tryAssign will now evict interference from the preferred
register even when another register is free.

To support this, add the EvictionCost struct that counts how many hints
are broken by an eviction. We don't want to break one hint just to
satisfy another.

Rename canEvict to shouldEvict, and add the first bit of eviction policy
that doesn't depend on spill weights: Always make room in the preferred
register as long as the evictees can be split and aren't already
assigned to their preferred register.

Also make the CSR avoidance more accurate. When looking for a cheaper
register it is OK to use a new volatile register. Only CSR aliases that
have never been used before should be avoided.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134735 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 20:46:18 +00:00