Daniel Sanders
2b9c11c071
[mips][sched] Split IIFmoveC1 into II_M[FT]C1, II_M[FT]HC1, II_DM[FT]C1
...
No functional change since the InstrItinData's have been duplicated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199748 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 15:03:52 +00:00
Daniel Sanders
49671f1b1a
[mips][sched] Split IIFStore into II_S[WD]C1, and II_S[WDU]XC1
...
No functional change since the InstrItinData's have been duplicated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199747 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 14:50:20 +00:00
Daniel Sanders
dc5734786a
[mips][sched] Split IIFLoad into II_L[WD]C1, and II_L[WDU]XC1
...
No functional change since the InstrItinData's have been duplicated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199743 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 13:59:56 +00:00
Daniel Sanders
faacfecf60
[mips][sched] Renamed II_FsqrtSingle and II_FsqrtDouble to II_SQRT_S and II_SQRT_D respectively
...
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199741 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 13:36:45 +00:00
Daniel Sanders
fa458d8ad2
[mips][sched] Renamed II_FdivSingle and II_FdivDouble to II_DIV_S and II_DIV_D respectively
...
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199738 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 13:22:08 +00:00
Daniel Sanders
be0843e767
[mips][sched] Split IIFmulDouble into II_MUL_D, II_MADD_D, II_MSUB_D, II_NMADD_D, and II_NMSUB_S
...
No functional change since the InstrItinData's have been duplicated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199737 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 13:07:31 +00:00
Daniel Sanders
c55cf21ac0
[mips][sched] Split IIFmulSingle into II_MUL_S, II_MADD_S, II_MSUB_S, II_NMADD_S, and II_NMSUB_S
...
No functional change since the InstrItinData's have been duplicated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199734 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 12:51:44 +00:00
Daniel Sanders
b029a0ec6a
[mips][sched] Split IIFadd into II_ADD_[DS], II_SUB_[DS]
...
No functional change since the InstrItinData's have been duplicated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199732 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 12:38:07 +00:00
Daniel Sanders
65d38c3fcd
[mips][sched] Split IIFcmp into II_C_CC_[SD]
...
No functional change since the InstrItinData's have been duplicated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199728 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 11:42:48 +00:00
Daniel Sanders
0e65e8c2a7
[mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD]
...
No functional change since the InstrItinData's have been duplicated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199727 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 11:28:03 +00:00
Daniel Sanders
c2e835fd7e
[mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEG
...
No functional change since the InstrItinData's have been duplicated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199722 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-21 10:56:23 +00:00
Zoran Jovanovic
ae3597c141
Support for microMIPS FPU instructions 2.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198009 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-25 10:09:27 +00:00
Zoran Jovanovic
1ef2ca6994
Support for microMIPS FPU instructions 1.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197815 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-20 15:44:08 +00:00
Vladimir Medic
e925f7dbbf
This patch implements Mips load/store instructions from/to coprocessor 2. Test cases are added.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190780 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-16 10:29:42 +00:00
Akira Hatanaka
3e6758541b
[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double
...
precision loads and stores as well as reg+imm double precision loads and stores.
Previously, expansion of loads and stores was done after register allocation,
but now it takes place during legalization. As a result, users will see double
precision stores and loads being emitted to spill and restore 64-bit FP registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190235 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-07 00:52:30 +00:00
Akira Hatanaka
a796d90c0e
[mips] Use ptr_rc to simplify definitions of base+index load/store instructions.
...
Also, fix predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189432 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-28 00:55:15 +00:00
Akira Hatanaka
b1f4f120a5
[mips] Add support for mfhc1 and mthc1.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188848 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 23:47:25 +00:00
Akira Hatanaka
c89cb45ecb
[mips] Remove predicates that were incorrectly or unnecessarily added.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188845 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 23:21:55 +00:00
Akira Hatanaka
3531db14c6
[mips] Define register class FGRH32 for the high half of the 64-bit floating
...
point registers. We will need this register class later when we add
definitions for instructions mfhc1 and mthc1. Also, remove sub-register indices
sub_fpeven and sub_fpodd and use sub_lo and sub_hi instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188842 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 22:58:56 +00:00
Akira Hatanaka
a98a486ad1
[mips] Resolve register classes dynamically using ptr_rc to reduce the number of
...
load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188830 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-20 21:08:22 +00:00
Akira Hatanaka
491d04969d
[mips] Rename accumulator register classes and FP register operands.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188020 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-08 21:54:26 +00:00
Akira Hatanaka
1858786285
[mips] Rename register classes CPURegs and CPU64Regs.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-06 23:08:38 +00:00
Vladimir Medic
b67775df0c
This patch implements parsing of mips FCC register operands. The example instructions have been added to test files.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187410 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-30 10:12:14 +00:00
Akira Hatanaka
407883b69b
[mips] Fix FP conditional move instructions to have explicit FP condition code
...
register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187242 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 20:51:20 +00:00
Akira Hatanaka
83d8ef133b
[mips] Fix FP branch instructions to have explicit FP condition code register
...
operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187238 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 20:13:47 +00:00
Akira Hatanaka
9955cb931b
[mips] Fix floating point branch, comparison, and conditional move instructions
...
to have register FCC0 (the first floating point condition code register) in
their Uses/Defs list.
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187233 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 19:01:56 +00:00
Akira Hatanaka
da218210f7
[mips] Delete MFC1_FT_CCR, MTC1_FT_CCR and MOVCCRToCCR.
...
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186642 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 01:19:52 +00:00
Vladimir Medic
0884836277
This patch represents Mips utilization of r186388 code that alows asm matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186397 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-16 10:07:14 +00:00
Akira Hatanaka
a66aacf6d7
[mips] Add new InstrItinClasses for move from/to coprocessor instructions and
...
floating point loads and stores.
No changes in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185399 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-02 00:00:02 +00:00
Vladimir Medic
90b1086b93
This patch introduces RegisterOperand class into Mips FPU instruction definitions and adds dedicated parser methods to MipsAsmParser. It is the first in a series of patches that should fix the problems with parsing Mips FPU instructions and optimize the code in MipsAsmParser.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184716 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 10:05:34 +00:00
Akira Hatanaka
ae7e7cb3d3
[mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr).
...
Previously, three instructions were needed:
trunc.w.s $f0, $f2
mfc1 $4, $f0
sw $4, 0($2)
Now we need only two:
trunc.w.s $f0, $f2
swc1 $f0, 0($2)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182053 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16 21:17:15 +00:00
Akira Hatanaka
ec4db6ab5f
[mips] Fix instruction selection pattern for sint_to_fp node to avoid emitting an
...
invalid instruction sequence.
Rather than emitting an int-to-FP move instruction and an int-to-FP conversion
instruction during instruction selection, we emit a pseudo instruction which gets
expanded post-RA. Without this change, register allocation can possibly insert a
floating point register move instruction between the two instructions, which is not
valid according to the ISA manual.
mtc1 $f4, $4 # int-to-fp move instruction.
mov.s $f2, $f4 # move contents of $f4 to $f2.
cvt.s.w $f0, $f2 # int-to-fp conversion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182042 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16 19:48:37 +00:00
Akira Hatanaka
afcca55ff9
[mips] Fix indentation.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182036 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16 18:42:42 +00:00
Akira Hatanaka
42f562a169
[mips] Add option -mno-ldc1-sdc1.
...
This option is used when the user wants to avoid emitting double precision FP
loads and stores. Double precision FP loads and stores are expanded to single
precision instructions after register allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181718 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-13 18:23:35 +00:00
Akira Hatanaka
175f0fd99a
[mips] Define reg+imm load/store pattern templates.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178407 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-30 02:01:48 +00:00
Akira Hatanaka
dc2f792740
[mips] Split SelectAddr, which was used to match address patterns, into two
...
functions. Set AddedComplexity to determine the order in which patterns are
matched.
This simplifies selection of floating point loads/stores.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175300 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-15 21:20:45 +00:00
Akira Hatanaka
d2047c6001
[mips] Set flag neverHasSideEffects flag on some of the floating point instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173401 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-25 00:20:39 +00:00
Jack Carter
ec3199f675
This patch tackles the problem of parsing Mips
...
register names in the standalone assembler llvm-mc.
Registers such as $A1 can represent either a 32 or
64 bit register based on the instruction using it.
In addition, based on the abi, $T0 can represent different
32 bit registers.
The problem is resolved by the Mips specific AsmParser
td definitions changing to work together. Many cases of
RegisterClass parameters are now RegisterOperand.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172284 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-12 01:03:14 +00:00
Akira Hatanaka
1e7739f614
[mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass
...
parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170661 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20 04:20:09 +00:00
Akira Hatanaka
c567b1cd0d
[mips] Delete all floating point instruction classes that are no longer used.
...
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170084 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 02:05:02 +00:00
Akira Hatanaka
b573539c6b
[mips] Modify definitions of floating point comparison instructions.
...
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170077 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 01:34:09 +00:00
Akira Hatanaka
89828a6a56
[mips] Modify definitions of floating point branch instructions.
...
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170076 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 01:32:36 +00:00
Akira Hatanaka
2b1a50cfdb
[mips] Modify definitions of floating point indexed load and store instructions.
...
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170075 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 01:30:49 +00:00
Akira Hatanaka
b2c68ddaab
[mips] Modify definitions of floating point multiply-add/sub instructions.
...
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170073 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 01:27:48 +00:00
Akira Hatanaka
6f94eb3512
[mips] Modify definitions of floating point load and store instructions.
...
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170072 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 01:24:00 +00:00
Akira Hatanaka
be9f72d2d8
[mips] Modify definitions of move from/to coprocessor instructions.
...
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170071 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 01:16:49 +00:00
Akira Hatanaka
4b921416b4
[mips] Modify definitions of two register operand floating point instructions.
...
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170069 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 01:14:07 +00:00
Akira Hatanaka
82fdad75f7
[mips] Modify definitions of three register operand floating point instructions
...
and separate encoding information from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170066 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 01:07:37 +00:00
Akira Hatanaka
10bd726459
[mips] Move classes that do not belong in MipsInstrFormats.td into
...
MipsInstrFPU.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170061 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 00:49:23 +00:00
Akira Hatanaka
2f3e06399a
[mips] Set isCommutable flag in a more explicit way.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170060 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-13 00:46:23 +00:00