Johnny Chen
157536b1fb
Fix SRS/SRSW encoding bits.
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rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS
Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with
http://llvm.org/viewvc/llvm-project?view=rev&revision=128859 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128864 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05 00:16:18 +00:00
Johnny Chen
597028cc28
A8.6.105 MUL
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Inst{15-12} should be specified as 0b0000.
rdar://problem/9231168 ARM disassembler discrepancy: erroneously accepting MUL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128862 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 23:57:05 +00:00
Johnny Chen
670a456c83
RFE encoding should also specify the "should be" encoding bits.
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rdar://problem/9229922 ARM disassembler discrepancy: erroneously accepting RFE
Also LDC/STC instructions are predicated while LDC2/STC2 instructions are not, fixed while
doing regression testings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128859 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 23:39:08 +00:00
Joerg Sonnenberger
c15a91dfc8
Make OpcodeMask an unsigned long long literal to deal with overflow.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128847 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 21:38:17 +00:00
Johnny Chen
2d66cec9dd
Fix incorrect alignment for NEON VST2b32_UPD.
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rdar://problem/9225433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128841 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 20:35:31 +00:00
Jakob Stoklund Olesen
5fcb81dace
Insert code in the right location when lowering PowerPC atomics.
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This causes defs to dominate uses, no instructions after terminators, and other
goodness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128836 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 17:57:29 +00:00
Bruno Cardoso Lopes
ac79e4c82f
- Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT
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also fix the encoding of the later.
- Add a new encoding bit to describe the index mode used in AM3.
- Teach printAddrMode3Operand to check by the addressing mode which
index mode to print.
- Testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128832 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 17:18:19 +00:00
Akira Hatanaka
f49fde2877
Move transformation of JmpLink and related nodes done during instruction selection to Legalize phase.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128830 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 17:11:07 +00:00
Jakob Stoklund Olesen
cf3a74824f
PowerPC atomic pseudos clobber CR0, they don't read it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128829 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 17:07:09 +00:00
Jakob Stoklund Olesen
2684c5db84
Use X0 instead of R0 for the zero register on ppc64.
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The 32-bit R0 cannot be used where a 64-bit register is expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128828 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 17:07:06 +00:00
Joerg Sonnenberger
4a8ac8de1d
Add support for the VIA PadLock instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128826 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 16:58:13 +00:00
Joerg Sonnenberger
229e4523f2
Expand Op0Mask by one bit in preparation for the PadLock prefixes.
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Define most shift masks incrementally to reduce the redundant
hard-coding. Introduce new shift for the VEX flags to replace the
magic constant 32 in various places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128822 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 15:58:30 +00:00
Jay Foad
3e2f74e6d6
Remove some support for ReturnInsts with multiple operands, and for
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returning a scalar value in a function whose return type is a single-
element structure or array.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128810 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-04 07:44:02 +00:00
Che-Liang Chiou
357be5e4ae
ptx: support setp's 4-operand format
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128767 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02 08:51:39 +00:00
Cameron Zwarich
4071a71112
Do some peephole optimizations to remove pointless VMOVs from Neon to integer
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registers that arise from argument shuffling with the soft float ABI. These
instructions are particularly slow on Cortex A8. This fixes one half of
<rdar://problem/8674845>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128759 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02 02:40:43 +00:00
Johnny Chen
04187ecd57
Fixed a bug in disassembly of STR_POST, where the immediate is the second operand in am2offset;
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instead of the second operand in addrmode_imm12.
rdar://problem/9225289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128757 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02 02:24:54 +00:00
Akira Hatanaka
ad8ffad60a
Undo changes mistakenly made in revision 128750.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128751 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02 00:26:12 +00:00
Akira Hatanaka
dc1652fd31
Insert space before ';' to prevent warnings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128750 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02 00:15:58 +00:00
Johnny Chen
103bf951a4
Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000.
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rdar://problem/9224276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128749 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 23:30:25 +00:00
Johnny Chen
6da3fe68c6
MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is UNPREDICTABLE.
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rdar://problem/9224120
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128748 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 23:15:50 +00:00
Johnny Chen
857b1939da
Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that
...
all the instruction have:
let Inst{31-27} = 0b1110; // non-predicated
Before, the ARM decoder was confusing:
> 0x40 0xf3 0xb8 0x80
as:
Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
adcs pc, r8, r0, asr #6
since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'.
Now, the AR decoder behaves correctly:
> 0x40 0xf3 0xb8 0x80
> END
Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt
Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------
adcshi pc, r8, r0, asr #6
>
rdar://problem/9223094
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128746 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 22:32:51 +00:00
Evan Cheng
0539c159fb
Avoid de-referencing pass beginning of a basic block. No small test case possible. rdar://9216009
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128743 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 22:09:28 +00:00
Akira Hatanaka
ad8180a0b8
Remove redundant code. There are assignments to variables Base and Offset right after the code that is removed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128742 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 21:56:02 +00:00
Akira Hatanaka
e2e436a6bc
Simplifies logic for printing target flags.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128741 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 21:41:06 +00:00
Owen Anderson
1721324d97
When the architecture is explicitly armv6 or thumbv6, we need to mark the object file appropriately.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128739 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 21:07:39 +00:00
Jim Grosbach
9a3507f091
LDRD/STRD instructions should print both Rt and Rt2 in the asm string.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128736 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 20:26:57 +00:00
Johnny Chen
ec30f6f5e5
Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction
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as invalid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128734 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 20:21:38 +00:00
Akira Hatanaka
a4485c4964
Modifies MipsAsmPrinter::isBlockOnlyReachableByFallthrough so that it handles delay slots correctly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128724 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 18:57:38 +00:00
Johnny Chen
5307da994a
Fix LDRi12 immediate operand, which was changed to be the second operand in $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm).
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rdar://problem/9219356
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128722 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 18:26:38 +00:00
Akira Hatanaka
20ada98de8
Add code for analyzing FP branches. Clean up branch Analysis functions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128718 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 17:39:08 +00:00
Benjamin Kramer
0e3ee43ea0
Initialize HasVMLxForwarding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128709 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 09:20:31 +00:00
Evan Cheng
8e23e815ad
Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs.
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rdar://8911343
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128696 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 00:42:02 +00:00
Matt Beaumont-Gay
e3662cca5d
Remove unused variables
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128692 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 00:06:01 +00:00
Bruno Cardoso Lopes
ae0855401b
Apply again changes to support ARM memory asm parsing. I removed
...
all LDR/STR changes and left them to a future patch. Passing all
checks now.
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 23:26:08 +00:00
Jakob Stoklund Olesen
1db952d0c6
Provide a legal pointer register class when targeting thumb1.
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The LocalStackSlotAllocation pass was creating illegal registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128687 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 23:02:15 +00:00
Evan Cheng
463d358f1d
Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier
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accumulator forwarding:
vadd d3, d0, d1
vmul d3, d3, d2
=>
vmul d3, d0, d2
vmla d3, d1, d2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128665 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 19:38:48 +00:00
Johnny Chen
a52d7da1d8
Fix single word and unsigned byte data transfer instruction encodings so that
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Inst{4} = 0.
rdar://problem/9213022
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128662 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 19:28:35 +00:00
Akira Hatanaka
1d6b38d9d3
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128650 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 18:26:17 +00:00
Johnny Chen
8901e6ff3d
Add BLXi to the instruction table for disassembly purpose.
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A8.6.23 BLX (immediate)
rdar://problem/9212921
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128644 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 17:53:50 +00:00
Bruno Cardoso Lopes
b41aaab5a1
Revert r128632 again, until I figure out what break the tests
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128635 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 15:54:36 +00:00
Richard Osborne
e8f3533323
Add XCore intrinsics for initializing / starting / synchronizing threads.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128633 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 15:13:13 +00:00
Bruno Cardoso Lopes
bcd3a9cd84
Reapply r128585 without generating a lib depedency cycle. An updated log:
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- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
{STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible.
- Move all instructions which use am2offset without a pattern to use
addrmode2.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128632 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 14:52:28 +00:00
Matt Beaumont-Gay
e4345c9977
Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and"
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This revision introduced a dependency cycle, as nlewycky mentioned by email.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128597 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-31 00:39:16 +00:00
Owen Anderson
6a7d36a320
Somehow we managed to forget to encode the lane index for a large swathe of NEON instructions. With this fix, the entire test-suite passes with the Thumb integrated assembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128587 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-30 23:45:29 +00:00
Evan Cheng
ee2e0e347e
Don't try to create zero-sized stack objects.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128586 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-30 23:44:13 +00:00
Bruno Cardoso Lopes
40829ed6f5
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
...
{STR,LDC}{2}_PRE.
- Fixed the encoding in some places.
- Some of those instructions were using am2offset and now use addrmode2.
Codegen isn't affected, instructions which use SelectAddrMode2Offset were not
touched.
- Teach printAddrMode2Operand to check by the addressing mode which index
mode to print.
- This is a work in progress, more work to come. The idea is to change places
which use am2offset to use addrmode2 instead, as to unify assembly parser.
- Add testcases for assembly parser
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128585 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-30 23:32:32 +00:00
Cameron Zwarich
c0e6d780cd
Add a ARM-specific SD node for VBSL so that forms with a constant first operand
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can be recognized. This fixes <rdar://problem/9183078>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128584 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-30 23:01:21 +00:00
Akira Hatanaka
81bd78b897
fixed typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128574 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-30 21:15:35 +00:00
Jay Foad
3ecfc861b4
Remove PHINode::reserveOperandSpace(). Instead, add a parameter to
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PHINode::Create() giving the (known or expected) number of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128537 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-30 11:28:46 +00:00
Evan Cheng
92e3916c3b
Add intrinsics @llvm.arm.neon.vmulls and @llvm.arm.neon.vmullu.* back. Frontends
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was lowering them to sext / uxt + mul instructions. Unfortunately the
optimization passes may hoist the extensions out of the loop and separate them.
When that happens, the long multiplication instructions can be broken into
several scalar instructions, causing significant performance issue.
Note the vmla and vmls intrinsics are not added back. Frontend will codegen them
as intrinsics vmull* + add / sub. Also note the isel optimizations for catching
mul + sext / zext are not changed either.
First part of rdar://8832507, rdar://9203134
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128502 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29 23:06:19 +00:00
Cameron Zwarich
3007d3331b
Add Neon SINT_TO_FP and UINT_TO_FP lowering from v4i16 to v4f32. Fixes
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<rdar://problem/8875309> and <rdar://problem/9057191>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128492 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29 21:41:55 +00:00
Owen Anderson
d0cfc99b30
Check early if this is an unsupported opcode, so that we can avoid needlessly instantiating the base register in some cases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128481 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29 20:27:38 +00:00
Johnny Chen
9eda569a74
A8.6.188 STC, STC2
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The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}.
rdar://problem/9200661
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128478 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29 19:49:38 +00:00
Owen Anderson
9eae80051b
Add safety check that didn't show up in testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128467 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29 17:42:25 +00:00
Owen Anderson
848b0c39b1
Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128461 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29 16:45:53 +00:00
Evan Cheng
78fe9ababe
Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
...
isel lowering to fold the zero-extend's and take advantage of no-stall
back to back vmul + vmla:
vmull q0, d4, d6
vmlal q0, d5, d6
is faster than
vaddl q0, d4, d5
vmovl q1, d6
vmul q0, q0, q1
This allows us to vmull + vmlal for:
f = vmull_u8( vget_high_u8(s), c);
f = vmlal_u8(f, vget_low_u8(s), c);
rdar://9197392
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128444 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-29 01:56:09 +00:00
Daniel Dunbar
a7b8c2b6a4
Integrated-As: Add support for setting the AllowTemporaryLabels flag via
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integrated-as.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128431 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-28 22:49:19 +00:00
Johnny Chen
d560a80925
Fix ARM disassembly for PLD/PLDW/PLI which suffers from code rot and add some test cases.
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Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128417 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-28 18:41:58 +00:00
Che-Liang Chiou
fb4a8344b6
ptx: clean up branch code a bit
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128405 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-28 10:23:13 +00:00
Benjamin Kramer
050db52276
Make helper static.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128338 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-26 12:38:19 +00:00
Johnny Chen
eca915fb52
Fixed the t2PLD and friends disassembly and add two test cases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-26 01:32:48 +00:00
Eric Christopher
29aeed1bf8
Fix the bfi handling for or (and a mask) (and b mask). We need the two
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masks to match inversely for the code as is to work. For the example given
we actually want:
bfi r0, r2, #1 , #1
not #0 , however, given the way the pattern is written it's not possible
at the moment.
Fixes rdar://9177502
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128320 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-26 01:21:03 +00:00
Johnny Chen
a2755b9829
Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode GPRRegClassID.
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Also add some test cases.
rdar://problem/9189829
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128304 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 22:19:07 +00:00
Johnny Chen
abeea57639
DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass. Add two test cases.
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rdar://problem/9182892
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128299 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 19:35:37 +00:00
Johnny Chen
ceceabd4b1
Modify DisassembleThumb2LdStEx() to be more robust/correct in light of recent change to
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t2LDREX/t2STREX instructions. Add two test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128293 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 18:29:49 +00:00
Benjamin Kramer
ef7b8d9e5a
Add a note.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128286 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 17:32:40 +00:00
Johnny Chen
6c3891067b
Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. Modify the disassembler to handle that.
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rdar://problem/9184053
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128285 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 17:31:16 +00:00
Johnny Chen
f14d5cf33a
Also need to handle invalid imod values for CPS2p.
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rdar://problem/9186136
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128283 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 17:03:12 +00:00
Jakob Stoklund Olesen
eb5067e0d9
Ignore special ARM allocation hints for unexpected register classes.
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Add an assertion to linear scan to prevent it from allocating registers outside
the register class.
<rdar://problem/9183021>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128254 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 01:48:18 +00:00
Johnny Chen
a7078c4f27
Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the register classes were changed),
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modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128252 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25 01:09:48 +00:00
Matt Beaumont-Gay
1866af4a98
Suppress an unused variable warning in -asserts builds
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128244 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 22:05:48 +00:00
Johnny Chen
c39b6271be
Handle the added VBICiv*i* NEON instructions, too.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128243 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 22:04:39 +00:00
Johnny Chen
8cb988686d
Plug a leak by ThumbDisassembler::getInstruction(), thanks to Benjamin Kramer!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128241 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 21:42:55 +00:00
Johnny Chen
9091bf25d9
T2 Load/Store Multiple:
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These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt. Also add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128240 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 21:36:56 +00:00
Benjamin Kramer
83ccbff84f
Plug a leak in the arm disassembler and put the tests back.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128238 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 21:14:28 +00:00
Bruno Cardoso Lopes
505f3cd296
Add asm parsing support w/ testcases for strex/ldrex family of instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128236 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 21:04:58 +00:00
Johnny Chen
e6d69e7dbe
ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled.
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Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128234 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 20:42:48 +00:00
Jim Grosbach
d31d304f83
Clean up assembly statement separator support.
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The MC asm lexer wasn't honoring a non-default (anything but ';') statement
separator. Fix that, and generalize a bit to support multi-character
statement separators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128227 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 18:46:34 +00:00
Johnny Chen
b4ac342ea0
The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.cpp to disassemble the
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VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function. Add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128226 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 18:40:38 +00:00
Johnny Chen
ce1868b21c
Add comments to the handling of opcode CPS3p to reject invalid instruction encoding,
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a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128220 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 17:04:22 +00:00
NAKAMURA Takumi
a2e0762fae
Target/X86: [PR8777][PR8778] Tweak alloca/chkstk for Windows targets.
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FIXME: Some cleanups would be needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128206 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 07:07:00 +00:00
Evan Cheng
d700617193
Nasty bug in ARMBaseInstrInfo::produceSameValue(). The MachineConstantPoolEntry
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entries being compared may not be ARMConstantPoolValue. Without checking
whether they are ARMConstantPoolValue first, and if the stars and moons
are aligned properly, the equality test may return true (when the first few
words of two Constants' values happen to be identical) and very bad things can
happen.
rdar://9125354
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128203 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 06:20:03 +00:00
Johnny Chen
e4000595fb
CPS3p: Let's reject impossible imod values by returning false from the DisassembleMiscFrm() function.
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Fixed rdar://problem/9179416 ARM disassembler crash: "Unknown imod operand" (fuzz testing)
Opcode=98 Name=CPS3p Format=ARM_FORMAT_MISCFRM(26)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
Before:
cpsUnknown imod operand
UNREACHABLE executed at /Volumes/data/lldb/llvm/lib/Target/ARM/InstPrinter/../ARMBaseInfo.h:123!
After:
/Volumes/data/Radar/9179416/mc-input-arm.txt:1:1: warning: invalid instruction encoding
0x93 0x1c 0x2 0xf1
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128192 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 02:24:36 +00:00
Johnny Chen
3d793962be
Load/Store Multiple:
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These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt. Also add two test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128191 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 01:40:42 +00:00
Johnny Chen
571f290376
STRT and STRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821).
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We now tag them as IndexModePost.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 01:07:26 +00:00
Johnny Chen
2abc9d2444
The r128103 fix to cope with the removal of addressing modes from the MC instructions
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were incomplete. The assert stmt needs to be updated and the operand index incrment is wrong.
Fix the bad logic and add some sanity checking to detect bad instruction encoding;
and add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128186 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-24 00:28:38 +00:00
Devang Patel
36dca60f5c
Enable GlobalMerge on darwin.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128183 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-23 23:34:19 +00:00
Andrew Trick
f6c39412dd
Revert r128175.
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I'm backing this out for the second time. It was supposed to be fixed by r128164, but the mingw self-host must be defeating the fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128181 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-23 23:11:02 +00:00
Evan Cheng
2c33915628
Cmp peephole optimization isn't always safe for signed arithmetics.
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int tries = INT_MAX;
while (tries > 0) {
tries--;
}
The check should be:
subs r4, #1
cmp r4, #0
bgt LBB0_1
The subs can set the overflow V bit when r4 is INT_MAX+1 (which loop
canonicalization apparently does in this case). cmp #0 would have cleared
it while not changing the N and Z bits. Since BGT is dependent on the V
bit, i.e. (N == V) && !Z, it is not safe to eliminate the cmp #0 .
rdar://9172742
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128179 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-23 22:52:04 +00:00
Andrew Trick
d8fa01fbd7
Reapply Eli's r127852 now that the pre-RA scheduler can spill EFLAGS.
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(target-specific branchless method for double-width relational comparisons on x86)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128175 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-23 22:16:02 +00:00
Owen Anderson
741ad15e26
The high bit of a Thumb2 ADR's offset is stored in bit 26, not bit 25.
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This fixes 464.h264ref with the integrated assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128172 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-23 22:03:44 +00:00
Justin Holewinski
d662576671
PTX: Improve support for 64-bit addressing
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- Fix bug in ADDRrr/ADDRri/ADDRii selection for 64-bit addresses
- Add comparison selection for i64
- Add zext selection for i32 -> i64
- Add shl/shr/sha support for i64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128153 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-23 16:58:51 +00:00
Johnny Chen
c59c87c322
For ARM Disassembler, start a newline to dump the opcode and friends for an instruction.
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Change inspired by llvm-bug 9530 submitted by Jyun-Yan You.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128122 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 23:49:46 +00:00
Johnny Chen
27c6baeca2
LDRT and LDRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821).
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We now tag them as IndexModePost.
This fixed http://llvm.org/bugs/show_bug.cgi?id=9530 .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128113 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 22:28:49 +00:00
Eli Friedman
97ab5803df
A bit more analysis of a memset-related README entry.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128107 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 20:49:53 +00:00
Johnny Chen
758df29741
A8.6.399 VSTM:
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VFP Load/Store Multiple Instructions used to embed the IA/DB addressing mode within the
MC instruction; that has been changed so that now, for example, VSTMDDB_UPD and VSTMDIA_UPD
are two instructions. Update the ARMDisassemblerCore.cpp's DisassembleVFPLdStMulFrm()
to reflect the change.
Also add a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128103 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 20:00:10 +00:00
Eric Christopher
7244d7cbce
Migrate the fix in r128041 to ARM's fastisel support as well.
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Fixes rdar://9169640
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128100 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 19:39:17 +00:00
Bruno Cardoso Lopes
026a42b170
Change MRC and MRC2 instructions to model the output register properly
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128085 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 15:06:24 +00:00
Che-Liang Chiou
5e0872e099
ptx: add analyze/insert/remove branch
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128084 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 14:12:00 +00:00
Matt Beaumont-Gay
ddb657c63d
Avoid -Wunused-variable in -asserts builds
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128048 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 00:37:28 +00:00