Bruno Cardoso Lopes
8400bfe9fa
While I'm here, remove the "_alt" hacks to a series of INSERT_SUBREG and
...
also add the AVX versions of the 128-bit patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137685 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 23:36:51 +00:00
Bruno Cardoso Lopes
1deddbbd56
Reorder declarations of vmovmskp* and also put the necessary AVX
...
predicate and TB encoding fields. This fix the encoding for the
attached testcase. This fixes PR10625.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137684 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 23:36:45 +00:00
Jim Grosbach
19cb7f491f
MCTargetAsmParser target match predicate support.
...
Allow a target assembly parser to do context sensitive constraint checking
on a potential instruction match. This will be used, for example, to handle
Thumb2 IT block parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 23:03:29 +00:00
Bruno Cardoso Lopes
50b37c7920
Fix PR10656. It's only profitable to use 128-bit inserts and extracts
...
when AVX mode is one. Otherwise is just more work for the type
legalizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137661 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 21:45:54 +00:00
Owen Anderson
c537f3be0c
Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
...
Patch by James Molloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137647 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 20:51:32 +00:00
Owen Anderson
92be8ab6a4
Remove dead classes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137643 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 20:11:11 +00:00
Owen Anderson
5df7ef6cdb
Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137641 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 20:08:25 +00:00
Owen Anderson
305e046e53
Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137636 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 19:00:06 +00:00
Owen Anderson
7a2e1770ea
Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137635 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 18:44:44 +00:00
Jim Grosbach
8757a4c6ab
Update comment to reflect MC target machine refactor.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137615 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 16:52:24 +00:00
Bob Wilson
7dcd04abe0
Expand VMOVQQQQ pseudo instructions.
...
Apparently we never added code to expand these pseudo instructions, and in
over a year, no one has noticed. Our register allocator must be awesome!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137551 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-13 05:14:55 +00:00
Jim Grosbach
10342123ad
ARM STR_POST_IMM offset encoding fix in load/store optimizer.
...
Tidy up the code a bit and push the definition of the value next to the uses
to try to minimize this sort of issue from arising again while I'm at it.
rdar://9945172
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 22:20:41 +00:00
Bruno Cardoso Lopes
4002d7e1e6
Fix comment!
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137521 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 21:54:42 +00:00
Bruno Cardoso Lopes
53cae1362d
The VPERM2F128 is a AVX instruction which permutes between two 256-bit
...
vectors. It operates on 128-bit elements instead of regular scalar
types. Recognize shuffles that are suitable for VPERM2F128 and teach
the x86 legalizer how to handle them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137519 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 21:48:26 +00:00
Bruno Cardoso Lopes
fa2f4fd9a2
Move code around and add comments
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 21:48:22 +00:00
Akira Hatanaka
5c21c9e78e
Define unaligned load and store.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137515 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 21:30:06 +00:00
Jim Grosbach
4dfe220ad5
ARM expansion of pre-indexed store pseudos should maintain memoperands.
...
Partial fix for rdar://9945172.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137513 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 21:02:34 +00:00
Owen Anderson
0d09499cf3
Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137502 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 20:36:11 +00:00
Owen Anderson
79628e92e1
Fix decoding of ARM-mode STRH.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137499 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 20:02:50 +00:00
Owen Anderson
6368119c25
Specify fixed bit in the LDRBT encoding, which allows us to distinguish it from certain USAT16 encodings.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137494 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 19:41:29 +00:00
Owen Anderson
7cdbf086e4
Fix decoding of pre-indexed stores.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137487 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 18:12:39 +00:00
Akira Hatanaka
0285e7d1c1
When constant double 0.0 is lowered, make sure 0 is copied directly from an
...
integer register to a floating point register. It is not valid to interpret
the value of a floating pointer register as part of a double precision
floating point value after a single precision floating point computational
or move instruction stores its result to the register.
- In the test case, the following code is generated before this patch is
applied:
mtc1 $zero, $f2 ; unformatted copy to $f2
mov.s $f0, $f2 ; $f0 is in single format
sdc1 $f12, 0($sp)
mov.s $f1, $f2 ; $f1 is in single format
c.eq.d $f12, $f0 ; $f0 cannot be interpreted as double
- The following code is generated after this patch is applied:
mtc1 $zero, $f0 ; unformatted copy to $f0
mtc1 $zero, $f1 ; unformatted copy to $f1
c.eq.d $f12, $f0 ; $f0 can be interpreted as double
Bhanu Chetlapalli and Chris Dearman at MIPS technologies reported this bug and
provided the test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137484 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 18:09:59 +00:00
Chris Lattner
c4d0e9fbdd
switch to the new struct apis.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137481 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 18:07:07 +00:00
Owen Anderson
3f3570a38b
Separate decoding for STREXD and LDREXD to make each work better.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137476 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 17:58:32 +00:00
Duncan Sands
1f6a329f79
Silence a bunch (but not all) "variable written but not read" warnings
...
when building with assertions disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137460 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 14:54:45 +00:00
Andrew Trick
32a183c84a
findDeadCallerSavedReg fix: Missing NULL terminator in register arrays.
...
Fix by Ivan Baev. Sorry I don't have a unit test, but the fix is obvious so I don't want to delay it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137404 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 00:49:19 +00:00
Jim Grosbach
857e1a7b3f
ARM vector compare to zero instruction assembly parsing support.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137389 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 23:51:13 +00:00
Akira Hatanaka
9029cf20e1
Enclose directive .cprestore with .set macro and nomacro to silence assembler
...
warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137378 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:42:31 +00:00
Jim Grosbach
d30970fb6c
Remove no-longer-true comments. These are for the assembler, also.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137375 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:30:30 +00:00
Jim Grosbach
342ebd5f38
ARM STRT assembly parsing and encoding.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137372 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:18:00 +00:00
Owen Anderson
41ff834e91
Make the USAT16 operand decoder auto-generate-able.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137371 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:10:11 +00:00
Owen Anderson
adf2b094cb
Add another accidentally omitted predicate operand.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137370 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:08:38 +00:00
Owen Anderson
1fb6673bc2
Add missing predicate operand on SMLA and friends.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137368 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:05:38 +00:00
Jim Grosbach
dd32ba337a
ARM load shifted register pre-index fix shift value asm parser encoding.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137367 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:05:09 +00:00
Owen Anderson
796d6b7602
Handle new register classes in Thumb2 mode. Should fix the ARM buildbots.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137364 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:52:38 +00:00
Owen Anderson
05b0c9f41e
Making SEL decodings auto-generate-able.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137363 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:50:56 +00:00
Bruno Cardoso Lopes
ef8d6999f3
Add a dag combine to xform 256-bit shuffles into simple vector
...
inserts and extracts. This simple combine makes us generate only 1
instruction instead of 11 in the v8 case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137362 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:50:44 +00:00
Jim Grosbach
89958d50c3
Tidy up comment.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137359 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:41:59 +00:00
Owen Anderson
cbfc044acd
Fix decoding support for STREXD and LDREXD.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137356 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:34:58 +00:00
Jim Grosbach
7b8f46cf9e
ARM STRH assembly parsing and encoding.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137353 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:17:22 +00:00
Akira Hatanaka
1f8d822023
Add isIndirectBranch flag.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137351 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:05:37 +00:00
Owen Anderson
508e1d3db5
Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137347 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:47:56 +00:00
Jim Grosbach
45251b3707
Tidy up. Remove unused template parameter.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137345 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:41:13 +00:00
Owen Anderson
9fe72bcd37
Improve operand validation for Thumb2 addressing modes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137344 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:40:40 +00:00
Jim Grosbach
14605d1a67
ARM STRD assembly parsing and encoding.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137342 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:28:23 +00:00
Owen Anderson
26d2f0ac91
Continue to tighten decoding by performing more operand validation.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137340 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:21:46 +00:00
Jim Grosbach
ade7d00f5a
Tidy up.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137339 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:13:35 +00:00
Jim Grosbach
10348e70d5
ARM STRBT assembly parsing and encoding.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137337 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:04:56 +00:00
Jim Grosbach
548340c4bf
ARM STR(immediate) assembly parsing and encoding.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137331 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 19:22:40 +00:00
Owen Anderson
71156a6e00
Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137325 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 19:00:18 +00:00