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1354 Commits

Author SHA1 Message Date
Chris Lattner
b80610cd13 REmove dead fields of TAI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77820 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-01 22:40:22 +00:00
Evan Cheng
25f7cfc3cc Workaround a couple of Darwin assembler bugs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77781 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-01 06:13:52 +00:00
Evan Cheng
13f8b36205 Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77764 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-01 01:43:45 +00:00
Evan Cheng
b620724e61 Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same 
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.

Also, we should be using BLX to call external function stubs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77756 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-01 00:16:10 +00:00
Evan Cheng
a0ee862f2e t2BR_JT is mov pc, it's 2 byte long, not 4. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77744 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 22:22:22 +00:00
Evan Cheng
1119776b19 Thumb2 movcc need .w suffix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77743 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 22:21:55 +00:00
Chris Lattner
a87dea4f8c switch off of 'Section' onto MCSection. We're not properly using 
MCSection subclasses yet, but this is a step in the right direction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77708 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 18:48:30 +00:00
Evan Cheng
ff6ab17619 Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .align 
to ensure the instruction that follows a TBB (when the number of table entries
is odd) is 2-byte aligned.
Patch by Sandeep Patel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77705 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 18:35:56 +00:00
Evan Cheng
d26b14c34c - Teach TBB / TBH offset limits are 510 and 131070 respectively since the offset 
is scaled by two.
- Teach GetInstSizeInBytes about TBB and TBH.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77701 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 18:28:05 +00:00
Chris Lattner
f26e03bc7e refactor section construction in TLOF to be through an explicit 
initialize method, which can be called when an MCContext is available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77687 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-31 17:42:42 +00:00
Evan Cheng
ee42fd309e When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77642 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 23:29:25 +00:00
David Goodwin
07337c0fcf Remove redundant match for frame index from imm8 addrmode, it is handled by the imm12 addrmode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77632 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 22:45:52 +00:00
David Goodwin
8f65253236 Darwin assembler now recognizes "orn", so remove workaround. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77627 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 21:51:41 +00:00
David Goodwin
7c92f3ac99 Darwin assembler now supports "rrx", so remove workaround. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77625 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 21:38:40 +00:00
David Goodwin
d8c95b5ac2 Cleanup and include code selection for some frame index cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77622 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 18:56:48 +00:00
David Goodwin
3e4b22d983 Add missing D* register clobbers for Thumb-2 call. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77611 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 18:01:09 +00:00
Chris Lattner
513503961d add a random codegen deficiency. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77598 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 16:08:58 +00:00
Daniel Dunbar
7f93dc8345 Switch obvious clients to Twine instead of utostr (when they were already using 
a Twine, e.g., for names).
 - I am a little ambivalent about this; we don't want the string conversion of
   utostr, but using overload '+' mixed with string and integer arguments is
   sketchy. On the other hand, this particular usage is something of an idiom.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77579 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 04:20:37 +00:00
Bob Wilson
cf661e2c56 Lower a 128-bit BUILD_VECTOR with 2 elements to a pair of INSERT_VECTOR_ELTs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77557 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-30 00:31:25 +00:00
Evan Cheng
8770f747a9 tbb / tbh instructions only branch forward, not backwards. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77522 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 23:20:20 +00:00
Evan Cheng
d600522608 Add VFP3 D registers to the DPR register class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77521 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 23:03:41 +00:00
Evan Cheng
20a2a0aff3 Make sure Thumb2 uses the right call instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77507 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 21:26:42 +00:00
Chris Lattner
2cfd52c507 Give getPointerRegClass() a "kind" value so that targets can 
support multiple different pointer register classes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77501 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 20:31:52 +00:00
Evan Cheng
0531d04d00 - Fix an obvious copy and paste error. 
- Darwin Thumb2 call clobbers r9.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77500 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 20:10:36 +00:00
Bob Wilson
b7d0c90c44 Change Neon VLDn intrinsics to return multiple values instead of really 
wide vectors.  Likewise, change VSTn intrinsics to take separate arguments
for each vector in a multi-vector struct.  Adjust tests accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77468 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 16:39:22 +00:00
Chris Lattner
e53a600f06 pass the mangler down into the various SectionForGlobal methods. 
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77432 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 05:09:30 +00:00
Evan Cheng
5657c01949 Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77422 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-29 02:18:14 +00:00
David Goodwin
d9453784fb Thumb-2: fix typo that caused incorrect stack elimination for VFP operations and very large stack frames. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77401 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 23:52:33 +00:00
Devang Patel
0a9f7b9c3e Rename MDNode.h header. It defines MDnode and other metadata classes. 
New name is Metadata.h.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77370 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 21:49:47 +00:00
Evan Cheng
e7c329bf4b In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77364 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 20:53:24 +00:00
David Goodwin
6340632d3b Remove support for ORN to workaround <rdar://problem/7096522>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77363 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 20:51:25 +00:00
Chris Lattner
b180d992d8 more simplifications and cleanup. :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77350 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 18:48:43 +00:00
David Goodwin
5743854f47 Add workaround for <rdar://problem/7098328>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77340 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 18:15:38 +00:00
Chris Lattner
4bb253c60f the apple "ld_classic" linker doesn't support .literal16 in 32-bit 
mode, and "ld64" (the default linker) falls back to it in -static
mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77334 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 17:50:28 +00:00
David Goodwin
3583df7676 Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77329 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 17:06:49 +00:00
Evan Cheng
bae20a6353 tADDrSPI doesn't have a predicate operand, but tADDhirr and tADDi3 have. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77305 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 07:38:35 +00:00
Evan Cheng
542383d93b Code clean up. No functionality changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77301 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 06:24:12 +00:00
Evan Cheng
6495f63945 - More refactoring. This gets rid of all of the getOpcode calls. 
- This change also makes it possible to switch between ARM / Thumb on a
  per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
  using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77300 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 05:48:47 +00:00
Chris Lattner
f0144127b9 Rip all of the global variable lowering logic out of TargetAsmInfo. Since 
it is highly specific to the object file that will be generated in the end,
this introduces a new TargetLoweringObjectFile interface that is implemented
for each of ELF/MachO/COFF/Alpha/PIC16 and XCore.

Though still is still a brutal and ugly refactoring, this is a major step
towards goodness.

This patch also:
1. fixes a bunch of dangling pointer problems in the PIC16 backend.
2. disables the TargetLowering copy ctor which PIC16 was accidentally using.
3. gets us closer to xcore having its own crazy target section flags and
   pic16 not having to shadow sections with its own objects.
4. fixes wierdness where ELF targets would set CStringSection but not
   CStringSection_.  Factor the code better.
5. fixes some bugs in string lowering on ELF targets.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77294 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-28 03:13:23 +00:00
David Goodwin
1f0962756d ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is a dirty word at ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77275 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 23:34:12 +00:00
David Goodwin
c9d138f505 Remove TPat. No patterns depend on just isThumb(). Must use either T1Pat (isThumb1Only()) or T2Pat (is Thumb2). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77242 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 19:59:26 +00:00
Chris Lattner
fa199f3c16 remove dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77233 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 19:00:33 +00:00
Evan Cheng
e0f21bd47f More DCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77231 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 18:48:45 +00:00
Evan Cheng
78703ddafe convertToThreeAddress can't handle Thumb2 instructions (which don't have same address mode as ARM instructions). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77230 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 18:44:00 +00:00
Evan Cheng
fc17fb0aee Get rid of more dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77227 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 18:38:54 +00:00
Evan Cheng
293f8d9b88 Cosmetic change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77222 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 18:31:40 +00:00
Evan Cheng
83e0e36be8 Clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77221 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 18:25:24 +00:00
Evan Cheng
5ca53a7ad8 Get rid of some more getOpcode calls. 
This also fixes potential problems in ARMBaseInstrInfo routines not recognizing thumb1 instructions when 32-bit and 16-bit instructions mix.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77218 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 18:20:05 +00:00
David Goodwin
752aa7d2fe Thumb-2 does not have RSC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77201 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 16:39:05 +00:00
David Goodwin
af0d08d55c Add ".w" suffix for wide thumb-2 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77199 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 16:31:55 +00:00
Chris Lattner
e346694a81 Eliminate getNamed/getUnnamedSection, adding a new and unified getOrCreateSection 
instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77186 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 06:17:14 +00:00
Chris Lattner
5fe575ff4f Eliminate SectionFlags, just embed a SectionKind into Section 
instead and drive things based off of that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77184 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 05:32:16 +00:00
Evan Cheng
1f5c988754 If CPSR is modified but the def is dead, then it's ok to fold the load / store. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77182 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 04:18:04 +00:00
Evan Cheng
5732ca084a Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate more getOpcode calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77181 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 03:14:20 +00:00
Evan Cheng
08b93c6a70 Use the right instructions to copy between GPR and the more strictive tGPR classes. t2MOV does not match the RC requirements. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77175 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 00:33:08 +00:00
Evan Cheng
dced03fc84 Merge isLoadFromStackSlot into one since it behaves the same regardless of sub-target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77174 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 00:24:36 +00:00
Evan Cheng
68e3c6ae49 Just use a single isMoveInstr to catch all the cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77173 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-27 00:05:15 +00:00
Evan Cheng
d83360694a Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77172 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-26 23:59:01 +00:00
Chris Lattner
0fcf4dc6d3 untangle a TargetAsmInfo hack where ELFTargetAsmInfo would create a 
'unnamed' bss section, but some impls would want a named one.  Since
they don't have consistent behavior, just make each target do their
own thing, instead of doing something "sortof common" then having
targets change immutable objects later.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77165 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-26 19:23:28 +00:00
Evan Cheng
30b2bdfa73 Refactor. Get rid of a few more getOpcode() calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77164 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-26 18:55:14 +00:00
Daniel Dunbar
93b67e40de Eliminate some uses of DOUT, cerr, and getNameStart(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77145 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-26 07:49:05 +00:00
Daniel Dunbar
8977d087c6 Factor commonality in triple match routines into helper template for registering 
classes, and migrate existing targets over.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77126 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-26 05:03:33 +00:00
Daniel Dunbar
fa27ff296d Kill Target specific ModuleMatchQuality stuff. 
- This was overkill and inconsistently implemented.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77114 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-26 02:22:58 +00:00
Bob Wilson
8bb9e48752 Add support for ARM Neon VREV instructions. 
Patch by Anton Korzh, with some modifications from me.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77101 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-26 00:39:34 +00:00
Daniel Dunbar
03d7651c36 Remove Value::{isName, getNameRef}. 
Also, change MDString to use a StringRef.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77098 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 23:55:21 +00:00
Daniel Dunbar
d6fd377f33 Simplify JIT target selection. 
- Instead of requiring targets to define a JIT quality match function, we just
   have them specify if they support a JIT.

 - Target selection for the JIT just gets the host triple and looks for the best
   target which matches the triple and has a JIT.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77060 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 10:09:50 +00:00
Daniel Dunbar
0c795d6187 Add new helpers for registering targets. 
- Less boilerplate == good.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77052 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 06:49:55 +00:00
Evan Cheng
c7423aff68 80 col violation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77041 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 01:55:25 +00:00
Evan Cheng
c6b54d5a33 Get rid of a couple of unnecessary getOpcode calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77035 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 01:25:08 +00:00
Evan Cheng
3c91f36a45 Another TODO. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77026 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 00:39:37 +00:00
Evan Cheng
66ac53165e Change Thumb2 jumptable codegen to one that uses two level jumps: 
Before:
      adr r12, #LJTI3_0_0
      ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
      .long    LBB3_24
      .long    LBB3_30
      .long    LBB3_31
      .long    LBB3_32

After:
      adr r12, #LJTI3_0_0
      add pc, r12, +r0, lsl #2
LJTI3_0_0:
      b.w    LBB3_24
      b.w    LBB3_30
      b.w    LBB3_31
      b.w    LBB3_32

This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
   (smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
   into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
   won't have to over-estimate the size.

Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77024 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 00:33:29 +00:00
Daniel Dunbar
ce63ffb52f More migration to raw_ostream, the water has dried up around the iostream hole. 
- Some clients which used DOUT have moved to DEBUG. We are deprecating the
   "magic" DOUT behavior which avoided calling printing functions when the
   statement was disabled. In addition to being unnecessary magic, it had the
   downside of leaving code in -Asserts builds, and of hiding potentially
   unnecessary computations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77019 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 00:23:56 +00:00
Evan Cheng
90daf4d035 ARM code emitter can't handle Thumb2 instructions yet. So don't even try. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77018 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-25 00:13:11 +00:00
Owen Anderson
eed707b1e6 Revert the ConstantInt constructors back to their 2.5 forms where possible, thanks to contexts-on-types. More to come. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77011 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 23:12:02 +00:00
Evan Cheng
0b6afa8c71 Uh. It would be useful to actually print the operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77004 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 20:47:38 +00:00
Evan Cheng
40efc251cd Disable my constant island pass optimization (to make use soimm more effectively). It caused infinite looping on lencod. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76995 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 19:31:03 +00:00
Evan Cheng
49f846805e Add a workaround for Darwin assembler bug where it's not setting the thumb bit in Thumb2 jumptable entries. We now pass Olden. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76991 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 18:54:23 +00:00
Evan Cheng
789476240d Make sure thumb2 jumptable entries are aligned. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76986 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 18:20:44 +00:00
Evan Cheng
23606e35ab Clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76984 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 18:20:16 +00:00
Evan Cheng
c324ecb7bc Replace use of std::set with SmallPtrSet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76983 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 18:19:46 +00:00
Eli Friedman
23ed52752b Remove unused member functions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76960 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 07:43:59 +00:00
Chris Lattner
c440cc7f2c use section flags more correctly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76944 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 04:08:17 +00:00
Chris Lattner
fb3431aec5 reduce api exposure: clients shouldn't call SectionKindForGlobal directly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76941 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 03:49:17 +00:00
Evan Cheng
865763bf80 Thumb2 should use the register scavenger. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76930 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 01:05:51 +00:00
Evan Cheng
b74bb1a7a4 FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same instructions on all sub-targets. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76925 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 00:53:56 +00:00
David Goodwin
5ff58b5c3a Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76919 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-24 00:16:18 +00:00
Evan Cheng
eee839dd3c Thumb2 does not allow the use of "pc" register as part of the load / store address. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76909 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 23:09:51 +00:00
Evan Cheng
d3d9d66dd2 Fix up ARM constant island pass for Thumb2. 
Also fixed up code to fully use the SoImm field for ADR on ARM mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76890 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 18:27:47 +00:00
Evan Cheng
81c102ba66 Since we have moved unified assembly, switch to ADR instruction instead of a the difficult-to-read .set + add syntax to materialize pc-relative address. 
Turns out this also fixed a poor code selection on Thumb1. I have no idea why we were using a mov + add to do the same thing as ADR before.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76889 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 18:26:03 +00:00
David Goodwin
b53cc014d0 Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76883 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 17:06:46 +00:00
Evan Cheng
697712c7d4 80 col violation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76872 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-23 07:58:08 +00:00
David Goodwin
e1e52edfff Fix typo in addrmode definition. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76806 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 22:24:31 +00:00
Evan Cheng
eadf04992a Use getTargetConstant instead of getConstant since it's meant as an constant operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76803 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 22:03:29 +00:00
Evan Cheng
78dd9dbdfb Eliminate a redudant check Eli pointed out. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76762 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 18:08:05 +00:00
Evan Cheng
756da12ae4 Don't forget D16 - D31 are clobbered by calls and sjlj eh. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76729 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 06:46:53 +00:00
Evan Cheng
4a8b7d030b Add R12 to the list of registers clobbered by 16-bit Thumb calls as a pre-caution. r12 could be live once we have mixed 32-bit and 16-bit instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76728 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 06:37:28 +00:00
Evan Cheng
3b6627b944 Fix a obvious copy-n-paste bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76727 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 06:12:40 +00:00
Evan Cheng
8295d99bff Get rid one of the getRegisterNumbering. Also add D16 - D31. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76725 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 05:55:18 +00:00
Evan Cheng
064a6eacab Add an entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76711 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 00:58:27 +00:00
Owen Anderson
e922c02019 Get rid of the Pass+Context magic. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76702 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-07-22 00:24:57 +00:00