Commit Graph

79264 Commits

Author SHA1 Message Date
Sebastian Pop
8a86887ba3 use getHostTriple instead of getDefaultTargetTriple in getClosestTargetForJIT
Get back getHostTriple.

For JIT compilation, use the host triple instead of the default
target: this fixes some JIT testcases that used to fail when the
compiler has been configured as a cross compiler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147542 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04 19:47:22 +00:00
Akira Hatanaka
b0e7af7797 Enable -soft-float for MIPS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147541 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04 19:29:11 +00:00
Nick Lewycky
234f8c9ef8 Remove pointless asserts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147529 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04 09:42:30 +00:00
Nick Lewycky
148fd55ef3 Teach instcombine all sorts of great stuff about shifts that have exact, nuw or
nsw bits on them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147528 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04 09:28:29 +00:00
Craig Topper
515783466c Allow vector shuffle normalizing to use concat vector even if the sources are commuted in the shuffle mask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147527 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04 09:23:09 +00:00
Craig Topper
481b79c950 Implement VECTOR_SHUFFLE canonicalizations during DAG combine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147525 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04 08:07:43 +00:00
NAKAMURA Takumi
7d34b92993 test/CodeGen/X86/jump_sign.ll: Add -mcpu=pentiumpro for non-x86 hosts. It uses "cmov".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147521 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04 03:52:23 +00:00
Akira Hatanaka
2010325a11 Rename immLUiOpnd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147519 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04 03:09:26 +00:00
Akira Hatanaka
f12e702a8c - Define base classes for Jump-and-link instructions and make 32-bit and 64-bit
versions derive from them.
- JALR64 is not needed since N64 does not emit jal. 
- Add template parameter to BranchLink that sets the rt field. 
- Fix the set of temporary registers for O32 and N64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147518 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04 03:02:47 +00:00
Akira Hatanaka
cb9dd72fdc Have getRegForInlineAsmConstraint return the correct register class when target
is Mips64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147516 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04 02:45:01 +00:00
Evan Cheng
afad0fe59a Fix more places which should be checking for iOS, not darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147513 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04 01:55:04 +00:00
Evan Cheng
56f582d664 For x86, canonicalize max
(x > y) ? x : y
=>
(x >= y) ? x : y

So for something like
(x - y) > 0 : (x - y) ? 0
It will be
(x - y) >= 0 : (x - y) ? 0

This makes is possible to test sign-bit and eliminate a comparison against
zero. e.g.
subl   %esi, %edi
testl  %edi, %edi
movl   $0, %eax
cmovgl %edi, %eax
=>
xorl   %eax, %eax
subl   %esi, $edi
cmovsl %eax, %edi

rdar://10633221


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147512 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04 01:41:39 +00:00
Kostya Serebryany
091523c648 [asan] one more test for asan instrumentation: (*a)++ should be instrumented only once.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147509 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04 01:02:14 +00:00
Chris Lattner
fcd7090063 Turn a few more inline asm errors into "emitErrors" instead of fatal errors.
Before we'd get:

$ clang t.c 
fatal error: error in backend: Invalid operand for inline asm constraint 'i'!

Now we get:

$ clang t.c
t.c:16:5: error: invalid operand for inline asm constraint 'i'!
    "movq         (%4), %%mm0\n"
    ^

Which at least gets us the inline asm that is the problem.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147502 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03 23:51:01 +00:00
Chris Lattner
3a4c60ca3b generalize LLVMContext::emitError to take a twine instead of a StringRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147501 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03 23:47:05 +00:00
Chad Rosier
b90d2a9046 Fix 80-column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147495 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03 23:19:12 +00:00
Jakob Stoklund Olesen
ac1ed44d95 Don't use enums larger than 1 << 31 for target features.
Patch by Andy Zhang!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147491 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03 23:04:28 +00:00
Jakob Stoklund Olesen
6d5b7cc235 Revert r146997, "Heed spill slot alignment on ARM."
This patch caused a miscompilation of oggenc because a frame pointer was
suddenly needed halfway through register allocation.

<rdar://problem/10625436>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147487 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03 22:34:35 +00:00
Jakob Stoklund Olesen
2d44e02533 Assert when reserved registers have been assigned.
This can only happen if the set of reserved registers changes during
register allocation.

<rdar://problem/10625436>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147486 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03 22:34:31 +00:00
Nadav Rotem
c2d064f028 Revert 147426 because it caused pr11696.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147485 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03 22:19:42 +00:00
Nadav Rotem
316477dd54 Fix incorrect widening of the bitcast sdnode in case the incoming operand is integer-promoted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147484 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03 22:12:28 +00:00
Chad Rosier
3d1161e9ae Enhance DAGCombine for transforming 128->256 casts into a vmovaps, rather
then a vxorps + vinsertf128 pair if the original vector came from a load.
rdar://10594409

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147481 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03 21:05:52 +00:00
Nick Lewycky
48a09aec60 Conform to the style guide; remove 'else' after 'return'. Also remove an extra
if-statement by turning it into an assert. No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147474 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03 20:33:00 +00:00
Owen Anderson
517c4d7fda Remove the restriction that target intrinsics can only involve legal types. Targets can perfects well support intrinsics on illegal types, as long as they are prepared to perform custom expansion during type legalization. For example, a target where i64 is illegal might still support the i64 intrinsic operation using pairs of i32's. ARM already does some expansions like this for non-intrinsic operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147472 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03 20:09:02 +00:00
Lang Hames
567cdbab28 Clarified assert text.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147471 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03 20:05:57 +00:00
Stepan Dyatkovskiy
2b29d233b9 Fix for PR11652: assertion failures when Type.cpp is compiled with -Os
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147470 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03 20:04:35 +00:00
Matt Beaumont-Gay
19055cc271 Fix malformed assert.
If anybody has strong feelings about 'default: assert(0 && "blah")' vs
'default: llvm_unreachable("blah")', feel free to regularize the instances of
each in this file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147459 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03 19:03:59 +00:00
Eric Christopher
5e33d21d7f Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147456 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03 18:38:37 +00:00
Nick Lewycky
5eb2e957b3 Fix typo in ruler. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147454 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03 18:22:43 +00:00
Devang Patel
b1666b971e Intel style asm variant does not need '%' prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147453 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03 18:22:10 +00:00
Stepan Dyatkovskiy
bd47f59afa Type: replaced usage of ID with getTypeID().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147446 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03 14:05:04 +00:00
Elena Demikhovsky
ce58a03587 Fixed a bug in SelectionDAG.cpp.
The failure seen on win32, when i64 type is illegal.
It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR.

The failure message is:
llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed.

I added a special test that checks vector shuffle on win32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147445 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03 11:59:04 +00:00
Andrew Trick
0f8cd56bfd Fix SCEVExpander to handle loops with no preheader when LSR gives it a
"phony" insertion point.

Fixes rdar://10619599: "SelectionDAGBuilder shouldn't visit PHI nodes!" assert


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147439 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-02 21:25:10 +00:00
Duncan Sands
cf6bd5a7c3 Correct spelling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147435 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-02 16:55:01 +00:00
Chandler Carruth
972cc0d54a Undo the hack in r147427 and move this unittest to a better home. This
is testing the bitcode reader's functionality, not VMCore's. Add the
what is a hope sufficient build system mojo to build and run a new
unittest.

Also clean up some of the test's naming. The goal for the file should be
to unittest the Bitcode Reader, and this is just one particular test
among potentially many in the future. Also, reverse my position and
relegate the PR# to a comment, but stash the comment on the same line as
the test name so it doesn't get lost. This makes the code more
self-documenting hopefully w/o losing track of the PR number.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147431 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-02 09:19:48 +00:00
Craig Topper
c612d79817 Miscellaneous shuffle lowering cleanup. No functional changes. Primarily converting the indexing loops to unsigned to be consistent across functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147430 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-02 09:17:37 +00:00
Craig Topper
a51bb3aa75 Make CanXFormVExtractWithShuffleIntoLoad reject loads with multiple uses. Also make it return false if there's not even a load at all. This makes the code better match the code in DAGCombiner that it tries to match. These two changes prevent some cases where vector_shuffles were making it to instruction selection and causing the older shuffle selection code to be triggered. Also needed to fix a bad pattern that this change exposed. This is the first step towards getting rid of the old shuffle selection support. No test cases yet because there's no way to tell whether a shuffle was handled in the legalize stage or at instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147428 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-02 08:46:48 +00:00
Chandler Carruth
f3cd23c6cb Fix unittest makefile after r147425. This should unbreak the makefile
build. This didn't show up in the CMake build because the CMake build
for the unittests is rather poorly factored.

This probably isn't the correct fix. This should be a bitcode reader
unittest not a VMCore unittest. I'll move it and clean various parts of
the unittest up in a follow-up patch, but I wanted to unbreak the bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147427 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-02 08:40:40 +00:00
Nadav Rotem
a46f35d3d6 Optimize the sequence blend(sign_extend(x)) to blend(shl(x)) since SSE blend instructions only look at the highest bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147426 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-02 08:05:46 +00:00
Rafael Espindola
47f79bb58e Materialize functions whose basic blocks are used by global variables. Fixes
PR11677.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147425 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-02 07:49:53 +00:00
Craig Topper
a86bcfb565 Allow CRC32 instructions to be selected when AVX is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147411 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-01 19:51:58 +00:00
Craig Topper
de9e4c728e Fix sfence, lfence, mfence, and clflush to be able to be selected when AVX is enabled. Fix monitor and mwait to require SSE3 or AVX, previously they worked even if SSE3 was disabled. Make prefetch instructions not set the execution domain since they don't use XMM registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147409 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-01 19:40:22 +00:00
Benjamin Kramer
8943574b44 X86Disassembler: Fix undefined behavior found by GCC 4.6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147404 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-01 17:55:36 +00:00
Benjamin Kramer
55c6d57734 PatternMatch: Introduce a matcher for instructions with the "exact" bit. Use it to simplify a few matchers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147403 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-01 17:55:30 +00:00
Benjamin Kramer
395363a9b9 PatternMatch: Simplify code by reusing the Operator class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147402 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-01 17:55:23 +00:00
Rafael Espindola
acae2a63b9 Revert 147399. It broke CodeGen/ARM/vext.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147400 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-01 17:36:23 +00:00
Elena Demikhovsky
ac12855066 Fixed a bug in SelectionDAG.cpp.
The failure seen on win32, when i64 type is illegal.
It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR.

The failure message is:
llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed.

I added a special test that checks vector shuffle on win32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147399 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-01 16:22:47 +00:00
NAKAMURA Takumi
45ba16588d Happy new year 2012!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147395 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-01 08:16:56 +00:00
Craig Topper
b3982da7d2 Merge X86 SHUFPS and SHUFPD node types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147394 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-31 23:50:21 +00:00
Craig Topper
3ee6d22c78 Add patterns for integer forms of SHUFPD/VSHUFPD with a memory load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147393 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-31 23:24:49 +00:00