Jim Grosbach
399cdca4d2
ARM assembly parsing and encoding for VLD1 with writeback.
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Four entry register lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142882 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-25 00:14:01 +00:00
Jim Grosbach
5921675ff5
ARM assembly parsing and encoding for VLD1 w/ writeback.
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Three entry register list variation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142876 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24 23:26:05 +00:00
Jim Grosbach
10b90a9bbf
ARM refactor am6offset usage for VLD1.
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Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142853 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24 21:45:13 +00:00
Owen Anderson
a7c98f58ea
Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142817 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24 18:04:29 +00:00
Benjamin Kramer
1a2f9886a2
Move various generated tables into read-only memory, fixing up const correctness along the way.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142726 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-22 16:50:00 +00:00
Jim Grosbach
224180e81b
Assembly parsing for 4-register sequential variant of VLD2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142704 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 23:58:57 +00:00
Jim Grosbach
4661d4cac3
Assembly parsing for 2-register sequential variant of VLD2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142691 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 22:21:10 +00:00
Jim Grosbach
b6310316db
Assembly parsing for 4-register variant of VLD1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 20:35:01 +00:00
Jim Grosbach
cdcfa28056
Assembly parsing for 3-register variant of VLD1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 20:02:19 +00:00
Jim Grosbach
280dfad489
ARM VLD parsing and encoding.
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Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 18:54:25 +00:00
Jim Grosbach
01817c39a9
Tidy up. Trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142591 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 17:28:20 +00:00
Chad Rosier
c378015d1c
Removed set, but unused variables.
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Patch by Joe Abbey <jabbey@arxan.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142223 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 18:48:30 +00:00
Richard Trieu
8223e45dff
Fix a non-firing assert. Change:
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assert("bad SymbolicOp.VariantKind");
To:
assert(0 && "bad SymbolicOp.VariantKind");
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142000 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 20:50:26 +00:00
Eli Friedman
ecb830e45c
Fix undefined shift. Patch by Ahmed Charles.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141914 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 23:36:06 +00:00
Owen Anderson
c18e940c5a
SETEND is not allowed in an IT block.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141874 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-13 17:58:39 +00:00
Jim Grosbach
81b2928d80
ARM addrmode5 represents the 'U' bit of the encoding backwards.
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The disassembler needs to use the AM5 factory methods instead of just
building up the immediate directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141819 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 21:59:02 +00:00
Jim Grosbach
c66e7afcf2
Thumb2 assembly parsing and encoding for LDC/STC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 20:54:17 +00:00
Jim Grosbach
b0786b33fa
addrmode2 is gone from these, so no need for the reg0 operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141794 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 18:11:24 +00:00
Owen Anderson
7011eee9b5
Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141339 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 23:33:11 +00:00
Kevin Enderby
9e5887b17e
Adding back support for printing operands symbolically to ARM's new disassembler
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using llvm's public 'C' disassembler API now including annotations.
Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
blx _puts
instead of this:
blx #-36
and includes support for annotations for branches to symbol stubs like:
bl 0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
ldr r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141129 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 22:44:48 +00:00
Jim Grosbach
4ebbf7b8a8
ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.
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Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.
rdar://10211428
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140834 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-30 00:50:06 +00:00
Owen Anderson
0afa0094af
ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140560 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-26 21:06:22 +00:00
Owen Anderson
31d485ec9a
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140415 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 21:07:25 +00:00
Owen Anderson
df0caeb6ec
Revert r140412. This affects more instructions than intended.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140413 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 21:02:01 +00:00
Owen Anderson
d256056581
Thumb2 register-shifted-register loads cannot target the PC or the SP.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140412 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-23 21:00:32 +00:00
Owen Anderson
d9346fbb06
tMOVSr is not allowed in an IT block either.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140104 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 23:57:20 +00:00
Owen Anderson
9f666b5f2e
CPS instructions are UNPREDICTABLE inside IT blocks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140102 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 23:47:10 +00:00
Owen Anderson
04c7877894
Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in the middle.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140079 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 22:34:23 +00:00
Jim Grosbach
7f739bee26
Thumb2 assembly parsing and encoding for TBB/TBH.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 22:21:13 +00:00
Owen Anderson
ecd1c55790
Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140032 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-19 18:07:10 +00:00
Owen Anderson
cb77551927
Bitfield mask instructions are unpredictable if the encoded LSB is higher than the encoded MSB.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139972 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 23:30:01 +00:00
Owen Anderson
8b22778431
Fix bitfield decoding based on Eli's feedback.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 23:04:48 +00:00
Owen Anderson
e4f2df945a
Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139965 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 22:42:36 +00:00
Owen Anderson
89db0f690c
Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139964 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 22:29:48 +00:00
Owen Anderson
705b48ff86
Fix disassembly of Thumb2 LDRSH with a #-0 offset.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139943 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-16 21:08:33 +00:00
Owen Anderson
98c5ddabca
Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139876 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-15 23:38:46 +00:00
Owen Anderson
34626acf7f
Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139736 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-14 21:06:21 +00:00
Owen Anderson
a3157b4026
Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139522 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-12 18:56:30 +00:00
Owen Anderson
921d01ae1f
LDM writeback is not allowed if Rn is in the target register list.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139432 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 23:13:33 +00:00
Owen Anderson
08fef885eb
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139422 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 22:24:36 +00:00
Owen Anderson
51f6a7abf2
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 21:48:23 +00:00
Jim Grosbach
b6aed508e3
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 18:37:27 +00:00
Owen Anderson
441462f932
All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139329 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 22:48:37 +00:00
Owen Anderson
d2fc31b3f7
Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139328 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 22:42:49 +00:00
Jim Grosbach
a77295db19
Thumb2 assembly parsing and encoding for LDRD(immediate).
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Refactor operand handling for STRD as well. Tests for that forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 22:07:06 +00:00
Owen Anderson
170580e8f4
Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139268 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 00:11:18 +00:00
Owen Anderson
8a83f71301
Create Thumb2 versions of STC/LDC, and reenable the relevant tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139256 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 21:10:42 +00:00
James Molloy
a5d5856854
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139250 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 19:42:28 +00:00
Owen Anderson
6de3c6f1a9
Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139240 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 17:55:19 +00:00
James Molloy
b950585cc5
Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139237 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 17:24:38 +00:00
Owen Anderson
a1c110045a
Merge the ARM disassembler header into the implementation file, since it is not externally exposed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138982 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01 23:35:51 +00:00
Owen Anderson
a6804444e8
Fix 80 columns violations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138980 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01 23:23:50 +00:00
James Molloy
c047dcade5
Fix up r137380 based on post-commit review by Jim Grosbach.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138948 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01 18:02:14 +00:00
Owen Anderson
b45b11bce1
The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138910 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-31 22:00:41 +00:00
Owen Anderson
eaca928a37
Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138840 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 22:58:27 +00:00
Owen Anderson
f1eab597b2
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 23:32:08 +00:00
Owen Anderson
9f7e831994
Spelling fail.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138667 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 21:47:57 +00:00
Owen Anderson
9ab0f25fc1
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138653 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 20:43:14 +00:00
Owen Anderson
1af7f7291d
Update for feedback from Jim.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138642 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 19:39:26 +00:00
Benjamin Kramer
86ce852a15
ARMDisassembler: Always return a size, even when disassembling fails.
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This should fix PR10772.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138636 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 18:21:36 +00:00
Owen Anderson
96425c8464
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138635 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 18:09:22 +00:00
Owen Anderson
9bd655dcde
Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors.
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This is the last disassembly crash detected by exhaustive Thumb2 instruction space. Major thanks to Chandler Carruth for making this kind of exhaustive testing possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138625 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 06:19:51 +00:00
Owen Anderson
99906830e8
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138575 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 18:30:18 +00:00
Owen Anderson
f44082091c
Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138507 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 22:40:22 +00:00
Owen Anderson
12a1e3bbcb
Be careful not to walk off the end of the operand info list while updating VFP predicates.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138492 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 21:35:46 +00:00
Evan Cheng
3e74d6fdd2
Move TargetRegistry and TargetSelect from Target to Support where they belong.
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These are strictly utilities for registering targets and components.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 18:08:43 +00:00
Owen Anderson
e234d02204
Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138443 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 17:21:43 +00:00
Owen Anderson
82265a2c72
Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138341 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 17:51:38 +00:00
Owen Anderson
6153a036f5
Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138339 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 17:45:18 +00:00
Owen Anderson
8e1e60b5f8
Reject invalid imod values in t2CPS instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138306 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 23:44:04 +00:00
Owen Anderson
357ec6850b
Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138269 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 20:27:12 +00:00
Owen Anderson
2cbf210450
Fix another batch of VLD/VST decoding crashes discovered by randomized testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138255 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 18:42:13 +00:00
Owen Anderson
f1c8e3e70e
Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138251 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 18:22:06 +00:00
Owen Anderson
b113ec55e8
Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138246 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-22 17:56:58 +00:00
Owen Anderson
78affc9ea1
STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate.
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Found by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 22:47:44 +00:00
Owen Anderson
846dd95f87
Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138000 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 22:31:17 +00:00
Owen Anderson
1dd56f05e1
Remember to fill in some operands so we can print _something_ coherent even when decoding the CPS instruction soft-fails.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 22:15:25 +00:00
Owen Anderson
14090bf263
Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions.
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Fixes a large class of disassembler crashes found by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137995 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-18 22:11:02 +00:00
Jim Grosbach
c40578250d
Tidy up. 80 columns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137881 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-17 21:58:18 +00:00
Jim Grosbach
70939ee141
ARM clean up the imm_sr operand class representation.
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Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137879 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-17 21:51:27 +00:00
Owen Anderson
0aa38ab1fb
Be more careful in the Thumb decoder hooks to avoid walking off the end of the OpInfo array.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137838 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-17 18:14:48 +00:00
Owen Anderson
83e3f67fb6
Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
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Patch by James Molloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137830 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-17 17:44:15 +00:00
Owen Anderson
16280308ac
Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137787 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-16 23:45:44 +00:00
Owen Anderson
ef2865a8ea
Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137686 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 23:38:54 +00:00
Owen Anderson
c537f3be0c
Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
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Patch by James Molloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137647 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 20:51:32 +00:00
Owen Anderson
7a2e1770ea
Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137635 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 18:44:44 +00:00
Owen Anderson
0d09499cf3
Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137502 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 20:36:11 +00:00
Owen Anderson
79628e92e1
Fix decoding of ARM-mode STRH.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137499 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 20:02:50 +00:00
Owen Anderson
7cdbf086e4
Fix decoding of pre-indexed stores.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137487 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 18:12:39 +00:00
Owen Anderson
3f3570a38b
Separate decoding for STREXD and LDREXD to make each work better.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137476 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 17:58:32 +00:00
Jim Grosbach
342ebd5f38
ARM STRT assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137372 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:18:00 +00:00
Owen Anderson
adf2b094cb
Add another accidentally omitted predicate operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137370 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:08:38 +00:00
Owen Anderson
1fb6673bc2
Add missing predicate operand on SMLA and friends.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137368 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 22:05:38 +00:00
Owen Anderson
cbfc044acd
Fix decoding support for STREXD and LDREXD.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137356 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 21:34:58 +00:00
Owen Anderson
508e1d3db5
Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137347 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:47:56 +00:00
Owen Anderson
26d2f0ac91
Continue to tighten decoding by performing more operand validation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137340 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:21:46 +00:00
Jim Grosbach
10348e70d5
ARM STRBT assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137337 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 20:04:56 +00:00
Owen Anderson
71156a6e00
Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137325 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 19:00:18 +00:00
Owen Anderson
2b7b238e84
Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137323 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 18:55:42 +00:00
Owen Anderson
ae0bc5deaa
Improve error checking in the new ARM disassembler. Patch by James Molloy.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137320 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 18:24:51 +00:00