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84 Commits

Author SHA1 Message Date
Chris Lattner
53e884587b make sure bit_converts are expanded 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24978 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-23 05:13:35 +00:00
Chris Lattner
3cb7187d5f fix the int<->fp instructions, which apparently take a single float register 
to represent the int part (because it's always 32-bits)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24976 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-23 05:00:16 +00:00
Chris Lattner
a01874fc89 Use BIT_CONVERT to simplify this code 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24975 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-23 02:31:39 +00:00
Jim Laskey
e81aecbae6 Disengage DEBUG_LOC from non-PPC targets. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24919 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-21 20:51:37 +00:00
Chris Lattner
7669a51c34 remove dead code 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24896 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-21 05:27:51 +00:00
Chris Lattner
7c423b4df1 Fix pifft by correcting the case when a i64/f64 straddles O5 and memory: 
we were storing into [FP+88] instead of [FP+92].
Improve codegen by emitting [FP+92], instead of emitting a copy of FP into
another GPR which wouldn't be coallesced because FP isn't register allocated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24859 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-19 07:57:53 +00:00
Chris Lattner
eb0966693b Fix calls to functions returning i64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24856 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-19 02:15:51 +00:00
Chris Lattner
61772c20ee mark some unsupported ops as unsupported 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24852 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-19 01:39:40 +00:00
Chris Lattner
6554beffe4 Keep stack frames 8-byte aligned. This fixes olden/voronoi 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24849 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-19 01:15:13 +00:00
Chris Lattner
8ba0423660 Elimiante SP and FP, which weren't members of the IntRegs register class 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24844 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-19 00:06:52 +00:00
Chris Lattner
311f8c21d0 Add support for calls to external symbols 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24838 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-18 23:07:11 +00:00
Chris Lattner
e90ac3a3e7 we have no memcpy 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24837 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-18 23:00:27 +00:00
Chris Lattner
b4d899e21c Fix a crash on a call with no arguments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24836 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-18 22:57:47 +00:00
Chris Lattner
dab05f0e19 Change return lowering so that we can autogen the matching code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24832 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-18 21:03:04 +00:00
Chris Lattner
2db3ff66f1 Implement Calls for V8. This would be completely autogenerated except for 
a small bug in tblgen.  When that is fixed, we can remove the ISD::Call case
in Select.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24830 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-18 15:55:15 +00:00
Chris Lattner
384e5efc0e Implement the full V8 ABI for incoming arguments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24825 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-18 13:33:06 +00:00
Chris Lattner
3308449afc Give V8 select_cc, in the spirit of the PPC backend 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24823 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-18 08:13:54 +00:00
Chris Lattner
065c896b7a V8 doesn't have FP extload 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24821 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-18 07:13:32 +00:00
Chris Lattner
d5aae05281 simplifications, fix typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24820 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-18 07:09:06 +00:00
Chris Lattner
8fa54dc702 Add frameindex support 
Add support for copying (e.g. returning) doubles
Add support for F<->I instructions


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24818 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-18 06:59:57 +00:00
Chris Lattner
76acc872b3 Add constant pool support, including folding into addresses. 
Pretty print addresses a bit, to not print [%r1+%g0]: just print [%r1]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24813 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-18 02:37:35 +00:00
Chris Lattner
e1389ad43a Teach the addressing mode stuff to fold "%lo" into 'ri' addressing modes, 
allowing us to compile this:

to this:

%G1 = external global int
%G2 = external global int
void %test() {
        %X = load int* %G1
        store int %X, int* %G2
        ret void
}

test:
        save -96, %sp, %sp
        sethi %hi(G1), %l0
        ld [%l0+%lo(G1)], %l0
        sethi %hi(G2), %l1
        st %l0, [%l1+%lo(G2)]
        restore %g0, %g0, %g0
        retl
        nop

instead of this:

test:
        save -96, %sp, %sp
        sethi %hi(G1), %l0
        or %g0, %lo(G1), %l1
        ld [%l1+%l0], %l0
        sethi %hi(G2), %l1
        or %g0, %lo(G2), %l2
        st %l0, [%l2+%l1]
        restore %g0, %g0, %g0
        retl
        nop


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24812 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-18 02:27:00 +00:00
Chris Lattner
e357246c6b Add initial support for global variables, and fix a bug in addr mode selection 
where we didn't select the operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24811 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-18 02:10:39 +00:00
Chris Lattner
4d55aca87a Add initial conditional branch support. This doesn't actually work yet due 
to a bug in the scheduler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24807 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-18 01:20:35 +00:00
Chris Lattner
d19fc65345 Implement 64-bit add/sub, make sure to receive and return 64-bit args with 
the right halves in the right regs


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24799 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-17 22:55:57 +00:00
Chris Lattner
7087e57872 implement div and rem 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24798 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-17 22:39:19 +00:00
Chris Lattner
ee3d5fba54 implement MULHU/MULHS for 64-bit multiplies 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24797 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-17 22:30:00 +00:00
Chris Lattner
9034b883a4 Make the addressing modes smarter 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24795 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-17 21:25:27 +00:00
Chris Lattner
217aabf89e Add support for 64-bit arguments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24792 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-17 20:59:06 +00:00
Chris Lattner
9a60ff654a Sparc doesn't have sext_inreg 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24791 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-17 20:50:42 +00:00
Chris Lattner
bc83fd9672 Add basic addressing mode support and one load. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24782 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-17 20:04:49 +00:00
Chris Lattner
4b4863188f Implement ret with operand, giving us this: 
int %test(int %A) {
  ret int %A
}


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24773 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-17 08:15:09 +00:00
Chris Lattner
a01b75758c Implement LowerArguments, at least for the first 6 integer args 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24770 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-17 08:03:24 +00:00
Chris Lattner
6c18b10ad4 Add the framework for a dag-dag isel 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24769 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-17 07:47:01 +00:00