6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-02 09:29:24 +00:00
Code Issues Projects Releases Wiki Activity
21,107 Commits 39 Branches 0 Tags 277 MiB
9b14f66320
Commit Graph

58 Commits

Author SHA1 Message Date
Nate Begeman
9b14f66320 Add the remainder of the AltiVec 4 x float instructions. Further 
enhancements will be necessary to teach the code generator that since
there is no fmul, it will have to do vmaddfp, adding +0.0.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24516 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-29 08:04:45 +00:00
Nate Begeman
01595c52b3 Small tweaks noticed while on the plane. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24492 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-26 22:39:34 +00:00
Nate Begeman
e4f17a5f9b Some first bits of AltiVec stuff: Instruction Formats, Encodings, and 
Registers.  Apologies to Jim if the scheduling info so far isn't accurate.

There's a few more things like VRsave support that need to be finished up
in my local tree before I can commit code that Does The Right Thing for
turning 4 x float into the various altivec packed float instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24489 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-23 05:29:52 +00:00
Chris Lattner
3075a4e94d Allow pseudos to have patterns, no functionality change 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23988 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-25 20:58:43 +00:00
Jim Laskey
538421411a Added InstrSchedClass to each of the PowerPC Instructions. 
Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23830 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-19 19:51:16 +00:00
Nate Begeman
2d5aff761d Write patterns for the various shl and srl patterns that don't involve 
doing something clever.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23824 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-19 18:42:01 +00:00
Chris Lattner
617742b1b8 Nuke PowerPCInstrFormats.h, its contents are dead. Remove the definitions 
from the .td file that correspond to it


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23736 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-14 22:44:13 +00:00
Chris Lattner
67ab118a6d Add a bunch of patterns for F64 FP ops, add some more integer ops 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23533 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-29 23:34:24 +00:00
Chris Lattner
bfde080ce0 add patterns for x?oris? 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23268 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-08 17:40:49 +00:00
Chris Lattner
3e63ead49b add patterns to the addi/addis/mulli etc instructions. Define predicates 
for matching signed 16-bit and shifted 16-bit ppc immediates


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23267 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-08 17:33:10 +00:00
Chris Lattner
d1cdc7028c Add patterns for some new instructions, allowing the use of the ineg fragment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23266 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-08 17:01:54 +00:00
Chris Lattner
6159fb20c2 Add AND/OR/XOR 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23232 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-02 22:35:53 +00:00
Chris Lattner
218a15d02c Add some initial patterns to simple binary instructions, though they 
currently don't do anything.  This elides patterns for binary operators
that ping on the carry flag, since we don't model it yet.

This patch also removes PPC::SUB, because it is dead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23230 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-02 21:18:00 +00:00
Nate Begeman
6718f11feb Fix JIT encoding of conditional branches 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23076 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-26 04:11:42 +00:00
Nate Begeman
394cd13ba3 Fix JIT encoding of ppc mfocrf instruction; the operands were reversed 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22707 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-08 20:04:52 +00:00
Chris Lattner
14522e31d9 switch over the rest of the formats that use RC to use isDOT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21352 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-19 05:21:30 +00:00
Chris Lattner
883059fb58 Convert the XForm instrs and XSForm instruction over to use isDOT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21351 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-19 05:15:18 +00:00
Chris Lattner
97a2d42999 Now that the ppc64 and vmx operands of I are always 0, forward substitute 
them away.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21350 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-19 05:05:22 +00:00
Chris Lattner
a611ab72ca convert over bform and iform instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21349 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-19 05:00:59 +00:00
Chris Lattner
57226fbc7b Convert over DForm and DSForm instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21348 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-19 04:59:28 +00:00
Chris Lattner
e19d0b1130 Convert XLForm and XForm instructions over to use PPC64 when appropriate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21347 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-19 04:51:30 +00:00
Chris Lattner
5035cef732 Convert XO XS and XFX forms to use isPPC64 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21346 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-19 04:40:07 +00:00
Chris Lattner
0bdc6f1fd4 Turn PPC64 and VMX into classes that can be added to instructions instead of 
bits that must be passed up the inheritance hierarchy.  Convert MForm and AForm
instructions over


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21345 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-19 04:32:54 +00:00
Nate Begeman
16ac709c63 Change codegen for setcc to read the bit directly out of the condition 
register.  Added support in the .td file for the g5-specific variant
  of cr -> gpr moves that executes faster, but we currently don't
  generate it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21314 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-18 02:43:24 +00:00
Nate Begeman
ef7288c824 Add the necessary support to codegen condition register logical ops with 
register allocated condition registers.  Make sure that the printed
  output is gas compatible.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21295 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-14 03:20:38 +00:00
Nate Begeman
7af0248af4 Initial support for allocation condition registers 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21246 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-12 07:04:16 +00:00
Chris Lattner
6b4ea2cfa2 Revert the previous patch, which I didn't mean to check in. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21226 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-11 15:03:41 +00:00
Chris Lattner
26d4fdb968 Fix a minor bug (ORo didn't mark that it set CR0). 
Refactor how . instructions are handled.  In particular, instead of passing
the RC flag all the way up the inheritance hierarchy, just make a new tblgen
class 'DOT' which can be added to an instruction definition.

For example, instead of this:

-def AND  : XForm_6<31,  28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-let Defs = [CR0] in
-def ANDo : XForm_6<31,  28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-                   "and. $rA, $rS, $rB">;

We now have this:

+def AND  : XForm_6<31,  28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
                    "and $rA, $rS, $rB">;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21225 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-11 15:01:39 +00:00
Chris Lattner
5cbf3bc202 Fix encoding of fsel, fixing olden/power, McCat/bisort and several others. 
All of Olden passes now! :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18227 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-25 04:11:07 +00:00
Chris Lattner
cd61ec837f Fix encoding of swari, fixing several programs, including Olden/mst 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18225 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-25 03:40:20 +00:00
Chris Lattner
69efbdd4f3 Fix a few more tests by encoding the extsb and other XForm11 instructions 
correctly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18200 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-24 03:52:02 +00:00
Chris Lattner
2f5091ac2a Fix the encoding of ORi and other DForm4 instructions. This brings us to 
36/42 SingleSource/UnitTests passing!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18199 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-24 02:15:41 +00:00
Chris Lattner
310a752872 Branch instructions explicitly represent CRx in them. bEcause of this, encode 
them explicitly as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18193 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-24 01:15:19 +00:00
Chris Lattner
5afa9af81b Fix the encoding of OR, AND and many other instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18174 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-23 21:17:35 +00:00
Chris Lattner
d162032013 Remove argtype and argcount magic, which was used by the old asmprinter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18170 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-23 20:41:34 +00:00
Chris Lattner
89d60de90e Fix encoding of rlwinm? 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18165 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-11-23 19:23:32 +00:00
Misha Brukman
bd7780bc60 DForm_1, particularly used by store instructions, needs the immediate operand to 
be listed second as that is how the instructions are usually created (and is the
correct asm syntax) so that it's assembled correctly from its constituents


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17183 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-23 06:08:38 +00:00
Misha Brukman
a671f3b1d4 There is only one field in an instruction, and that is `Inst', the final view of 
the instruction binary format, all others are simply operands and should not
have the `field' label


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16978 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-14 05:55:37 +00:00
Nate Begeman
ed42853be1 All PPC instructions are now auto-printed 
32 and 64 bit AsmWriters unified
Darwin and AIX specific features of AsmWriter split out


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16163 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-04 05:00:00 +00:00
Nate Begeman
b7a8f2cdaa Convert remaining X-Form and Pseudo instructions over to asm writer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16142 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-02 08:13:00 +00:00
Nate Begeman
cc8bd9ca7c convert M and MD form instructions to generated asm writer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16121 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-31 02:28:08 +00:00
Nate Begeman
07aada8b0f Move yet more instructions over to being printed by the generated asm writer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16112 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-30 02:28:06 +00:00
Nate Begeman
6b3dc55ef8 Convert A-Form instructions to auto-generated asm writer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16107 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-29 22:45:13 +00:00
Nate Begeman
c3306120cc Move XForm instructions over to the auto-generated asm writer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15962 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-21 05:56:39 +00:00
Chris Lattner
0ea3171fbf Convert all of the DForm_6* operations, which makes all of the Zimm16 users 
dead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15754 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-15 05:46:14 +00:00
Chris Lattner
97b2a2e389 Convert the DForm_4 over to the asmprintergen 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15751 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-15 05:20:16 +00:00
Nate Begeman
244e64ead2 Add some more 64 bit instructions we need for the PowerPC-64 ISel to the tablegen files 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15710 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-13 02:19:26 +00:00
Misha Brukman
f1f6cef161 Add support for 64-bit CMPDI, CMPLDI, and CMPLD opcodes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15667 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-11 20:56:14 +00:00
Misha Brukman
96b6110685 Add doubleword load/store (64-bit only). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15665 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-11 15:54:36 +00:00
Misha Brukman
5b5708106e Renamed PPC32 (namespace for regs, opcodes) to PPC to include 64-bit targets 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15631 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-10 22:47:03 +00:00