Jim Grosbach
3197380143
Add ARM heuristic for when to allocate a virtual base register for stack
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access. rdar://8277890&7352504
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111968 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 21:19:33 +00:00
Daniel Dunbar
fba88d49e3
MC/X86: Tweak imul recognition, previous hack only applies for the imul form
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taking immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111950 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 19:37:56 +00:00
Daniel Dunbar
ae528f65ba
MC/X86: Add custom hack for recognizing "imul $12, %eax" and friends.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111947 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 19:24:18 +00:00
Daniel Dunbar
ee9102587e
MC/X86: Warn on scale factors > 1 without index register, instead of erroring,
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for 'as' compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111945 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 19:13:38 +00:00
Jim Grosbach
a273442891
Move enabling the local stack allocation pass into the target where it belongs.
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For now it's still a command line option, but the interface to the generic
code doesn't need to know that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111942 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 19:05:43 +00:00
Jim Grosbach
cd59dc5e81
add ARM cmd line option to force always using virtual base regs when possible.
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Intended to help ease reproducing problems by increasing base register usage
after heuristics for only using the when needed are in place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111930 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 18:04:52 +00:00
Dan Gohman
92b651fb19
Fix X86's isLegalAddressingMode to recognize that static addresses
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need not be RIP-relative in small mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111917 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 15:55:12 +00:00
Kalle Raiskila
55aebef654
Fix SPU BE to use all the available return registers.
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llc used to assert on the added testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111911 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 11:50:48 +00:00
Kalle Raiskila
f53fdc2e45
Remove some dead code from SPU BE that remained
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from 64bit vector support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111910 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 11:05:51 +00:00
Bruno Cardoso Lopes
8878e21fe6
Use pshufhw and pshuflw in more cases and fix getTargetShuffleNode number of arguments
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111890 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 01:16:15 +00:00
Bill Wendling
5e7044bd0e
Add comments for what the condition code symbols mean.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111889 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 01:11:30 +00:00
Eric Christopher
882d62e2db
Update comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111887 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 01:10:52 +00:00
Eric Christopher
2012c7bb7b
Fix the opcode and the operands for the load instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111885 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 01:10:04 +00:00
Eric Christopher
f06f309002
Add register class hack that needs to go away, but makes it more obvious
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that it needs to go away. Use loadRegFromStackSlot where possible.
Also, remember to update the value map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111883 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 00:50:47 +00:00
Eric Christopher
cb0b04ba6f
Add some more debugging code, make it more obvious that RegOffset is
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getting an address for an object and select some default values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111871 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 00:07:24 +00:00
Eric Christopher
1dfb4d31e0
Don't need the extra register here.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111864 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-23 23:28:04 +00:00
Eric Christopher
8654c71e56
Add some more "get address into register" code and a more TODOs/FIXMEs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111860 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-23 23:14:31 +00:00
Eric Christopher
7fe55b739c
Add an ARMFunctionInfo member and use it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-23 22:32:45 +00:00
Eric Christopher
8300712c1e
Start getting ARM loads/address computation going.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111850 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-23 21:44:12 +00:00
Bruno Cardoso Lopes
3efc0778c9
Start using target speficic nodes for shuffles: pshufhw and pshuflw
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111837 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-23 20:41:02 +00:00
Gabor Greif
11bc1652c9
tyops
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111835 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-23 20:30:51 +00:00
Chris Lattner
d80c7e1232
Add a new llvm.x86.int intrinsic, allowing access to the
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x86 int and int3 instructions. Patch by Peter Housel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111831 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-23 19:39:25 +00:00
Chris Lattner
b7f243a638
random improvement for variable shift codegen.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111813 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-23 17:30:29 +00:00
Anton Korobeynikov
4654a07e25
Revert invalid r111792. Jump tables are not broken on x86-64 / coff,
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it's COFF emitter which does not support differences of two symbols
(and needs to be fixed). GAS is pretty fine with code produced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111801 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-23 07:38:51 +00:00
Michael J. Spencer
3464cec4d8
Workaround broken jump tables on x86-64 COFF.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111792 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-23 04:45:37 +00:00
Anton Korobeynikov
699647cabc
Use rip-rel addressing on win64 by default. For this we just
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defaults to small pic code model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111741 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-21 17:21:11 +00:00
Michael J. Spencer
da0bfcdaf9
MC: Add partial x86-64 support to COFF.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111728 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-21 05:58:13 +00:00
Dan Gohman
8bef744518
Fix x86 fast-isel's cmp+branch folding to avoid folding when the
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comparison is in a different basic block from the branch. In such
cases, the comparison's operands may not have initialized virtual
registers available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111709 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-21 02:32:36 +00:00
Bruno Cardoso Lopes
bf8154a439
Prepare LowerVECTOR_SHUFFLEv8i16 to use x86 target specific nodes directly
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111704 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-21 01:32:18 +00:00
Bruno Cardoso Lopes
3157ef1c13
This is the first step towards refactoring the x86 vector shuffle code. The
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general idea here is to have a group of x86 target specific nodes which are
going to be selected during lowering and then directly matched in isel.
The commit includes the addition of those specific nodes and a *bunch* of
patterns, and incrementally we're going to switch between them and what we
have right now. Both the patterns and target specific nodes can change as
we move forward with this work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111691 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-20 22:55:05 +00:00
Bill Wendling
55ae515f9d
Create the new linker type "linker_private_weak_def_auto".
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It's similar to "linker_private_weak", but it's known that the address of the
object is not taken. For instance, functions that had an inline definition, but
the compiler decided not to inline it. Note, unlike linker_private and
linker_private_weak, linker_private_weak_def_auto may have only default
visibility. The symbols are removed by the linker from the final linked image
(executable or dynamic library).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111684 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-20 22:05:50 +00:00
Bob Wilson
b31a11b466
Replace the arm.neon.vmovls and vmovlu intrinsics with vector sign-extend and
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zero-extend operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111614 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-20 04:54:02 +00:00
Eric Christopher
f762fbe4fa
Fix loop conditionals (MO.isDef() asserts that it's a reg) and
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move some constraints around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111594 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-20 00:36:24 +00:00
Eric Christopher
cb59229a4a
Add a couple of random comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111592 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-20 00:20:31 +00:00
Jim Grosbach
e2f556933e
Better handling of offsets on frame index references. rdar://8277890
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111585 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-19 23:52:25 +00:00
Jim Grosbach
74d7b0af58
Add Thumb1 support for virtual frame indices.
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rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111533 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-19 17:52:13 +00:00
Eric Christopher
979e0a1414
Silence warning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111518 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-19 15:35:27 +00:00
Chris Lattner
59f8a6a666
fix PR7465, mishandling of lcall and ljmp: intersegment long
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call and jumps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111496 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-19 01:18:43 +00:00
Chris Lattner
efbdc8e236
minor progress towards fixing PR7465
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111494 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-19 01:00:34 +00:00
Eric Christopher
456144eb14
Add an AddOptionalDefs method and use it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111489 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-19 00:37:05 +00:00
Bill Wendling
f0e132c385
Add the "isCompare" attribute to the defm instead of each individual instr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111481 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-19 00:05:48 +00:00
Jakob Stoklund Olesen
7552a3df39
Don't call Predicate_* in Mips.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111468 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18 23:56:46 +00:00
Eric Christopher
d96b02b3d6
Remove extra header.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111456 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18 23:38:16 +00:00
Jim Grosbach
2b1e202e1c
Enable ARM base register reuse to local stack slot allocation. Whenever a new
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frame index reference to an object in the local block is seen, check if
it's near enough to any previously allocaated base register to re-use.
rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111443 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18 22:44:49 +00:00
Bill Wendling
ad422718f9
Minor simplification. Gets rid of a needless temporary.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111430 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18 21:32:07 +00:00
Bill Wendling
86b98b5874
Marked with ATTRIBUTE_USED so that clang doesn't complain.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111383 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18 18:40:57 +00:00
Jim Grosbach
74d803a58c
Add hook for re-using virtual base registers for local stack slot access.
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Nothing fancy, just ask the target if any currently available base reg
is in range for the instruction under consideration and use the first one
that is. Placeholder ARM implementation simply returns false for now.
ongoing saga of rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111374 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18 17:57:37 +00:00
Kalle Raiskila
ca9460f5a0
Fix a bug with insertelement on SPU.
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The previous algorithm in LowerVECTOR_SHUFFLE
didn't check all requirements for "monotonic" shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111361 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18 10:20:29 +00:00
Kalle Raiskila
86a791284a
Remove all traces of v2[i,f]32 on SPU.
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The "half vectors" are now widened to full size by the legalizer.
The only exception is in parameter passing, where half vectors are
expanded. This causes changes to some dejagnu tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18 10:04:39 +00:00
Kalle Raiskila
44ff5f5435
Change SPU C calling convention to match that described in
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"SPU Application Binary Interface Specification, v1.9" by
IBM.
Specifically: use r3-r74 to pass parameters and the return value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111358 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18 09:50:30 +00:00
Chris Lattner
2bde78206d
remove some dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111345 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18 02:42:11 +00:00
Chris Lattner
0d857cf8d1
remove some code that is dead now that lea's are modeled with segment registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111343 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18 02:40:44 +00:00
Bob Wilson
2003bcfbd2
Expand ZERO_EXTEND operations for NEON vector types.
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Testcase from Nick Lewycky.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111341 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18 01:45:52 +00:00
Jim Grosbach
dc140c6e7b
Add materialization of virtual base registers for frame indices allocated into
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the local block. Resolve references to those indices to a new base register.
For simplification and testing purposes, a new virtual base register is
allocated for each frame index being resolved. The result is truly horrible,
but correct, code that's good for exercising the new code paths.
Next up is adding thumb1 support, which should be very simple. Following that
will be adding base register re-use and implementing a reasonable ARM
heuristic for when a virtual base register should be generated at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111315 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 22:41:55 +00:00
Anton Korobeynikov
5dad73cec8
Revert part of one of the prev. patches - tailjmp will follow later.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111291 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 21:08:28 +00:00
Anton Korobeynikov
3a1e54a6b9
More fixes for win64:
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- Do not clobber al during variadic calls, this is AMD64 ABI-only feature
- Emit wincall64, where necessary
Patch by Cameron Esfahani!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111289 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 21:06:07 +00:00
Anton Korobeynikov
e9df15e65c
Enable more win64 calls folding opportunities.
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Patch by Cameron Esfahani!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111288 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 21:06:01 +00:00
Jakob Stoklund Olesen
00d3dda86f
Don't call tablegen'ed Predicate_* functions in the ARM target.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111277 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 20:39:04 +00:00
Jim Grosbach
c5ed0134a7
80 column cleanup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111266 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 18:39:16 +00:00
Jakob Stoklund Olesen
4bb862d179
Don't call Predicate_* methods directly from Sparc target.
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Modernize predicates a bit.
The Predicate_* methods are not used by TableGen any longer. They are only
emitted for the sake of legacy code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111263 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 18:17:12 +00:00
Jim Grosbach
8708ead5a4
Add hook to examine an instruction referencing a frame index to determine
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whether to allocate a virtual frame base register to resolve the frame
index reference in it. Implement a simple version for ARM to aid debugging.
In LocalStackSlotAllocation, scan the function for frame index references
to local frame indices and ask the target whether to allocate virtual
frame base registers for any it encounters. Purely infrastructural for
debug output. Next step is to actually allocate base registers, then add
intelligent re-use of them.
rdar://8277890
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111262 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 18:13:53 +00:00
Jim Grosbach
3edb904927
explicitly handle no-op cases for clarity. Fixes clang warning.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111260 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 18:00:41 +00:00
Bob Wilson
f955f290c9
Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid
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printing "lsl #0 ". This fixes the remaining parts of pr7792. Make
corresponding changes for encoding/decoding these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111251 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 17:23:19 +00:00
Chris Lattner
23e70ebf35
fix emacs language spec's, patch by Edmund Grimley-Evans!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111241 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 16:20:04 +00:00
Bob Wilson
7aaf5bf3db
Allow more cases of undef shuffle indices and add tests for them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111226 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 05:54:34 +00:00
Eric Christopher
0fe7d54732
Copy over some overridden MI wrappers for ARM fast-isel. This is where
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we're adding predicates and optional defs to the MachineInstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111222 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 01:25:29 +00:00
Eric Christopher
038fea5e30
Make arm fast-isel possible to enable via command line.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111219 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 00:46:57 +00:00
Bob Wilson
ca5e47d3f8
Ignore undef shuffle indices when checking for a VTRN shuffle. Radar 8290937.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111208 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-16 23:37:17 +00:00
Bob Wilson
dc66edaced
Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee
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that the high halfword is zero. The shift need not be exactly 16 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111196 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-16 22:26:55 +00:00
Eli Friedman
bc1fb2b6fa
Comment out some broken/unused/useless instructions which mess up disassembly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111185 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-16 21:18:51 +00:00
Eli Friedman
321473d51d
Don't attempt to SimplifyShortMoveForm in 64-bit mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111182 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-16 21:03:32 +00:00
Matt Fleming
453db50333
Hookup ELF support for X86.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111173 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-16 18:36:14 +00:00
Bob Wilson
22f5dc79c0
Rename sat_shift operand to shift_imm, in preparation for using it for other
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instructions besides saturate instructions. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111168 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-16 18:27:34 +00:00
Jakob Stoklund Olesen
de78f05cf7
Partially revert r111155. It looks like MSVC is calling an operator<() that
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clang says is unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111167 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-16 18:24:54 +00:00
Jakob Stoklund Olesen
a649ab542d
Remove unused functions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111155 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-16 17:18:18 +00:00
Bob Wilson
45cdd7fd61
Remove unused code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111154 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-16 17:06:03 +00:00
Argyrios Kyrtzidis
8c8b9ee8c8
Revert r111082. No warnings for this common pattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111102 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-15 10:27:23 +00:00
Eric Christopher
c0b2a2018a
Rework how the non-sse2 memory barrier is lowered so that the
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encoding is correct for the built-in assembler.
Based on a patch from Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111083 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-14 21:51:50 +00:00
Argyrios Kyrtzidis
7268d97ae6
Add ATTRIBUTE_UNUSED to methods that are not supposed to be used.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111082 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-14 21:35:10 +00:00
Chris Lattner
132929aa9e
improve indentation
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111073 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-14 17:26:09 +00:00
Bob Wilson
136e491280
T2I_rbin_irs rr variant is for disassembly only, so don't provide a pattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111068 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-14 03:18:29 +00:00
Bob Wilson
20d8e4e7aa
Add a Thumb2 t2RSBrr instruction for disassembly only.
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This fixes another part of PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111057 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-13 23:24:25 +00:00
Bob Wilson
703af3ab12
Temporarily disable tail calls on ARM to work around some linker problems.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111050 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-13 22:43:33 +00:00
Bob Wilson
38aa2871fc
Move the Thumb2 SSAT and USAT optional shift operator out of the
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instruction opcode. This fixes part of PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111047 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-13 21:48:10 +00:00
Bruno Cardoso Lopes
30baa63474
Add comments to some pattern fragments in x86
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111041 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-13 20:39:01 +00:00
Bob Wilson
6daf2a254b
Refactor the code for disassembling Thumb2 saturate instructions along the
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same lines as the change I made for ARM saturate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111029 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-13 19:04:21 +00:00
Dale Johannesen
1b4051095d
Revert 110491. While not wrong, it was based on a
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misanalysis and is undesirable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111028 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-13 18:43:45 +00:00
Bruno Cardoso Lopes
bb0a9489e0
Fix comment to reflect code, and remove an unused argument
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111022 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-13 17:50:47 +00:00
Bruno Cardoso Lopes
bbadd39bbb
Improve comment to make explicit why not to touch this could before JIT goes MC
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111021 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-13 17:44:10 +00:00
Eric Christopher
63f02ac349
Revert last patch and r110954 as I meant to.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111001 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-13 02:37:50 +00:00
Eric Christopher
4404c00db6
Revert r110954 for now, pseudo instructions can't make it through to the JIT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111000 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-13 02:30:00 +00:00
Bruno Cardoso Lopes
64baddc0f2
Some small clean-up: use of pseudo instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110954 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 20:55:18 +00:00
Johnny Chen
1adc40cac3
Cleaned up the for-disassembly-only entries in the arm instruction table so that
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the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110951 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 20:46:17 +00:00
Evan Cheng
719510a178
Make sure ARM constant island pass does not break up an IT block. If the split point is in the middle of an IT block, it should move it up to just above the IT instruction. rdar://8302637
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110947 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 20:30:05 +00:00
Bruno Cardoso Lopes
642eb02045
- Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary.
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- Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too.
- Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX.
- Add a testcase for a simple 128-bit zero vector creation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110946 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 20:20:53 +00:00
Bruno Cardoso Lopes
6da9cee0f1
Define AVX 128-bit pattern versions of SET0PS/PD.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110937 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 18:20:59 +00:00
Bruno Cardoso Lopes
4d04362813
Fix comment order
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110898 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 02:08:52 +00:00
Bruno Cardoso Lopes
8c05a850f4
Begin to support some vector operations for AVX 256-bit intructions. The long
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term goal here is to be able to match enough of vector_shuffle and build_vector
so all avx intrinsics which aren't mapped to their own built-ins but to
shufflevector calls can be codegen'd. This is the first (baby) step, support
building zeroed vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110897 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 02:06:36 +00:00
Johnny Chen
270159fcc2
The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td
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entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.
Added a "usat" test case to arm-tests.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110894 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 01:40:54 +00:00
Daniel Dunbar
09062b1672
MC/X86/AsmParser: Give an explicit error message when we reject an instruction
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because it could have an ambiguous suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110890 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12 00:55:42 +00:00