Commit Graph

422 Commits

Author SHA1 Message Date
Jim Grosbach
fb8989e640 ARM parsing and encoding of SBFX and UBFX.
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136264 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 21:09:25 +00:00
Jim Grosbach
7032741e7b ARM cleanup of remaining extend instructions.
Refactor the rest of the extend instructions to not artificially distinguish
between a rotate of zero and a rotate of any other value. Replace the by-zero
versions with Pat<>'s for ISel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136226 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 17:48:13 +00:00
Jim Grosbach
c5a8c861c9 ARM extend instructions simplification.
Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not
have an 'r' and an 'r_rot' version, but just a single version with a rotate
that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136225 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 16:47:19 +00:00
Jim Grosbach
45f3929ef0 ARM rot_imm printing adjustment.
Allow the rot_imm operand to be optional. This sets the stage for refactoring
away the "rr" versions from the multiclasses and replacing them with Pat<>s.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136154 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 21:44:37 +00:00
Jim Grosbach
85bfd3b023 ARM cleanup of rot_imm encoding.
Start of cleaning this up a bit. First step is to remove the encoder hook by
storing the operand as the bits it'll actually encode to so it can just be
directly used. Map it to the assembly source values 8/16/24 when we print it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136152 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 21:28:43 +00:00
Jim Grosbach
f49433523e ARM assembly parsing and encoding for SSAT16 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136006 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 23:09:14 +00:00
Jim Grosbach
580f4a9c1c ARM assembly parsing and encoding for SSAT instruction.
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').

Add tests for diagnostics and proper encoding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 22:20:28 +00:00
Jim Grosbach
4a5ffb399f ARM SSAT instruction 5-bit immediate handling.
The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield.
Update the representation such that we store the operand as 0-31, allowing us
to remove the encoder method and the special case handling in the disassembler.
Update the assembly parser and the instruction printer accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135823 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 23:16:18 +00:00
Jim Grosbach
7c9fbc0340 ARM assembly parsing and encoding for SMC instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135782 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 18:13:31 +00:00
Jim Grosbach
1769a3df4a Tidy up a bit.
Move common definitions for ARM and Thumb2 into ARMInstrFormats.td and rename
them to be a bit more descriptive that they're for the PKH instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135617 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 20:49:03 +00:00
Jim Grosbach
a0472dc420 ARM: Tidy up representation of PKH instruction.
The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't
be also encoded as part of the shift value immediate. Otherwise we're able to
represent invalid instructions, plus it needlessly complicates the
representation. Preparatory work for asm parsing of these instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135616 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 20:32:09 +00:00
Jim Grosbach
ccfd9313d1 ARM assembly parsing for MRC/MRC2/MRRC/MRRC2.
Add range checking to the immediate operands. Update tests accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135521 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 20:35:35 +00:00
Jim Grosbach
ffa3225e26 ARM assembly parsing for MOV (immediate).
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135500 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 19:13:28 +00:00
Jim Grosbach
c8ae39e746 ARM MCRR/MCRR2 immediate operand range checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135192 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 21:26:42 +00:00
Jim Grosbach
e540c7422c ARM MCR/MCR2 assembly parsing operand constraints.
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 21:19:17 +00:00
Owen Anderson
16884415db Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 23:22:26 +00:00
Jim Grosbach
6f9f884502 ARM Assembler support for DBG instruction.
Add range checking and testing for parsing and encoding of DBG instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135102 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:59:38 +00:00
Jim Grosbach
1cbb0c16a1 Revert 135093. Think-o.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135094 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:06:11 +00:00
Jim Grosbach
91eb0aa5de Correct range for thumb co-processor immediate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135093 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:03:11 +00:00
Jim Grosbach
83ab070fc1 Range checking for CDP[2] immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135092 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 22:01:08 +00:00
Jim Grosbach
e35c5e06fe Cleanup Thumb co-processor instructions a bit.
Combine redundant base classes and such. No indended functional change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135085 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 21:35:10 +00:00
Jim Grosbach
0d8dae292a Parameterize away the ARM T1Cop class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135082 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 21:17:59 +00:00
Jim Grosbach
9bb098ad3a Fix predicates for Thumb co-processor instructions.
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135081 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13 21:14:23 +00:00
Jim Grosbach
af7f2d6b67 Use tPseudoExpand for tTAILJMPd and tTAILJMPdND.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134732 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 20:32:21 +00:00
Jim Grosbach
53e3fc463e Use TableGen'erated pseudo lowering for ARM.
Hook up the TableGen lowering for simple pseudo instructions for ARM and
use it for a subset of the many pseudos the backend has as proof of concept.

More conversions to come.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134705 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 17:40:42 +00:00
Jim Grosbach
a7603982db ARMv7M vs. ARMv7E-M support.
The DSP instructions in the Thumb2 instruction set are an optional extension
in the Cortex-M* archtitecture. When present, the implementation is considered
an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation."

Add a subtarget feature hook for the v7e-m instructions and hook it up. The
cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is
a v7e-m implementation.

rdar://9572992



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134261 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 21:12:19 +00:00
Jim Grosbach
efeedceb41 Pseudo-ize t2MOVCC[ri].
t2MOVCC[ri] are just t2MOV[ri] instructions, so properly pseudo-ize them.
The Thumb1 versions, tMOVCC[ri] were only present for use by the size-
reduction pass, so they're no longer necessary at all and can be deleted.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134242 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01 17:14:11 +00:00
Jim Grosbach
ff97eb0cf4 Pseudo-ize the Thumb tTPsoft instruction.
It's just a call to a special helper function. Get rid of the T2 variant
entirely, as it's identical to the Thumb1 version.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134178 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30 19:38:01 +00:00
Jim Grosbach
16f9924000 Pseudo-ize the t2LDMIA_RET instruction.
It's just a t2LDMIA_UPD instruction with extra codegen properties, so it
doesn't need the encoding information. As a side-benefit, we now correctly
recognize for instruction printing as a 'pop' instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134173 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30 18:25:42 +00:00
Jim Grosbach
f6fd90910a Remove redundant Thumb2 ADD/SUB SP instruction definitions.
Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the
stack pointer. It can just use the normal add-register-immediate encoding
since it can use all registers as a source, not just R0-R7. The extra
instruction definitions are just duplicates of the normal instructions with
the (not well enforced) constraint that the source register was SP.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134114 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29 23:25:04 +00:00
Jim Grosbach
adf7366771 ARM Thumb2 asm syntax optional destination operand for binary operators.
When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.

For example, the following two instructions are equivalent:
and r1, #ff
and r1, r1, #ff

rdar://9672867



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133973 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 00:19:13 +00:00
Jim Grosbach
6b8f1e35ea ARM Assembly support for Thumb mov-immediate.
Correctly parse the forms of the Thumb mov-immediate instruction:
  1. 8-bit immediate 0-255.
  2. 12-bit shifted-immediate.

The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic,
but is not yet supported. More parser logic necessary there due to fixups.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133966 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 23:54:06 +00:00
Evan Cheng
734f63bed9 Reorg. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133533 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-21 19:00:54 +00:00
Evan Cheng
9568e5c3c3 Teach dag combine to match halfword byteswap patterns.
1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8)
   => (bswap x) >> 16
2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8))
   => (rotl (bswap x) 16)

This allows us to eliminate most of the def : Pat patterns for ARM rev16
revsh instructions. It catches many more cases for ARM and x86.

rdar://9609108


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133503 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-21 06:01:08 +00:00
Evan Cheng
6d6c55bc27 Add an alternative rev16 pattern. We should figure out a better way to handle these complex rev patterns. rdar://9609108
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133289 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-17 20:47:21 +00:00
Evan Cheng
f60ceac9cd Another revsh pattern. rdar://9609059
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133064 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15 17:17:48 +00:00
Jim Grosbach
f921c0fe34 Clean up a few 80 column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132946 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-13 22:54:22 +00:00
Andrew Trick
a1099f184d Fix for setjmp/longjmp exception handling on ARM. setjmp clobbers CPSR.
rdar://problem/9556069


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132699 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-07 00:08:49 +00:00
Bruno Cardoso Lopes
895c1e2dee Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value
must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132324 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31 03:33:27 +00:00
Bruno Cardoso Lopes
a0112d0c39 Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairs
to load/store i64 values. Since there's no current support to explicitly
declare such restrictions, implement it by using specific hardcoded register
pairs during isel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132248 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28 04:07:29 +00:00
Cameron Zwarich
d6ffcd88ba Actually, the address operand of the Thumb2 LDREX / STREX instructions *can*
take r13, so we can just make it a GPR. This fixes PR8825.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131507 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 23:26:20 +00:00
Cameron Zwarich
3c60ff4f3d Correct a minor problem with the Thumb2 LDREX and STREX instruction encodings. They
were marked as taking a tGPR when in reality they take an rGPR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131506 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 23:11:12 +00:00
Jakob Stoklund Olesen
2944b4fe05 Mark ultra-super-registers QQQQ as call-clobbered instead of the D sub-registers.
LiveVariables doesn't understand that clobbering D0 and D1 completely overwrites
Q0, so if Q0 is live-in to a function, its live range will extend beyond a
function call that only clobbers D0 and D1. This shows up in the
ARM/2009-11-01-NeonMoves test case.

LiveVariables should probably implement the much stricter rules for physreg
liveness that RAFast imposes - a physreg is killed by the first use of any
alias.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130801 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 22:31:24 +00:00
Bruno Cardoso Lopes
0a69ba309f Fold ARM coprocessor intrinsics patterns into the instructions defs whenever
it's possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130764 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 17:29:29 +00:00
Bruno Cardoso Lopes
54ad87ab78 Add a few ARM coprocessor intrinsics. Testcases included
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130763 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 17:29:22 +00:00
Eli Friedman
c573e2c7ea Switch to ImmLeaf (which can be used by FastISel) for a few more common ARM/Thumb2 patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130552 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-29 22:48:03 +00:00
Andrew Trick
d49ffe8284 Teach Thumb2 isel to fold and->rotr ==> ROR.
Generalization of Nate Begeman's patch!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130502 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-29 14:18:15 +00:00
Eric Christopher
8f232d307a Let the immediate leaf pattern take transforms and switch the signed
immediate patterns in arm to using the pattern.

Handles rdar://9299434


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130386 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-28 05:49:04 +00:00
Andrew Trick
1c3af779fc Thumb2 and ARM add/subtract with carry fixes.
Fixes Thumb2 ADCS and SBCS lowering: <rdar://problem/9275821>.
t2ADCS/t2SBCS are now pseudo instructions, consistent with ARM, so the
assembly printer correctly prints the 's' suffix.

Fixes Thumb2 adde -> SBC matching to check for live/dead carry flags.

Fixes the internal ARM machine opcode mnemonic for ADCS/SBCS.
Fixes ARM SBC lowering to check for live carry (potential bug).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130048 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-23 03:55:32 +00:00
Johnny Chen
3a96122c4a Thumb2 BFC was insufficiently encoded.
rdar://problem/9292717


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129619 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 22:52:15 +00:00