Commit Graph

28183 Commits

Author SHA1 Message Date
Venkatraman Govindaraju
08da01c741 [Sparc] Add support for decoding 'swap' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203424 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-09 23:32:07 +00:00
Craig Topper
124c86ee4a [C++11] Add 'override' keyword to virtual methods that override their base class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203418 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-09 18:03:14 +00:00
NAKAMURA Takumi
e086782817 Revert r203230, "CodeGenPrep: sink extends of illegal types into use block."
It choked i686 stage2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203386 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-09 11:01:07 +00:00
Craig Topper
feb0113a1e De-virtualize some methods since they don't override anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203379 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-09 07:58:15 +00:00
Craig Topper
f2c9fef815 [C++11] Add 'override' keyword to virtual methods that override their base class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203378 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-09 07:44:38 +00:00
Chandler Carruth
36b699f2b1 [C++11] Add range based accessors for the Use-Def chain of a Value.
This requires a number of steps.
1) Move value_use_iterator into the Value class as an implementation
   detail
2) Change it to actually be a *Use* iterator rather than a *User*
   iterator.
3) Add an adaptor which is a User iterator that always looks through the
   Use to the User.
4) Wrap these in Value::use_iterator and Value::user_iterator typedefs.
5) Add the range adaptors as Value::uses() and Value::users().
6) Update *all* of the callers to correctly distinguish between whether
   they wanted a use_iterator (and to explicitly dig out the User when
   needed), or a user_iterator which makes the Use itself totally
   opaque.

Because #6 requires churning essentially everything that walked the
Use-Def chains, I went ahead and added all of the range adaptors and
switched them to range-based loops where appropriate. Also because the
renaming requires at least churning every line of code, it didn't make
any sense to split these up into multiple commits -- all of which would
touch all of the same lies of code.

The result is still not quite optimal. The Value::use_iterator is a nice
regular iterator, but Value::user_iterator is an iterator over User*s
rather than over the User objects themselves. As a consequence, it fits
a bit awkwardly into the range-based world and it has the weird
extra-dereferencing 'operator->' that so many of our iterators have.
I think this could be fixed by providing something which transforms
a range of T&s into a range of T*s, but that *can* be separated into
another patch, and it isn't yet 100% clear whether this is the right
move.

However, this change gets us most of the benefit and cleans up
a substantial amount of code around Use and User. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203364 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-09 03:16:01 +00:00
Duncan P. N. Exon Smith
f911d52a2c Change else if => if after return, after r203265
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203347 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-08 15:15:42 +00:00
Owen Anderson
7cf32a7893 Range-ify some for loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203306 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 22:48:22 +00:00
Eli Bendersky
32643e3673 Remove unused method declaration
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203301 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 22:19:10 +00:00
Tom Stellard
6cadd406cc R600/SI: Using SGPRs is illegal for instructions that read carry-out from VCC
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203281 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 20:12:39 +00:00
Tom Stellard
7e06370873 R600/SI: Custom lower i1 stores
These are sometimes created by the shrink to boolean optimization in the
globalopt pass.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203280 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 20:12:33 +00:00
Rafael Espindola
5abd4662b8 Don't avoid cfi instructions on the bg/p.
The integrated assembler now works for ppc. Since this was the last use of the
bg/p predicate and Hal says that it is now dead, drop the predicate too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203269 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 19:04:12 +00:00
Ted Kremenek
1a763b03eb Remove dead 'break' (dominated by 'return').
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203267 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 18:54:08 +00:00
Ted Kremenek
af0c5ed7e5 Remove dead 'return'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203265 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 18:51:16 +00:00
Nico Weber
f456d37c4f "Mac OS/X" -> "Mac OS X" spelling fixes for llvm.
Patch from Sean McBride <sean@rogue-research.com>!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203258 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 18:08:54 +00:00
Duncan P. N. Exon Smith
ac4c4a8844 ARM: Make .unreq directives case-insensitive
Be case-insensitive when processing .unreq directives.

Patch by Lin Zuojian!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203251 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 16:16:52 +00:00
Richard Sandiford
122a970111 [SystemZ] Move sign_extend optimization to PerformDAGCombine
The target was marking SIGN_EXTEND as Custom because it wanted to optimize
certain sign-extended shifts.  In all other respects the extension is Legal,
so it'd be better to do the optimization in PerformDAGCombine instead.

No functional change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203234 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 11:34:35 +00:00
Tim Northover
fa9e4b52f4 CodeGenPrep: sink extends of illegal types into use block.
This helps the instruction selector to lower an i64 * i64 -> i128
multiplication into a single instruction on targets which support it.

Patch by Manuel Jacob.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203230 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 11:04:30 +00:00
Tim Northover
69d2b2aa5a InstCombine: form shuffles from wider range of insert/extractelements
Sequences of insertelement/extractelements are sometimes used to build
vectorsr; this code tries to put them back together into shuffles, but
could only produce a completely uniform shuffle types (<N x T> from two
<N x T> sources).

This should allow shuffles with different numbers of elements on the
input and output sides as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203229 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 10:24:44 +00:00
Alexey Volkov
177c1ef30d Enable FeatureFastUAMem for Silvermont processor
Differential Revision: http://llvm-reviews.chandlerc.com/D2982


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203218 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 09:03:49 +00:00
Alexey Volkov
adaa3e5760 Test commit
Removed whitespace


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203216 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 08:28:44 +00:00
David Majnemer
508e0c4d34 MC: Remove superfluous section attribute flag definitions
Summary:
llvm/MC/MCSectionMachO.h and llvm/Support/MachO.h both had the same
definitions for the section flags.  Instead, grab the definitions out of
support.

No functionality change.

Reviewers: grosbach, Bigcheese, rafael

Reviewed By: rafael

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D2998

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203211 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 07:36:05 +00:00
Rafael Espindola
7d7d99622f Replace PROLOG_LABEL with a new CFI_INSTRUCTION.
The old system was fairly convoluted:
* A temporary label was created.
* A single PROLOG_LABEL was created with it.
* A few MCCFIInstructions were created with the same label.

The semantics were that the cfi instructions were mapped to the PROLOG_LABEL
via the temporary label. The output position was that of the PROLOG_LABEL.
The temporary label itself was used only for doing the mapping.

The new CFI_INSTRUCTION has a 1:1 mapping to MCCFIInstructions and points to
one by holding an index into the CFI instructions of this function.

I did consider removing MMI.getFrameInstructions completelly and having
CFI_INSTRUCTION own a MCCFIInstruction, but MCCFIInstructions have non
trivial constructors and destructors and are somewhat big, so the this setup
is probably better.

The net result is that we don't create temporary labels that are never used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203204 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 06:08:31 +00:00
Rafael Espindola
49dd5e831b Simplify. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203202 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 04:58:32 +00:00
Rafael Espindola
ab5573ef1b Simplify. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203199 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 04:45:03 +00:00
Saleem Abdulrasool
4eb048a6f1 Support: split object format out of environment
This is a preliminary setup change to support a renaming of Windows target
triples.  Split the object file format information out of the environment into a
separate entity.  Unfortunately, file format was previously treated as an
environment with an unknown OS.  This is most obvious in the ARM subtarget where
the handling for macho on an arbitrary platform switches to AAPCS rather than
APCS (as per Apple's needs).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203160 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 20:47:11 +00:00
Reid Kleckner
9035f6be4c MS asm: The initial dot in struct access is optional
Fixes PR18994.

Tests, once again, in that other repository.  =P

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203146 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 19:19:12 +00:00
Matt Arsenault
161e3a80b2 R600: Fix extloads from i8 / i16 to i64.
This appears to only be working for global loads. Private
and local break for other reasons.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203135 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 17:34:12 +00:00
Matt Arsenault
b4cd160bb9 R600/SI: Expand selects on vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203134 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 17:34:03 +00:00
Matt Arsenault
0c5c3b93d8 Fix missing C++ mode comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203133 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 17:33:58 +00:00
Richard Osborne
d530a96701 [XCore] Add support for the "m" inline asm constraint.
Summary:
This provides support for CP and DP relative global accesses in inline
asm.

Reviewers: robertlytton

Reviewed By: robertlytton

Differential Revision: http://llvm-reviews.chandlerc.com/D2943

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203129 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 16:37:48 +00:00
Chad Rosier
514d703ff6 [AArch64] This is a work in progress to provide a machine description
for the Cortex-A53 subtarget in the AArch64 backend.

This patch lays the ground work to annotate each AArch64 instruction
(no NEON yet) with a list of SchedReadWrite types. The patch also
provides the Cortex-A53 processor resources, maps those the the default
SchedReadWrites, and provides basic latency. NEON support will be added
in a subsequent patch with proper forwarding logic.

Verification was done by setting the pre-RA scheduler to linearize to
better gauge the effect of the MIScheduler. Even without modeling the
forward logic, the results show a modest improvement for Cortex-A53.

Reviewers: apazos, mcrosier, atrick
Patch by Dave Estes <cestes@codeaurora.org>!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203125 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 16:04:00 +00:00
Richard Sandiford
abe768029b [SystemZ] Remove "virtual" from override methods
Also fix a couple of cases where "override" was missing.  No behavioural
change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203110 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 12:03:36 +00:00
Richard Sandiford
0c3682a402 [SystemZ] Use "auto" for cast results
No functional change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203106 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 11:22:58 +00:00
Richard Sandiford
b653ed8545 [SystemZ] Use "for (auto" a bit
Just the simple cases for now.  There were a few knock-on changes of
MachineBasicBlock *s to MachineBasicBlock &s.  No functional change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203105 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 11:00:15 +00:00
Richard Sandiford
9a1cd05a3d [SystemZ] Update namespace formatting to match current guidelines
No functional change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203103 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 10:38:30 +00:00
Elena Demikhovsky
b0a3627443 AVX-512: Added rrk, rrkz, rmk, rmkz, rmbk, rmbkz versions of AVX512 FP packed instructions, added encoding tests for them.
By Robert Khazanov.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203098 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 08:45:30 +00:00
Elena Demikhovsky
f4623cee34 AVX-512: fixed comressed displacement - by Robert Khazanov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203096 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 08:15:35 +00:00
Yaron Keren
7bc835b7bf Cleaning up two more pre-Visual C++ 2012 build hacks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203093 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 08:05:43 +00:00
Chandler Carruth
67f6bf70d2 [Layering] Move InstVisitor.h into the IR library as it is pretty
obviously coupled to the IR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203064 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 03:23:41 +00:00
Hal Finkel
a14dc34e10 The PPC global base register cannot be r0
The global base register cannot be r0 because it might end up as the first
argument to addi or addis. Fixes PR18316.

I don't have a small stable test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203054 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 01:28:23 +00:00
Chandler Carruth
f4ec8bfaec [Layering] Move DebugInfo.h into the IR library where its implementation
already lives.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203046 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 00:46:21 +00:00
Hal Finkel
341ea7ddf6 Fixup PPC Darwin i1 argument handling
Like on other targets, we need to zero_extend/truncate i1 args before copying
them to GPRs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203045 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 00:45:19 +00:00
Hal Finkel
025c1cefca When using CR bit registers on PPC32, handle the i1 vaarg case
When copying an i1 value into a GPR for a vaarg call, we need to explicitly
zero-extend the i1 value (otherwise an invalid CRBIT -> GPR copy will be
generated).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203041 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 00:23:33 +00:00
Hal Finkel
f698d7775a With PPC CR bit registers, handle int_to_fp on older cores
On cores without fpcvt support, we cannot promote int_to_fp i1 operations,
because there is nothing to promote them to. The most straightforward
implementation of this uses a select to choose between the two possible
resulting floating-point values (and that's what is done here).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203015 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-05 22:14:00 +00:00
Matt Arsenault
af0cc459bf Fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203013 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-05 21:47:22 +00:00
Cameron McInally
f3ff7c32f7 Lower AVX v4i64->v4i32 truncate to one shuffle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202996 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-05 19:41:16 +00:00
David Blaikie
986a284592 Fix clang -Werror build break due to mismatched sign comparison.
Originally committed in r202985.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202992 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-05 18:53:36 +00:00
Oliver Stannard
0d31d1e612 ARM: Correctly align arguments after a byval struct is passed on the stack
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202985 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-05 15:25:27 +00:00
Joerg Sonnenberger
7c09fb6af2 Enable integrated assembler on OpenBSD/PPC32 by default, too.
From Brad Smith.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202967 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-05 11:37:04 +00:00
Vladimir Medic
6844c3f234 This patch implements .set dsp directive and sets appropriate feature bits.This directive is a counterpart of -mattr=dsp command line option with the exception that it does not influence elf header flags. The usage example is gives in test file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202966 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-05 11:05:09 +00:00
Evan Cheng
bc03027dd8 Remove a special character in comment that accidentially got committed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202905 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 22:56:57 +00:00
Reid Kleckner
a9a43d01f2 MS asm: Attempt to parse variables followed by a bracketed displacement
This is required to include MSVC's <atomic> header, which we do now in
LLVM.

Tests forthcoming in Clang, since that's where we test semantic inline
asm changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202865 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 17:57:01 +00:00
Saleem Abdulrasool
86e85c1115 X86: 80-column
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202863 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 17:11:46 +00:00
Will Schmidt
db09f822fd [PowerPC] support powerpc64le as syntax-checking target (pass2)
Register the Asm Printer for the ppc64le target.

This fills in a spot that was missed in an earlier change (r187179).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202861 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 16:51:52 +00:00
Richard Osborne
f41c05c7ca [XCore] Fix call of absolute address.
Previously for:

tail call void inttoptr (i64 65536 to void ()*)() nounwind

We would emit:

bl 65536

The immediate operand of the bl instruction is a relative offset so it is
wrong to use the absolute address here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202860 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 16:50:30 +00:00
Daniel Sanders
e06bec47d6 [mips][msa] Correct the behaviour of the COPY_FW pseudo on lanes 2 and 3.
Summary:
Previously, attempting to extract lanes 2 and 3 would actually extract lane 1.
The MSA CodeGen tests only covered lanes 0 and 1.

Differential Revision: http://llvm-reviews.chandlerc.com/D2935

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202848 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 13:54:30 +00:00
Chandler Carruth
ff956e7568 [Modules] Move the NoFolder into the IR library as it creates
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202834 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 12:05:47 +00:00
Chandler Carruth
03e36d752c [Modules] Move CFG.h to the IR library as it defines graph traits over
IR types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202827 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 11:45:46 +00:00
Chandler Carruth
7225e27b4c [Modules] Move ValueMap to the IR library. While this class does not
directly care about the Value class (it is templated so that the key can
be any arbitrary Value subclass), it is in fact concretely tied to the
Value class through the ValueHandle's CallbackVH interface which relies
on the key type being some Value subclass to establish the value handle
chain.

Ironically, the unittest is already in the right library.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202824 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 11:26:31 +00:00
Chandler Carruth
eb3d76da81 [Modules] Move ValueHandle into the IR library where Value itself lives.
Move the test for this class into the IR unittests as well.

This uncovers that ValueMap too is in the IR library. Ironically, the
unittest for ValueMap is useless in the Support library (honestly, so
was the ValueHandle test) and so it already lives in the IR unittests.
Mmmm, tasty layering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202821 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 11:17:44 +00:00
Chandler Carruth
4bbfbdf7d7 [Modules] Move CallSite into the IR library where it belogs. It is
abstracting between a CallInst and an InvokeInst, both of which are IR
concepts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202816 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 11:01:28 +00:00
Chandler Carruth
bd7cba0d81 [Modules] Move GetElementPtrTypeIterator into the IR library. As its
name might indicate, it is an iterator over the types in an instruction
in the IR.... You see where this is going.

Another step of modularizing the support library.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202815 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 10:40:04 +00:00
Chandler Carruth
876ac60880 [Modules] Move InstIterator out of the Support library, where it had no
business.

This header includes Function and BasicBlock and directly uses the
interfaces of both classes. It has to do with the IR, it even has that
in the name. =] Put it in the library it belongs to.

This is one step toward making LLVM's Support library survive a C++
modules bootstrap.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202814 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 10:30:26 +00:00
Chandler Carruth
1decd56b8d [cleanup] Re-sort all the includes with utils/sort_includes.py.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202811 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 10:07:28 +00:00
Vladimir Medic
7650bc0fd2 This patch implements .set mips32r2 directive and sets appropriate feature bits. It also introduces helper functions that are used to set and clear feature bits as necessary. This directive is a counterpart of -mips32r2 command line options with the exception that it does not influence elf header flags. The usage example is gives in test file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202807 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 09:54:09 +00:00
Yaron Keren
b62b44ccc5 Cleaning up a bunch of pre-Visual C++ 2012 build hacks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202806 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 09:23:33 +00:00
Kevin Qin
5dee350565 [AArch64]Fix improper diagnostics about offset range of load/store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202775 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 02:05:13 +00:00
Reid Kleckner
4e43e1e686 MC: Fix Intel assembly parser for [global + offset]
We were dropping the displacement on the floor if we also had some
immediate offset.

Should fix PR19033.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202774 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 00:33:17 +00:00
Chad Rosier
168a1af83c Revert "[AArch64] This is a work in progress to provide a machine description"
This reverts commit ff717c8fc786a0cfa1602982b91895fa09e514fc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202773 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 00:32:07 +00:00
Chad Rosier
824dfb1c56 [AArch64] This is a work in progress to provide a machine description
for the Cortex-A53 subtarget in the AArch64 backend.

This patch lays the ground work to annotate each AArch64 instruction
(no NEON yet) with a list of SchedReadWrite types. The patch also
provides the Cortex-A53 processor resources, maps those the the default
SchedReadWrites, and provides basic latency. NEON support will be added
in a subsequent patch with proper forwarding logic.

Verification was done by setting the pre-RA scheduler to linearize to
better gauge the effect of the MIScheduler. Even without modeling the
forward logic, the results show a modest improvement for Cortex-A53.

Reviewers: apazos, mcrosier, atrick
Patch by Dave Estes <cestes@codeaurora.org>!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202767 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-03 23:32:47 +00:00
Daniel Sanders
fc210ac1ef [mips] Prevent %lo relocation being used on MSA loads and stores.
Summary:
Parts of the compiler still believed MSA load/stores have a 16-bit offset when
it is actually 10-bit. Corrected this, and fixed a closely related issue this
uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS
respectively) could not load/store using offsets from the stack/frame pointer.
They accepted frameindex+offset, but not frameindex by itself.

Reviewers: jacksprat, matheusalmeida

Reviewed By: jacksprat

Differential Revision: http://llvm-reviews.chandlerc.com/D2888

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202717 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-03 14:31:21 +00:00
Ed Maste
c1e634da0c [mips] support FK_Data_2 and FK_Data_8 to fix big-endian debug data
This fixes invalid lengths in .debug_aranges on big-endian mips64
(lengths appear to be left-shifted by 32 bits) and in .debug_loc.

Differential Revision: http://llvm-reviews.chandlerc.com/D2517


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202716 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-03 14:27:49 +00:00
Vladimir Medic
6e983f35b4 Fixing a build failure reported by certain buildbots. This will disable jalx instruction for micromips target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202715 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-03 14:05:14 +00:00
Vladimir Medic
afa6150f04 This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202706 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-03 13:12:59 +00:00
Venkatraman Govindaraju
c594f39acb [Sparc] Add trap on integer condition codes (Ticc) instructions to Sparc backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202670 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 23:39:07 +00:00
Venkatraman Govindaraju
75bff895e4 [Sparc] Add return/rett instruction to Sparc backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202666 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 22:55:53 +00:00
Venkatraman Govindaraju
c4b0eecd83 [Sparc] Add support for decoding jmpl/retl/ret instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202663 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 21:17:44 +00:00
Venkatraman Govindaraju
833687be0e [Sparc] Add fcmpe* instructions to Sparc backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202661 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 19:56:19 +00:00
Venkatraman Govindaraju
cf06410678 [Sparc] Add VIS instructions to sparc backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202660 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 19:31:21 +00:00
Hal Finkel
5a49125fec Add a PPC inline asm constraint type for single CR bits
Now that the PowerPC backend can track individual CR bits as first-class
registers, we should also have a way of allocating them for inline asm
statements. Because these registers are only one bit, if an output variable is
implicitly cast to a larger integer size, we'll get an any_extend to that
larger type (this is part of the existing target-independent logic). As a
result, regardless of the size of the output type, only the first bit is
meaningful.

The constraint identifier "wc" has been chosen for this purpose. Although gcc
does not currently support allocating individual CR bits, this identifier
choice has been coordinated with the gcc PowerPC team, and will be marked as
reserved for this purpose in the gcc constraints.md file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202657 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 18:23:39 +00:00
Benjamin Kramer
a4f0aad951 [C++11] Replace llvm::tie with std::tie.
The old implementation is no longer needed in C++11.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202644 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 13:30:33 +00:00
Benjamin Kramer
d628f19f5d [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.
Remove the old functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202636 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 12:27:27 +00:00
Venkatraman Govindaraju
2871375882 [SparcV9] Adds support for branch on integer register instructions (BPr) and conditional moves on integer register (MOVr/FMOVr).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202628 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 09:46:56 +00:00
Elena Demikhovsky
a9fe27ffb3 AVX-512: Fixed extract_vector_elt for v8i1 vector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202624 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 09:19:44 +00:00
Craig Topper
629b96cb4f Switch all uses of LLVM_OVERRIDE to just use 'override' directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202621 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 09:09:27 +00:00
Craig Topper
4eb03f049e Switch all uses of LLVM_FINAL to just use 'final', and remove the macro.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202618 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 08:08:51 +00:00
Venkatraman Govindaraju
a21b315a06 [Sparc] Add support for parsing branches and conditional move instructions with %fcc1-%fcc3 conditional registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202616 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 06:28:15 +00:00
Venkatraman Govindaraju
18fe44cb05 [Sparc] Make floating point branch instruction formats to accept %fcc0-%fcc1 conditional registers as input.
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202614 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 04:43:45 +00:00
Venkatraman Govindaraju
afad335cae [Sparc] Add support for parsing fcmp with %fcc registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202610 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 03:39:39 +00:00
Venkatraman Govindaraju
243491693b [Sparc] Add register class for floating point conditional flags (%fcc0 - %fcc3).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202604 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 02:12:33 +00:00
Venkatraman Govindaraju
628886b1d2 [SparcV9] Add support for parsing branch instructions with prediction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202602 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-01 22:03:07 +00:00
Hal Finkel
92b38a9d1c Remove extra truncs/exts around i32 bit operations on PPC64
This generalizes the code to eliminate extra truncs/exts around i1 bit
operations to also do the same on PPC64 for i32 bit operations. This eliminates
a fairly prevalent code wart:

int foo(int a) {
  return a == 5 ? 7 : 8;
}

On PPC64, because of the extension implied by the ABI, this would generate:

	cmplwi 0, 3, 5
	li 12, 8
	li 4, 7
	isel 3, 4, 12, 2
	rldicl 3, 3, 0, 32
	blr

where the 'rldicl 3, 3, 0, 32', the extension, is completely unnecessary. At
least for the single-BB case (which is all that the DAG combine mechanism can
handle), this unnecessary extension is no longer generated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202600 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-01 21:36:57 +00:00
Venkatraman Govindaraju
e4c88dd909 [Sparc] Add support for parsing annulled branch instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202599 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-01 20:08:48 +00:00
Venkatraman Govindaraju
d4dafd17e1 [Sparc] Add support for parsing sparcv9 instructions addc/subc/addccc/subccc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202598 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-01 18:54:52 +00:00
Venkatraman Govindaraju
e1f5cd3002 [Sparc] Add missing ALU instruction patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202597 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-01 17:51:00 +00:00
Benjamin Kramer
ee5e607355 Now that we have C++11, turn simple functors into lambdas and remove a ton of boilerplate.
No intended functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202588 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-01 11:47:00 +00:00
Venkatraman Govindaraju
9314308db1 [Sparc] Add support to decode unimp instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202581 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-01 09:28:18 +00:00
Venkatraman Govindaraju
61f5c0a065 [Sparc] Add support to decode negative simm13 operands in the sparc disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202578 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-01 09:11:57 +00:00
Venkatraman Govindaraju
830156c660 [Sparc] Add support for decoding call instructions in the sparc disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202577 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-01 08:30:58 +00:00
Venkatraman Govindaraju
06f2e69c2f [Sparc] Add support to disassemble sparc memory instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202575 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-01 07:46:33 +00:00
Venkatraman Govindaraju
5ddaa6dcf4 [Sparc] Implement writeNopData. Emit actual NOP instruction instead of just filling with zeroes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202572 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-01 05:45:09 +00:00
Venkatraman Govindaraju
e0c7e3d139 [Sparc] Teach SparcAsmParser to emit correct relocations for PIC code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202571 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-01 05:07:21 +00:00
Venkatraman Govindaraju
f06322b3ef [Sparc] 80 column rule. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202565 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-01 02:28:34 +00:00
Venkatraman Govindaraju
17e9537004 [Sparc] Add support for parsing directives in SparcAsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202564 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-01 02:18:04 +00:00
Venkatraman Govindaraju
c9bf74fdc5 [Sparc] Emit 'restore' instead of 'restore %g0, %g0, %g0'. This improves the readability of the generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202563 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-01 01:04:26 +00:00
Tom Stellard
34faf78241 R600: Verify all instructions in the AsmPrinter on debug builds
Make a call to R600's implementation of verifyInstruction() to
check that instructions are only using legal operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202544 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 21:36:41 +00:00
Tom Stellard
9f0d68f522 R600/SI: Expand all v16[if]32 operations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202543 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 21:36:37 +00:00
Zoran Jovanovic
2a80d7db79 Fixed operand of SC microMIPS instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202526 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 18:22:56 +00:00
Zoran Jovanovic
5d945dbe5e Fixed encoding of SYSCALL microMIPS instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202523 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 18:17:08 +00:00
Zoran Jovanovic
8f883ae9d3 Revert revision 202518 because of wrong commit message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202521 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 18:14:16 +00:00
Zoran Jovanovic
60f8980545 Fix operand of SC instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202518 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 18:02:17 +00:00
Evgeniy Stepanov
2c4b1c4853 X86Operand is extracted into individual header.
X86Operand is extracted into individual header, because it allows to create an
arbitrary memory operand and append it to MCInst. It'll be reused in X86 inline
assembly instrumentation.

Patch by Yuri Gorshenin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202496 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 12:28:07 +00:00
NAKAMURA Takumi
bec8cee981 Reorder Mips/MCTargetDesc/CMakeLists.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202483 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 10:18:21 +00:00
Sasa Stankovic
99e493f16f [mips] Add MipsNaClELFStreamer.cpp to CMakeLists.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202482 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 10:14:12 +00:00
Sasa Stankovic
068a8c145a [mips] Implement NaCl sandboxing of indirect jumps:
* Align targets of indirect jumps to instruction bundle boundaries (in MI layer).
  * Add masking instructions before indirect jumps (in MC layer).

Differential Revision: http://llvm-reviews.chandlerc.com/D2847


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202479 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 10:00:38 +00:00
Hal Finkel
3d2ce7a5a7 Swap PPC isel operands to allow for 0-folding
The PPC isel instruction can fold 0 into the first operand (thus eliminating
the need to materialize a zero-containing register when the 'true' result of
the isel is 0). When the isel is fed by a bit register operation that we can
invert, do so as part of the bit-register-operation peephole routine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202469 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 06:11:16 +00:00
Hal Finkel
b7a2ea7228 Trying to unbreak the darwin11 builder
The CR bit tracking code broke PPC/Darwin; trying to get it working again...

(the darwin11 builder, which defaults to the darwin ABI when running PPC tests,
asserted when running test/CodeGen/PowerPC/inverted-bool-compares.ll)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202459 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 01:17:25 +00:00
Hal Finkel
ff455c0954 Try to unbreak the C++11 build
Cannot use negative numbers in case statements without running afoul of -Wc++11-narrowing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202455 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:45:27 +00:00
Hal Finkel
36e1825e68 Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:

 - Reduction in register pressure (because we no longer need GPRs to store
   boolean values).

 - Logical operations on booleans can be handled more efficiently; we used to
   have to move all results from comparisons into GPRs, perform promoted
   logical operations in GPRs, and then move the result back into condition
   register bits to be used by conditional branches. This can be very
   inefficient, because the throughput of these CR <-> GPR moves have high
   latency and low throughput (especially when other associated instructions
   are accounted for).

 - On the POWER7 and similar cores, we can increase total throughput by using
   the CR bits. CR bit operations have a dedicated functional unit.

Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).

This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.

It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
  trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
  zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).

POWER7 test-suite performance results (from 10 runs in each configuration):

SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup

SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 00:27:01 +00:00
Andrew Trick
4c34f71b81 Provide a target override for the latest regalloc heuristic.
This is a temporary workaround for native arm linux builds:
PR18996: Changing regalloc order breaks "lencod" on native arm linux builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202433 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 21:37:33 +00:00
Roman Divacky
14551f041b Lower FNEG just like FABS to fneg[ds] and fmov[ds], thus avoiding
expensive libcall. Also, Qp_neg is not implemented on at least
FreeBSD. This is also what gcc is doing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202422 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 19:26:29 +00:00
Adrian Prantl
4bd26ae070 Debug info: Remove ARMAsmPrinter::EmitDwarfRegOp(). AsmPrinter can now
scan the register file for sub- and super-registers.
No functionality change intended.

(Tests are updated because the comments in the assembler output are
different.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202416 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 17:56:08 +00:00
Richard Osborne
cc331c8f40 [XCore] Support functions returning more than 4 words.
If a function returns a large struct by value return the first 4 words
in registers and the rest on the stack in a location reserved by the
caller. This is needed to support the xC language which supports
functions returning an arbitrary number of return values. This is
r202397 reapplied with a fix to avoid an uninitialized read of a member.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202414 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 17:47:54 +00:00
Richard Osborne
870d997d8c [XCore] Make LowerCallResult a static function.
No functionality change. This is r202396 reapplied with no changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202413 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 17:47:48 +00:00
Rafael Espindola
b9e06b97ce Remove MCPureStreamer.
We moved MCJIT to use native object formats a long time ago and R600
now uses ELF, so it was dead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202408 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 16:17:34 +00:00
Richard Osborne
e4db795a4c Revert r202396, r202397.
These are causing test failures, revert for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202398 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 14:24:13 +00:00
Richard Osborne
ad4ffce35f [XCore] Support functions returning more than 4 words.
Summary:
If a function returns a large struct by value return the first 4 words
in registers and the rest on the stack in a location reserved by the
caller. This is needed to support the xC language which supports
functions returning an arbitrary number of return values.

Reviewers: robertlytton

Reviewed By: robertlytton

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D2889

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202397 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 14:00:40 +00:00
Richard Osborne
6257ef8732 [XCore] Make LowerCallResult a static function.
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202396 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 14:00:34 +00:00
Richard Osborne
c26292d4dc [XCore] Target optimized library function __memcpy_4()
Summary:
If the src, dst and size of a memcpy are known to be 4 byte aligned we
can call __memcpy_4() instead of memcpy().

Reviewers: robertlytton

Reviewed By: robertlytton

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D2871

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202395 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 13:39:07 +00:00
Richard Osborne
83eab939a4 [XCore] Add dag combines for instructions that ignore some input bits.
These instructions ignore the high bits of one of their input operands -
try and use this to simplify the code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202394 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 13:20:11 +00:00
Richard Osborne
ef174f733a [XCore] Provide information about known zero bits of resource instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202393 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 13:20:06 +00:00
Craig Topper
74be63b014 [X86] Fix Uses/Defs lists for INS, OUTS, SCAS, CMPS, LODS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202348 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 05:08:25 +00:00
Craig Topper
7e992687ad [X86] Add RAX/EAX/AX Uses/Defs to XCHG RAX/EAX/AX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202347 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 04:27:00 +00:00
Craig Topper
956ef7f165 [X86] Add RAX/EAX/AX/AL Uses/Defs to the absolute memory location move instructions. Patch by Florian Lukas with some additional instructions fixed by me. Fixes PR18975.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202345 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 04:07:57 +00:00
Michel Danzer
644aecfc97 R600/SI: Optimize SI_KILL for constant operands
If the SI_KILL operand is constant, we can either clear the exec mask if
the operand is negative, or do nothing otherwise.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202337 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 01:47:09 +00:00
Michel Danzer
a5fbf24716 R600/SI: Allow SI_KILL for geometry shaders
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202336 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 01:47:02 +00:00
Matt Arsenault
3f19b69b01 R600: Remove unnecessary build_vector pattern.
It is already fully handled in AMDGPUISelDAGToDAG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202312 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-26 23:00:58 +00:00
Quentin Colombet
685b0d9315 Lower unsigned vsetcc to psubus in certain cases
The current approach to lower a vsetult is to flip the sign bit of the
operands, swap the operands and then use a (signed) pcmpgt.  psubus (unsigned
saturating subtract) can be used to emulate a vsetult more efficiently:

+    case ISD::SETULT: {
+      // If the comparison is against a constant we can turn this into a
+      // setule.  With psubus, setule does not require a swap.  This is
+      // beneficial because the constant in the register is no longer
+      // destructed as the destination so it can be hoisted out of a loop.

I also enable lowering via psubus in a few other cases where it's clearly
beneficial: setule and setuge if minu/maxu cannot be used.
    
rdar://problem/14338765

Patch by Adam Nemet <anemet@apple.com>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202301 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-26 21:39:12 +00:00
Aaron Ballman
a4e265ae47 Silencing an MSVC signed comparison warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202295 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-26 20:22:20 +00:00
Artyom Skrobov
e708238373 ARMv8 IfConversion must skip narrow instructions that a) define CPSR and b) wouldn't affect CPSR in an IT block
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202257 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-26 11:27:28 +00:00
Daniel Sanders
f6679de299 [mips] Treat -mcpu=generic the same way as an empty CPU string.
Summary:
This should fix the MCJIT unit tests that were broken by r201792 on the MIPS buildbot.
MIPS currently uses the default implementation of sys::getHostCPUName() which
always returns "generic". For now, we will accept "generic" and coerce it to
"mips32" or "mips64" depending on the target architecture like we do for empty
CPU names.

Reviewers: jacksprat, matheusalmeida

Reviewed By: jacksprat

Differential Revision: http://llvm-reviews.chandlerc.com/D2878

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202253 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-26 10:20:15 +00:00
Craig Topper
ecb903c1b5 [x86] Add same itinerary to SYSEXIT64 as SYSEXIT for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202240 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-26 06:50:27 +00:00
Craig Topper
9262808ecd [x86] Remove some unused instruction format classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202234 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-26 06:06:38 +00:00
Craig Topper
df24b19e45 [x86] Simplify disassembler code slightly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202233 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-26 06:01:21 +00:00
Rafael Espindola
356deb5ecd Use DataLayout from the module when easily available.
Eventually DataLayoutPass should go away, but for now that is the only easy
way to get a DataLayout in some APIs. This patch only changes the ones that
have easy access to a Module.

One interesting issue with sometimes using DataLayoutPass and sometimes
fetching it from the Module is that we have to make sure they are equivalent.
We can get most of the way there by always constructing the pass with a Module.
In fact, the pass could be changed to point to an external DataLayout instead
of owning one to make this stricter.

Unfortunately, the C api passes a DataLayout, so it has to be up to the caller
to make sure the pass and the module are in sync.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202204 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-25 23:25:17 +00:00
Tom Stellard
431e9f0310 R600: Don't unconditionally unroll loops with private memory accesses
This causes the size of the scrypt kernel to explode and eats all the
memory on some systems.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202195 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-25 21:36:21 +00:00
Tom Stellard
d8c31046a9 R600/SI: Custom select 64-bit ADD
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202194 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-25 21:36:18 +00:00
Hal Finkel
15ac7dfb90 Account for 128-bit integer operations in PPCCTRLoops
We need to abort the formation of counter-register-based loops where there are
128-bit integer operations that might become function calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202192 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-25 20:51:50 +00:00
Richard Osborne
150f810744 [XCore] Add intrinsic for CLRPT (clear port time) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202172 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-25 17:31:15 +00:00
Richard Osborne
fb2f73acb9 [XCore] Add intrinsic for EDU (event disable unconditional) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202171 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-25 17:31:06 +00:00
Rafael Espindola
57edc9d4ff Make DataLayout a plain object, not a pass.
Instead, have a DataLayoutPass that holds one. This will allow parts of LLVM
don't don't handle passes to also use DataLayout.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202168 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-25 17:30:31 +00:00
Richard Osborne
6dc9f732ce [XCore] Prefer to word align functions.
The behaviour of the XCore's instruction buffer means that the performance
of the same code sequence can differ depending on whether it starts at a 4
byte aligned address or not. Since we don't model the instruction buffer
in the backend we have no way of knowing for sure if it is beneficial to
word align a specific function. However, in the absence of precise
modelling, it is better on balance to word align functions because:

* It makes a fetch-nop while executing the prologue slightly less likely.
* If we don't word align functions then a small perturbation in one
  function can have a dramatic knock on effect. If the size of the function
  changes it might change the alignment and therefore the performance of
  all the functions that happen to follow it in the binary. This butterfly
  effect makes it harder to reason about and measure the performance of
  code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202163 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-25 16:37:15 +00:00
Alp Toker
bf930d5c1f Fix typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202107 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-25 04:21:15 +00:00
Rafael Espindola
ec89b9fb9e Make some DataLayout pointers const.
No functionality change. Just reduces the noise of an upcoming patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202087 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 23:12:18 +00:00
Albrecht Kadlec
0aedb78442 trivial test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202084 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 22:18:38 +00:00
Matt Arsenault
2e4ab2aa8a Fix unused variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202080 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 21:16:50 +00:00
Matt Arsenault
bc247e4afd R600/SI - Add new CI arithmetic instructions.
Does not yet include larger part required
to match v_mad_i64_i32 / v_mad_u64_u32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202077 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 21:01:28 +00:00
Matt Arsenault
3f9f4bc0af R600: Make check clearer.
The check is clearer as southern islands or later,
rather than checking for later than northern islands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202076 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 21:01:23 +00:00
Matt Arsenault
e87a1a9e2c Fix DOT4 missing from getTargetOpcodeName
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202075 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 21:01:21 +00:00
Quentin Colombet
b55c398992 [X86][SchedModel] Add missing scheduling model for SSE related instructions.
The patch defines new or refines existing generic scheduling classes to match
the behavior of the SSE instructions.
It also maps those scheduling classes on the related SSE instructions.

<rdar://problem/15607571>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202065 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 19:33:51 +00:00
Roman Divacky
68e1531d39 Add a dwarf number to the Y register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202057 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 18:41:31 +00:00
Rafael Espindola
ac69459e0f Replace the F_Binary flag with a F_Text one.
After this I will set the default back to F_None. The advantage is that
before this patch forgetting to set F_Binary would corrupt a file on windows.
Forgetting to set F_Text produces one that cannot be read in notepad, which
is a better failure mode :-)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202052 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 18:20:12 +00:00
Christian Pirker
d7e12561a5 Add AArch64 big endian Target (aarch64_be)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202024 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 11:34:50 +00:00
Elena Demikhovsky
58423c8f1a AVX-512: Fixed encoding of VPCMPEQ and VPCMPGT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202015 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 10:08:30 +00:00
Benjamin Kramer
570d544799 SPARC: Implement TRAP lowering. Matches what GCC emits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201994 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-23 21:43:52 +00:00
Saleem Abdulrasool
b4702e215e ARMAsmParser: whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201989 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-23 17:45:36 +00:00
Saleem Abdulrasool
ec1c80576d ARM IAS: support .align without parameters
.align is handled specially on certain targets.  .align without any parameters
on ARM indicates a default alignment (4).  Handle the special case in the target
parser, but fall back to the generic parser for the normal version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201988 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-23 17:45:32 +00:00
Elena Demikhovsky
73f1a5fe45 AVX-512: Fixed encoding of VPTESTMQ
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201980 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-23 14:28:35 +00:00
Saleem Abdulrasool
be66089390 ARM IAS: support .short and .hword
This adds support for the .short and its alias .hword for adding literal values
into the object file.  This is similar to the .word directive, however, rather
than inserting a value of 4 bytes, adds a 2-byte value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201968 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-23 06:22:09 +00:00
Logan Chien
80668d18e8 Move get[S|U]LEB128Size() to LEB128.h.
This commit moves getSLEB128Size() and getULEB128Size() from
MCAsmInfo to LEB128.h and removes some copy-and-paste code.

Besides, this commit also adds some unit tests for the LEB128
functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201937 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-22 14:00:39 +00:00
Juergen Ributzka
94f20bfe6e [Stackmaps] Move the target-independent frame index elimination for stackmaps and patchpoints into target-specific code.
The lowering of the frame index for stackmaps and patchpoints requires some
target-specific magic and should therefore be handled in the target-specific
eliminateFrameIndex method.

This is related to <rdar://problem/16106219>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201904 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-21 23:29:32 +00:00
Kevin Qin
10ecde5c34 [AArch64] Add register constraints to avoid generating STLXR and STXR with unpredictable behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201841 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-21 07:45:48 +00:00
Rafael Espindola
eb6e1d3165 Rename a few more DataLayout variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201833 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-21 01:53:35 +00:00
Benjamin Kramer
3e552a331b Remove unnecessary copy of array_lengthof.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201798 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 17:36:31 +00:00
Oliver Stannard
71f63717a8 AArch64: __va_list.__stack must be 8-byte aligned
The va_start macro for AArch64 must set va_list.__stack to the address
following the last named argument on the stack, rounded up to an alignment
of 8 bytes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201797 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 17:19:26 +00:00
Chad Rosier
fda2dfbca7 [AArch64] Add support for TargetTransformInfo Analysis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201793 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 16:00:08 +00:00
Daniel Sanders
5c86661f15 [mips] Make it impossible to have UnknownABI in CodeGen and Integrated Assembler.
Summary:
This removes the need to coerce UnknownABI to the default ABI (O32 for
MIPS32, N64 for MIPS64 [*]) in both MipsSubtarget and MipsAsmParser.

Clang has been updated to disable both possible default ABI's before enabling
the ABI it intends to use.

[*] N64 being the default for MIPS64 is not actually correct.
    However N32 is not fully implemented/tested yet.

Depends on: D2830

Reviewers: jacksprat, matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D2832
Differential Revision: http://llvm-reviews.chandlerc.com/D2846



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201792 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 14:58:19 +00:00
NAKAMURA Takumi
1e3bb3fc41 [CMake] Move intrinsics_gen to lib/Target out of add_public_tablegen_target.
add_public_tablegen_target is used somewhere.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201787 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 13:42:30 +00:00
Daniel Sanders
7934a2a9f1 [mips] Make mips64 the default CPU for the mips64 architecture
Summary:
This is consistent with the integrated assembler.
All mips64 codegen tests previously passed -mcpu. Removed -mcpu from
blez_bgez.ll and const-mult.ll to cover the default case.

Ideally, the two implementations of selectMipsCPU() will be merged but it's
proven difficult to find a home for the function that doesn't cause link errors.
For now, we'll hoist the common functionality into a function and mark it with
FIXME's.

Reviewers: jacksprat, matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D2830

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201782 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 13:13:33 +00:00
Craig Topper
46aa7fb720 [x86] Switch PAUSE instruction to use XS prefix instead of HasREPPrefix. Remove HasREPPrefix support from disassembler table generator since its now only used by CodeGenOnly instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201767 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 07:59:43 +00:00
Elena Demikhovsky
143df776e2 AVX-512: Fixed compilation issue
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201761 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 07:00:10 +00:00
Elena Demikhovsky
08316a11e4 AVX-512: Assembly parsing of broadcast semantic in AVX-512; imlemented by Nis Zinovy (zinovy.y.nis@intel.com)
Fixed truncate i32 to i1; a test will be provided in the next commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201757 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 06:34:39 +00:00
Reed Kotler
fccbee8faf Make one statement easier to understand from post commmit feedback from a
review of the previous patch that introduced this week.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201723 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 22:11:45 +00:00
Roman Divacky
3bd3f426a5 Expand 64bit {SHL,SHR,SRA}_PARTS on sparcv9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201718 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 21:35:39 +00:00
Rafael Espindola
b4aaffffd3 move getNameWithPrefix and getSymbol to TargetMachine.
TargetLoweringBase is implemented in CodeGen, so before this patch we had
a dependency fom Target to CodeGen. This would show up as a link failure of
llvm-stress when building with -DBUILD_SHARED_LIBS=ON.

This fixes pr18900.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201711 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 20:30:41 +00:00
Rafael Espindola
737c9f6005 Add back r201608, r201622, r201624 and r201625
r201608 made llvm corretly handle private globals with MachO. r201622 fixed
a bug in it and r201624 and r201625 were changes for using private linkage,
assuming that llvm would do the right thing.

They all got reverted because r201608 introduced a crash in LTO. This patch
includes a fix for that. The issue was that TargetLoweringObjectFile now has
to be initialized before we can mangle names of private globals. This is
trivially true during the normal codegen pipeline (the asm printer does it),
but LTO has to do it manually.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201700 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 17:23:20 +00:00
Christian Pirker
eb5fe7002a Test commit - remove the new line to lib/Target/AArch64/AArch64TargetMachine.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201698 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 16:58:28 +00:00
Daniel Sanders
ffac49bd7f [mips] In the integrated assembler, select the default feature bits by changing the CPU value.
This is consistent with the way CodeGen acheives this. However, CodeGen
always selects mips32 (even when the architecture is mips64).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201694 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 16:13:26 +00:00
Christian Pirker
f47b32ed76 Test commit - added a new line to lib/Target/AArch64/AArch64TargetMachine.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201692 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 16:07:32 +00:00
Daniel Sanders
9a8ab56fac [mips] Use llvm::Triple in ParseMipsTriple() instead of manually parsing it
No functional change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201689 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 15:55:21 +00:00
Daniel Sanders
f51321702b [mips] Remove unused NotN64 predicate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201682 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 15:16:47 +00:00
Cameron McInally
35f15e54a9 Fix AVX512 vector sqrt assembly strings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201681 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 15:16:09 +00:00
Daniel Jasper
9a92586114 Revert r201622 and r201608.
This causes the LLVMgold plugin to segfault. More information on the
replies to r201608.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201669 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 12:26:01 +00:00
Tim Northover
44697f3fc1 X86 CodeGenPrep: sink shufflevectors before shifts
On x86, shifting a vector by a scalar is significantly cheaper than shifting a
vector by another fully general vector. Unfortunately, because SelectionDAG
operates on just one basic block at a time, the shufflevector instruction that
reveals whether the right-hand side of a shift *is* really a scalar is often
not visible to CodeGen when it's needed.

This adds another handler to CodeGenPrepare, to sink any useful shufflevector
instructions down to the basic block where they're used, predicated on a target
hook (since on other architectures, doing so will often just introduce extra
real work).

rdar://problem/16063505

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201655 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 10:02:43 +00:00
Craig Topper
fa0cf99585 Remove special FP opcode maps and instead add enough MRM_XX formats to handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201649 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 08:25:02 +00:00
Craig Topper
52fb0a59d0 Reduce size of map field in X86 TSFlags since it now requires less bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201646 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 07:29:07 +00:00
Craig Topper
75116bc27e Put some of the X86 formats in a more logical order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201645 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 06:59:13 +00:00
Craig Topper
82a644adf2 Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201641 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 05:34:21 +00:00
Rafael Espindola
6880f0e19f Fix PR18743.
The IR
@foo = private constant i32 42

is valid, but before this patch we would produce an invalid MachO from it. It
was invalid because it would use an L label in a section where the liker needs
the labels in order to atomize it.

One way of fixing it would be to just reject this IR in the backend, but that
would not be very front end friendly.

What this patch does is use an 'l' prefix in sections that we know the linker
requires symbols for atomizing them. This allows frontends to just use
private and not worry about which sections they go to or how the linker handles
them.

One small issue with this strategy is that now a symbol name depends on the
section, which is not available before codegen. This is not a problem in
practice. The reason is that it only happens with private linkage, which will
be ignored by the non codegen users (llvm-nm and llvm-ar).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201608 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-18 22:24:57 +00:00
Rafael Espindola
1836fe5651 Rename a DebugLoc variable to DbgLoc and a DataLayout to DL.
This is quiet a bit less confusing now that TargetData was renamed DataLayout.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201606 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-18 22:05:46 +00:00
Ana Pazos
a3de371b53 [AArch64] Expanded sin, cos, pow with FP vector types inputs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201601 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-18 20:31:05 +00:00
Robert Lytton
ade82a4157 XCore target: Handle common linkage
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201563 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-18 11:21:59 +00:00
Robert Lytton
b489828264 XCore target: addMemOperand as necessary
BuildMI instructions were not including MachineMemOperand information.
This was discovered by 'SingleSource/Benchmarks/Stanford/Oscar' failing
due to a FrameIndex load incorrectly being hoisted by postra-machine-licm.
No other tests have been found to fail.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201562 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-18 11:21:53 +00:00
Robert Lytton
9409825b57 XCore target: Fix llvm.eh.return and EH info register handling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201561 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-18 11:21:48 +00:00
Tim Northover
4bcb985295 GlobalMerge: move "-global-merge" option to the pass itself.
It's rather odd to have the flag enabling and disabling this pass only affect a
single target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201559 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-18 11:17:29 +00:00
Tim Northover
d729dfc96e X86: use vpsllvd (& friends) for 16-bit shifts on Haswell
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201558 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-18 11:15:32 +00:00
Craig Topper
ce3db3cdb2 Add PS prefix to some classes I missed in r201538.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201551 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-18 08:24:22 +00:00
Craig Topper
17e2af6928 Add a bunch of OpSize32 tags to 64-bit mode only instructions to match their 32-bit mode counterparts for cases where there is also a OpSize16 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201550 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-18 08:18:29 +00:00
Elena Demikhovsky
2e58f4605d AVX-512: Fixed size of mask registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201546 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-18 07:52:26 +00:00
Jiangning Liu
47f6b173f5 Fix a typo about lowering AArch64 va_copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201541 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-18 02:37:42 +00:00
Craig Topper
7d2bb38164 Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201538 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-18 00:21:49 +00:00
Kevin Enderby
4959a2d878 Fix the arm assembler so that this malformed instruction:
ldrd r6, r7 [r2, #15]
simply gives an error and does not triggers an assertion.

As Jim points out, the diagnostic is really strange here,
but fixing that would be more complicated. The missing
comma results in the parser expecting a construct like r2[2],
which is the vector index thing the error message is talking
about. That's not what the user intended, though, and there's
nothing else in the instruction that looks at all like a vector.
Yet more fallout from not having a real parser here and trying
to do context-free generic matching for addressing modes.

rdar://15097243


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201531 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-17 21:45:27 +00:00
Craig Topper
3457506fb9 Fix diassembler handling of rex.b when mod=00/01/10 and bbb=101. Mod=00 should ignore the base register entirely. Mod=01/10 should treat this as R13 plus displacment. Fixes PR18860.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201507 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-17 10:03:43 +00:00
Elena Demikhovsky
e139a1e0e4 AVX-512: implemented zext fron i1 to i16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201502 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-17 07:29:33 +00:00
Mark Seaborn
09d1d540c8 Use 16 byte stack alignment for NaCl on ARM
NaCl's ARM ABI uses 16 byte stack alignment, so set that in
ARMSubtarget.cpp.

Using 16 byte alignment exposes an issue in code generation in which a
varargs function leaves a 4 byte gap between the values of r1-r3 saved
to the stack and the following arguments that were passed on the
stack.  (Previously, this code only needed to support 4 byte and 8
byte alignment.)

With this issue, llc generated:

varargs_func:
        sub     sp, sp, #16
        push    {lr}
        sub     sp, sp, #12
        add     r0, sp, #16   // Should be 20
        stm     r0, {r1, r2, r3}
        ldr     r0, .LCPI0_0  // Address of va_list
        add     r1, sp, #16
        str     r1, [r0]
        bl      external_func

Fix the bug by checking for "Align > 4".  Also simplify the code by
using OffsetToAlignment(), and update comments.

Differential Revision: http://llvm-reviews.chandlerc.com/D2677

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201497 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-16 18:59:48 +00:00
Rafael Espindola
56d34914b2 Remove dead code, we already require cmake 2.8.8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201495 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-16 14:36:26 +00:00
Elena Demikhovsky
f280c65b32 AVX-512: simpyfied BUILD_VECTOR for masks; fixed cmp/test sequence
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201487 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-16 11:34:23 +00:00
Saleem Abdulrasool
1edea19210 ARM IAS: (partially) support .arch_extension directive
This adds a partial implementation of the .arch_extension directive to the
integrated ARM assembler.  There are a number of limitations to this
implementation arising from the target backend support rather than the
implementation itself.  Namely, iWMMXT (v1 and v2), Maverick, and XScale support
is not present in the ARM backend.  Currently, there is no check for A-class
only (needed for virt), and no ARMv6k detection (needed for os and sec).  The
remainder of the extensions are fully supported.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201471 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-16 00:16:41 +00:00
Craig Topper
0877c6575a Add opcode extension forms of MOV8ri/MOV16ri/MOV32ri.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201463 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-15 07:29:18 +00:00
Reed Kotler
fba2a769a1 This patch has two main functions:
1) Fix a specific bug when certain conversion functions are called in a program compiled as mips16 with hard float and
the program is linked as c++. There are two libraries that are reversed in the link order with gcc/g++ and clang/clang++ for
mips16 in this case and the proper stubs will then not be called. These stubs are normally handled in the Mips16HardFloat pass
but in this case we don't know at that time that we need to generate the stubs. This must all be handled later in code generation
and we have moved this functionality to MipsAsmPrinter. When linked as C (gcc or clang) the proper stubs are linked in from libc.

2) Set up the infrastructure to handle 90% of what is in the Mips16HardFloat pass in this new area of MipsAsmPrinter. This is a more
logical place to handle this and we have known for some time that we needed to move the code later and not implement it using
inline asm as we do now but it was not clear exactly where to do this and what mechanism should be used. Now it's clear to us
how to do this and this patch contains the infrastructure to move most of this to MipsAsmPrinter but the actual moving will be done
in a follow on patch. The same infrastructure is used to fix this current bug as described in #1. This change was requested by the list
during the original putback of the Mips16HardFloat pass but was not practical for us do at that time.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201426 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-14 19:16:39 +00:00
Artyom Skrobov
e228078ca6 Generate the DWARF stack frame decode operations in the function prologue for ARM/Thumb functions.
Patch by Keith Walker!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201423 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-14 17:19:07 +00:00
Kevin Qin
54136cad2e [AArch64 NEON] Fix a bug to avoid using floating type as condition type in lowering SELECT_CC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201395 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-14 09:41:15 +00:00
Jiangning Liu
255181f2b8 Enable AArch64 NEON by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201385 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-14 04:38:09 +00:00
Hao Liu
9c4127a6a5 [AArch64]Fix the assertion failure caused by "v1i1 SETCC" DAG node.
As v1i1 is illegal, the type legalizer tries to scalarize such node. But if the type operands of SETCC is legal, the scalarization algorithm will cause an assertion failure.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201381 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-14 02:21:56 +00:00
Juergen Ributzka
5cb9925acd [X86] Don't mark movabsq as cheap-as-move - it isn't that cheap.
A simple register copy on X86 is just 3 bytes, whereas movabsq is a 10 byte
instruction. Marking movabsq as not beeing cheap will allow LICM to move it
out of the loop and it also prevents unnecessary rematerializations if the
value is needed in more than one register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201377 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-14 00:51:13 +00:00
Tom Stellard
0f2e653317 R600/SI: Expand all v8[if]32 operations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201371 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-13 23:34:15 +00:00
Tom Stellard
9757ba1206 R600/SI: Add a pattern for i32 anyext
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201370 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-13 23:34:13 +00:00
Tom Stellard
130f271259 R600/SI: Completely Disable TypeRewriter on compute
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201369 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-13 23:34:12 +00:00
Tom Stellard
1a52c2b25a R600/SI: Split global vector loads with more than 4 elements
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201368 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-13 23:34:10 +00:00
Daniel Sanders
38c6b58eec Re-commit: Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove hasRawTextSupport() call
Summary:
AsmPrinter::EmitInlineAsm() will no longer use the EmitRawText() call for
targets with mature MC support. Such targets will always parse the inline
assembly (even when emitting assembly). Targets without mature MC support
continue to use EmitRawText() for assembly output.

The hasRawTextSupport() check in AsmPrinter::EmitInlineAsm() has been replaced
with MCAsmInfo::UseIntegratedAs which when true, causes the integrated assembler
to parse inline assembly (even when emitting assembly output). UseIntegratedAs
is set to true for targets that consider any failure to parse valid assembly
to be a bug. Target specific subclasses generally enable the integrated
assembler in their constructor. The default value can be overridden with
-no-integrated-as.

All tests that rely on inline assembly supporting invalid assembly (for example,
those that use mnemonics such as 'foo' or 'hello world') have been updated to
disable the integrated assembler.

Changes since review (and last commit attempt):
- Fixed test failures that were missed due to configuration of local build.
  (fixes crash.ll and a couple others).
- Fixed tests that happened to pass because the local build was on X86
  (should fix 2007-12-17-InvokeAsm.ll)
- mature-mc-support.ll's should no longer require all targets to be compiled.
  (should fix ARM and PPC buildbots)
- Object output (-filetype=obj and similar) now forces the integrated assembler
  to be enabled regardless of default setting or -no-integrated-as.
  (should fix SystemZ buildbots)

Reviewers: rafael

Reviewed By: rafael

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D2686



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201333 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-13 14:44:26 +00:00
Tim Northover
a7181f21fb ARM: remove floating-point patterns for @llvm.arm.neon.vabs
The front-end is now generating the generic @llvm.fabs for this
operation now, so the extra patterns are no longer needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201314 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-13 10:44:30 +00:00
Oliver Stannard
b8c81b50f7 Add Cortex-A53 and Cortex-A57 cores to the AArch64 backend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201305 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-13 09:46:11 +00:00
Hao Liu
7a6f5c77c4 [AArch64]Fix the problems that can't select mul/add/sub of v1i8/v1i16/v1i32 types.
As this problems are similar to shl/sra/srl, also add patterns for shift nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201298 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-13 05:42:33 +00:00
Hao Liu
4f2256187c [AArch64]Add support for spilling FPR8/FPR16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201287 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-13 02:36:58 +00:00
Andrea Di Biagio
029a76b0a2 [Vectorizer] Add a new 'OperandValueKind' in TargetTransformInfo called
'OK_NonUniformConstValue' to identify operands which are constants but
not constant splats.

The cost model now allows returning 'OK_NonUniformConstValue'
for non splat operands that are instances of ConstantVector or
ConstantDataVector.

With this change, targets are now able to compute different costs
for instructions with non-uniform constant operands.
For example, On X86 the cost of a vector shift may vary depending on whether
the second operand is a uniform or non-uniform constant.

This patch applies the following changes:
 - The cost model computation now takes into account non-uniform constants;
 - The cost of vector shift instructions has been improved in
   X86TargetTransformInfo analysis pass;
 - BBVectorize, SLPVectorizer and LoopVectorize now know how to distinguish
   between non-uniform and uniform constant operands.

Added a new test to verify that the output of opt
'-cost-model -analyze' is valid in the following configurations: SSE2,
SSE4.1, AVX, AVX2.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201272 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-12 23:43:47 +00:00
Andrea Di Biagio
8887371782 [X86] Teach the backend how to lower vector shift left into multiply rather than scalarizing it.
Instead of expanding a packed shift into a sequence of scalar shifts,
the backend now tries (when possible) to convert the vector shift into a
vector multiply.

Before this change, a shift of a MVT::v8i16 vector by a
build_vector of constants was always scalarized into a long sequence of "vector
extracts + scalar shifts + vector insert".
With this change, if there is SSE2 support, we emit a single vector multiply.

This change also affects SSE4.1, AVX, AVX2 shifts:
 - A shift of a MVT::v4i32 vector by a build_vector of non uniform constants
is now lowered when possible into a single SSE4.1 vector multiply.
 - Packed v16i16 shift left by constant build_vector are now expanded when
possible into a single AVX2 vpmullw.
This change also improves the lowering of AVX512f vector shifts.

Added test CodeGen/X86/vec_shift6.ll with some code examples that are affected
by this change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201271 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-12 23:42:28 +00:00
Daniel Sanders
7580df334e Revert r201237+r201238: Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove hasRawTextSupport() call
It introduced multiple test failures in the buildbots.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201241 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-12 15:39:20 +00:00
Daniel Sanders
57edb9588b Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove hasRawTextSupport() call
Summary:
AsmPrinter::EmitInlineAsm() will no longer use the EmitRawText() call for targets with mature MC support. Such targets will always parse the inline assembly (even when emitting assembly). Targets without mature MC support continue to use EmitRawText() for assembly output.

The hasRawTextSupport() check in AsmPrinter::EmitInlineAsm() has been replaced with MCAsmInfo::UseIntegratedAs which when true, causes the integrated assembler to parse inline assembly (even when emitting assembly output). UseIntegratedAs is set to true for targets that consider any failure to parse valid assembly to be a bug. Target specific subclasses generally enable the integrated assembler in their constructor. The default value can be overridden with -no-integrated-as.

All tests that rely on inline assembly supporting invalid assembly (for example, those that use mnemonics such as 'foo' or 'hello world') have been updated to disable the integrated assembler.

Reviewers: rafael

Reviewed By: rafael

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D2686

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201237 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-12 14:44:54 +00:00
Benjamin Kramer
eee40f92a9 R600: Always implement both versions of isTruncateFree and add a sanity check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201222 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-12 10:17:54 +00:00
Craig Topper
56d749a86b Mark XACQUIRE_PREFIX/XRELEASE_PREFIX as isAsmParserOnly so they'll disappear from the disassembler table build without custom filtering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201215 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-12 08:02:29 +00:00
Evan Cheng
9f5baa3c7e Tweak ARM fastcc by adopting these two AAPCS rules:
* CPRCs may be allocated to co-processor registers or the stack – they may never be allocated to core registers
* When a CPRC is allocated to the stack, all other VFP registers should be marked as unavailable

The difference is only noticeable in rare cases where there are a large number of floating point arguments (e.g.
7 doubles + additional float, double arguments). Although it's probably still better to avoid vmov as it can cause
stalls in some older ARM cores. The other, more subtle benefit, is to minimize difference between the various
calling conventions.

rdar://16039676


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201193 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-11 23:49:31 +00:00
Matt Arsenault
69bc4ddf10 R600/SI: Fix assertion on infinite loops.
This isn't the most useful case to fix in the real world,
but bugpoint runs into this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201177 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-11 21:12:38 +00:00
Jim Grosbach
0c2ff8cbfd ARM: Thumb2 LDR(literal) can target SP.
Fix a slightly overzealous destination register restriction for the
'without .w' alias. Add some explicit testcases.

rdar://16033140

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201173 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-11 20:48:39 +00:00
Robert Lytton
d3abd0b648 XCore target: fix const section handling
Xcore target ABI requires const data that is externally visible
to be handled differently if it has C-language linkage rather than
C++ language linkage.

Clang now emits ".cp.rodata" section information.

All other externally visible constant data will be placed in the DP section.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201144 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-11 10:36:26 +00:00
Robert Lytton
04a573a41f XCore target: Lower ATOMIC_LOAD & ATOMIC_STORE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201143 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-11 10:36:18 +00:00
Elena Demikhovsky
e9d5f6e387 AVX: fixed a bug in LowerVECTOR_SHUFFLE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201140 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-11 10:21:53 +00:00
Elena Demikhovsky
e4092e9895 AVX-512: Optimized BUILD_VECTOR pattern;
fixed encoding of VEXTRACTPS instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201134 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-11 07:25:59 +00:00
Matt Arsenault
700bba297b R600: Implement isTruncateFree
Truncation is just accessing a subregister for any multiple of
the register size, so it's free.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201107 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 19:57:42 +00:00
Tom Stellard
42faffddb9 R600/SI: Initialize M0 and emit S_WQM_B64 whenever DS instructions are used
DS instructions that access local memory can only uses addresses that
are less than or equal to the value of M0.  When M0 is uninitialized,
then we experience undefined behavior.

This patch also changes the behavior to emit S_WQM_B64 on pixel shaders
no matter what kind of DS instruction is used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201097 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 16:58:30 +00:00