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1827 Commits

Author SHA1 Message Date
Johnny Chen
76b39e88e4 Explicitly specify 0b00, i.e, zero rotation, as the rotate filed (Inst{11-10}) 
for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85271 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 18:44:24 +00:00
Johnny Chen
6a3b5eec89 Test commit. Added '.' to the comment line. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85255 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 17:25:15 +00:00
Rafael Espindola
f87611272b Correctly align double arguments in the stack. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85235 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 14:09:44 +00:00
Evan Cheng
dd22a45acc Now VFP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85186 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 00:20:49 +00:00
Evan Cheng
699bebac4f Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85184 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-27 00:08:59 +00:00
Evan Cheng
162e30921d Change ARM asm strings to separate opcode from operands with a tab instead of a space. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85178 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 23:45:59 +00:00
Bob Wilson
dda9583e51 Try to get ahead of Johnny Chen and pro-actively add some more ARM encoding 
bits.  Johnny, please review -- I do not have a good track record of getting
these right.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85173 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 22:59:12 +00:00
Bob Wilson
d9ecd3108f Fix ARM encoding typo: Opcod3 is not passed to ASuI parent class. 
Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85169 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 22:42:13 +00:00
Bob Wilson
7e053bb33c Add more ARM instruction encodings for 's' bit set and "rs" register encoding 
bits.  Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85167 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 22:34:44 +00:00
David Goodwin
2e7be612d5 Break anti-dependence breaking out into its own class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85127 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-26 16:59:04 +00:00
Jim Grosbach
dd5694203b of -> or 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85065 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 19:14:48 +00:00
Jim Grosbach
f639e9f9e6 80-column cleanup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85064 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 18:55:46 +00:00
Evan Cheng
4f54c1293a Add ARM getMatchingSuperRegClass to handle S / D / Q cross regclass coalescing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85049 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 07:53:28 +00:00
Evan Cheng
ed3ad212ec Don't forget subreg indices when folding load / store. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85048 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 07:52:27 +00:00
Nick Lewycky
f5a86f45e7 Remove includes of Support/Compiler.h that are no longer needed after the 
VISIBILITY_HIDDEN removal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85043 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 06:57:41 +00:00
Nick Lewycky
6726b6d75a Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces. 
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85042 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 06:33:48 +00:00
Evan Cheng
5a850beb2e 80 col violation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84986 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-24 02:07:42 +00:00
Jim Grosbach
2f1abe2dae Restrict Thumb1 register allocation to low registers, even for instructions that 
can access the hi regs. Our prologue and epilogue code doesn't know how to
properly handle save/restore of the hi regs, so things go badly when we alloc
them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84982 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-24 00:19:24 +00:00
Jim Grosbach
7388037dd1 FIXME no longer applies. R12 and R3 are available for allocation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84977 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-23 23:07:42 +00:00
David Goodwin
4c3715c2e5 Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84911 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 23:19:17 +00:00
Bob Wilson
bac6ed4ba4 Revert 84843. Evan, this was breaking some of the if-conversion tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84868 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 16:52:21 +00:00
Evan Cheng
87689d3b70 Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84843 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 06:48:32 +00:00
Evan Cheng
faf93aa233 Load / store multiple was missing opportunites when the load / store bundles are at the end of the bb. Test case is already in, the bug is exposed by subsequent commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84842 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 06:47:35 +00:00
Evan Cheng
62d1723a9c Trim more includes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84832 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 05:11:00 +00:00
Evan Cheng
268c79350e Trim include. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84831 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 05:08:49 +00:00
Evan Cheng
8000c6c535 Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84813 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 00:40:00 +00:00
Jim Grosbach
41fff8c19a Missing piece of the ARM frame index post-scavenging conditionalization 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84798 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 23:40:56 +00:00
Jim Grosbach
1d6827bbe9 Conditionalize ARM/T2 frame index post-scavenging while working out fixes 
for a few bugs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84791 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 22:59:24 +00:00
Bob Wilson
20d108140e Most of the NEON shuffle instructions do not support 64-bit element types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84785 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 21:36:27 +00:00
Jim Grosbach
65b7f3af76 Improve handling of immediates by splitting 32-bit immediates into two 16-bit 
immediate operands when they will fit into the using instruction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84778 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 20:44:34 +00:00
Bob Wilson
b27b51aaa6 Fix NEON VST2LN instruction encoding. 
Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84767 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 17:54:01 +00:00
Bob Wilson
407d57489f Revert 84732. It was the wrong fix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84766 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 17:52:34 +00:00
Evan Cheng
2095659a85 Match more patterns to movt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84751 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 08:15:52 +00:00
Chris Lattner
1ce75ef5ef tidy 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84738 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 04:10:24 +00:00
Bob Wilson
b3c8359360 Fix some more NEON instruction encoding problems. 
Thanks to Johnny Chen for discovering the problem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84732 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 02:27:20 +00:00
Bob Wilson
507df402b0 Leave some NEON instruction encoding bits unspecified instead of setting 
a default value of zero.  This is important for decoding the instructions.
Patch by Johnny Chen, with some changes from me, too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84730 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-21 02:15:46 +00:00
Daniel Dunbar
a7cc65283a Fix -Asserts warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84687 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 22:10:05 +00:00
Jim Grosbach
3229b0bcf1 Disable by default while debugging 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84669 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 20:31:31 +00:00
Jim Grosbach
18ed9c9a2b add cmd line opt to disable frame index reuse for ARM and T2. debug aid. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84664 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 20:19:50 +00:00
Benjamin Kramer
174101e13a Random #include pruning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84632 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 11:44:38 +00:00
Chris Lattner
235e2f6a68 implement some more easy hooks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84614 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 06:22:33 +00:00
Chris Lattner
bf16faa16a Implement some hooks, make printOperand abort if unknown modifiers are 
present.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84613 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 06:15:28 +00:00
Chris Lattner
c6b8a99207 t2MOVi32imm is currently always lowered by the Thumb2ITBlockPass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84611 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 05:58:02 +00:00
Daniel Dunbar
2685a29a8d Wire up the ARM MCInst printer, for llvm-mc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84600 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 05:15:36 +00:00
Jim Grosbach
8fa4efeabf Now that all ARM subtargets use frame index scavenging, the Thumb1 requires* 
functions are not needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84587 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 01:32:47 +00:00
Jim Grosbach
7e831db1d4 Enable post-pass frame index register scavenging for ARM and Thumb2 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84585 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 01:26:58 +00:00
Chris Lattner
161dcbf799 lower ARM::MOVi32imm properly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84583 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 01:11:37 +00:00
Chris Lattner
292df8eb1f add support for external symbols. The mc instprinter can now handle 
reasonable code like Codegen/ARM/2009-02-27-SpillerBug.ll, producing 
identical output except for superior formatting of constant pool entries.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84582 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 00:56:16 +00:00
Chris Lattner
96bc2173bb get fancy: support basic block operands. Yay for jumps. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84579 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 00:52:47 +00:00
Chris Lattner
233917c072 add supprort for the 'sbit' operand, MOVi apparently has one. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84577 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 00:46:11 +00:00
Chris Lattner
413ae25fb5 add support for instruction predicates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84575 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 00:42:49 +00:00
Chris Lattner
017d9478d5 implement printSORegOperand, add lowering for the nasty and despicable MOVi2pieces :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84573 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 00:40:56 +00:00
Jim Grosbach
1fc1dc0682 Refs: A8-598. 
Leave Inst{11-8}, which represents the starting byte index of the extracted
result in the concatenation of the operands and is left unspecified.

Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84572 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 00:38:19 +00:00
Jim Grosbach
780d207d1c Add missing encoding bits to NLdSt class of instructions. 
Patch by Johnny Chen.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84570 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-20 00:19:08 +00:00
Chris Lattner
306d14f9aa handle addmode4 modifiers, fix a fixme in printRegisterList 
by ignoring all implicit regs when lowering.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84566 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 23:31:43 +00:00
Jim Grosbach
6009751244 Enable allocation of R3 in Thumb1 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84563 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 22:57:03 +00:00
Chris Lattner
5a207897bc use EmitLabel instead of text emission 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84562 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 22:51:16 +00:00
Chris Lattner
7c5b021793 add a twine version of MCContext::GetOrCreateSymbol. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84561 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 22:49:00 +00:00
Chris Lattner
a70e644820 lower the ARM::CONSTPOOL_ENTRY pseudo op, giving us constant pool entries 
like:

@ BB#1:
	.align	2
LCPI1_0:
	.long	L_.str-(LPC0+8)

Note that proper indentation of the label :)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84558 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 22:33:05 +00:00
Jim Grosbach
d482f55af1 Adjust the scavenge register spilling to allow the target to choose an 
appropriate restore location for the spill as well as perform the actual
save and restore.

The Thumb1 target uses this to make sure R12 is not clobbered while a spilled
scavenger register is live there.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84554 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 22:27:30 +00:00
Chris Lattner
4d15222341 add MCInstLower support for lowering ARM::PICADD, a pseudo op for pic stuffola. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84553 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 22:23:04 +00:00
Chris Lattner
e306d8d6cc add register list and hacked up addrmode #4 support, we now get this: 
_main:
	stmsp! sp!, {r7, lr}
	mov r7, sp
	sub sp, sp, #4
	mov r0, #0
	str r0, [sp]
	ldr r0, LCPI1_0
	bl _printf
	ldr r0, [sp]
	mov sp, r7
	ldmsp! sp!, {r7, pc}

Note the unhappy ldm/stm because of modifiers being ignored.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84546 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 22:09:23 +00:00
Chris Lattner
084f87d445 add addrmode2 support, getting us up to: 
_main:
	stm , 
	mov r7, sp
	sub sp, sp, #4
	mov r0, #0
	str r0, [sp]
	ldr r0, LCPI1_0
	bl _printf
	ldr r0, [sp]
	mov sp, r7
	ldm , 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84543 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 21:57:05 +00:00
Chris Lattner
6f99776f6c add jump tables, constant pools and some trivial global 
lowering stuff.  We can now compile hello world to:

_main:
	stm , 
	mov r7, sp
	sub sp, sp, #4
	mov r0, #0
	str r0, 
	ldr r0, 
	bl _printf
	ldr r0, 
	mov sp, r7
	ldm , 

Almost looks like arm code :)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84542 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 21:53:00 +00:00
Chris Lattner
8514e21deb reduce #includes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84536 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 21:23:15 +00:00
Chris Lattner
61d35c273e add printing support for SOImm operands, getting us to: 
_main:
	stm , 
	mov r7, sp
	sub sp, sp, #4
	mov r0, #0
	str r0, 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84535 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 21:21:39 +00:00
Chris Lattner
8bc86cba60 wire up some basic printOperand goodness, giving us stuff like this before 
we abort:

_main:
	stm , 
	mov r7, sp
	sub sp, sp, 
	mov r0, 
	str r0, 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84532 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 20:59:55 +00:00
Chris Lattner
9cf0eb5e58 add the files that go with the previous rev 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84531 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 20:21:05 +00:00
Chris Lattner
97f0693744 wire up skeletal support for having llc print instructions 
through mcinst lowering -> mcinstprinter, when llc is passed
the -enable-arm-mcinst-printer flag.  Currently this
is very "aborty".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84530 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 20:20:46 +00:00
Chris Lattner
6a71afaec1 wire up ARM's printMCInst method. Now llvm-mc should be able to produce 
"something" when printing MCInsts, it will just be missing all the 
operand info.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84528 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 19:59:05 +00:00
Chris Lattner
fd60382e75 stub out a minimal ARMInstPrinter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84527 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 19:56:26 +00:00
Chris Lattner
b8f64a72d8 simplify code, reducing string thrashing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84521 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 18:49:14 +00:00
Chris Lattner
e4d9ea83c0 switch hidden gv stubs to use MachineModuleInfoMachO instead of a custom map. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84520 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 18:44:38 +00:00
Chris Lattner
b0f294c14b use MachineModuleInfoMachO for non-lazy gv stubs instead of a private map. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84519 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 18:38:33 +00:00
Chris Lattner
ee8b32981e remove dead map 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84513 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 18:11:25 +00:00
Chris Lattner
a10343f039 don't bother trying to avoid emitting redundant constant pool alignment directives. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84512 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 18:08:02 +00:00
Chris Lattner
74cd3b7ceb emit .subsections_via_symbols through MCStreamer instead of textually. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84509 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 18:03:08 +00:00
Chris Lattner
4a071d667d cleanup doFinalization -> EmitEndOfAsmFile. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84508 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-19 17:59:19 +00:00
Evan Cheng
ff89dcb06f -Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed 
stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot 
move above a store of spill slot #2. 
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84424 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-18 18:16:27 +00:00
Evan Cheng
491f54f1fd Distinquish stack slots from other stack objects. They (and fixed objects) get FixedStack PseudoSourceValues. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84326 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-17 09:20:14 +00:00
Evan Cheng
6553155172 Revert 84315 for now. Re-thinking the patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84321 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-17 07:53:04 +00:00
Evan Cheng
bf125583f8 Rename getFixedStack to getStackObject. The stack objects represented are not 
necessarily fixed. Only those will negative frame indices are "fixed."


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84315 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-17 06:22:26 +00:00
Evan Cheng
fa16354e03 Change createPostRAScheduler so it can be turned off at llc -O1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84273 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-16 21:06:15 +00:00
Evan Cheng
b46aea1032 I am no spelling bee. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84250 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-16 06:18:09 +00:00
Evan Cheng
d3dd50fec0 Enable post-alloc scheduling for all ARM variants except for Thumb1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84249 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-16 06:11:08 +00:00
Evan Cheng
fee0c1074c Add comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84246 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-16 05:33:58 +00:00
Bob Wilson
1dd4348408 Fix more NEON instruction encodings. 
Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84243 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-16 03:58:44 +00:00
Bob Wilson
934f98b536 Revert svn r80498 and replace it with a different solution. The only problem 
I can see with the original code was that I forgot that this runs after
type legalization and hence the result type will always be i32. (Custom
legalization of EXTRACT_VECTOR_ELT is only enabled for vector types with
8- and 16-bit elements.)

Regarding the FIXME comment: any information about sign and zero-extension
should be captured by separate extension operations.  The DAG combiner should
handle those to produce either VGETLANEu or VGETLANEs, and that seems to be
working now.  If there are cases that we're missing, let me know.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84218 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 23:12:05 +00:00
Sandeep Patel
452b54a8ae Branches must be the last instruction in a Thumb2 IT block. Approved by Evan Cheng. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84212 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 22:25:32 +00:00
Bob Wilson
6f122625dd Fix encoding bits for N3VLInt3_QHS multiclass with 8-bit elements. 
Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84206 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 21:57:47 +00:00
Kevin Enderby
e2a98dd2a4 Fix ARM memory operand parsing of post indexing with just a base register, that 
is just "[Rn]" and no tailing comma with an offset, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84205 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 21:42:45 +00:00
Bob Wilson
b923953733 Fix a potential performance problem in placing ARM constant pools. 
In the case where there are no good places to put constants and we fall back
upon inserting unconditional branches to make new blocks, allow all constant
pool references in range of those blocks to put constants there, even if that
means resetting the "high water marks" for those references.  This will still
terminate because you can't keep splitting blocks forever, and in the bad
cases where we have to split blocks, it is important to avoid splitting more
than necessary.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84202 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 20:49:47 +00:00
Kevin Enderby
515d509360 More bits of the ARM target assembler for llvm-mc, code added to parse labels 
as expressions, code for parsing a few arm specific directives (still needs
the MCStreamer calls for these).  Some clean up of the operand parsing code
and adding some comments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84201 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 20:48:48 +00:00
Bob Wilson
549dda9d82 Be smarter about reusing constant pool entries. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84173 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 05:52:29 +00:00
Bob Wilson
36fa5321ba Fix another problem with ARM constant pools. Radar 7303551. 
When ARMConstantIslandPass cannot find any good locations (i.e., "water") to
place constants, it falls back to inserting unconditional branches to make a
place to put them.  My recent change exposed a problem in this area.  We may
sometimes append to the same block more than one unconditional branch.  The
symptoms of this are that the generated assembly has a branch to an undefined
label and running llc with -debug will cause a seg fault.

This happens more easily since my change to prevent CPEs from moving from
lower to higher addresses as the algorithm iterates, but it could have
happened before.  The end of the block may be in range for various constant
pool references, but the insertion point for new CPEs is not right at the end
of the block -- it is at the end of the CPEs that have already been placed
at the end of the block.  The insertion point could be out of range.  When
that happens, the fallback code will always append another unconditional
branch if the end of the block is in range.

The fix is to only append an unconditional branch if the block does not
already end with one.  I also removed a check to see if the constant pool load
instruction is at the end of the block, since that is redundant with
checking if the end of the block is in-range.

There is more to be done here, but I think this fixes the immediate problem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84172 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-15 05:10:36 +00:00
Bob Wilson
b3642dccee Fix instruction encoding bits for NEON VPADAL. 
Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84146 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-14 21:43:17 +00:00
Bob Wilson
681a2ad403 Remove unused variables to fix build warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84144 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-14 21:40:45 +00:00
Jim Grosbach
b9d319b585 Inst{11-8} for vshl should be 0b0101, not 0b1111. 
Refs: A7-17 & A8-750.

Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84131 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-14 20:31:01 +00:00
Bob Wilson
8e86b5195b Set instruction encoding bits 4 and 7 for ARM register-register and 
register-shifted-register instructions.  Patch by Johnny Chen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84124 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-14 19:00:24 +00:00
Bob Wilson
24f995d84b Refactor code to select NEON VST intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84122 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-14 18:32:29 +00:00