Jim Grosbach
2f196747f1
ARM assembly parsing and encoding support for LDRD(label).
...
rdar://9932658
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 23:06:24 +00:00
Jim Grosbach
d22170e16a
ARM NEON two-operand aliases for VPADD.
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rdar://10602276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 19:51:03 +00:00
Jim Grosbach
61b74b4247
ARM NEON implied destination aliases for VMAX/VMIN.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146885 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 18:57:38 +00:00
Jim Grosbach
eeaf1c1636
ARM NEON relax parse time diagnostics for alignment specifiers.
...
There's more variation that we need to handle. Error checking will need
to be on operand predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-19 18:31:43 +00:00
Jim Grosbach
a738da7bd3
ARM NEON VCLE is an alias for VCGE w/ the source operands reversed.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146699 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 22:56:33 +00:00
Jim Grosbach
60d99a5278
ARM NEON VTBL/VTBX assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146691 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-15 22:27:11 +00:00
Jim Grosbach
9b1b390288
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146605 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 23:25:46 +00:00
Jim Grosbach
ec04a3f8db
ARM NEON fix alignment encoding for VST2 w/ writeback.
...
Add tests for w/ writeback instruction parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146594 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 21:49:24 +00:00
Jim Grosbach
e90ac9bce9
ARM NEON VST2 assembly parsing and encoding.
...
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146579 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 19:35:22 +00:00
Jim Grosbach
8d11c6349f
ARM/Thumb2 'cmp rn, #imm' alias to cmn.
...
When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.
rdar://10552389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146567 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 17:30:24 +00:00
Jim Grosbach
a39cda7aff
ARM assembler support for the target-specific .req directive.
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rdar://10549683
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146543 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 02:16:11 +00:00
Jim Grosbach
863d2af947
Thumb2 assembler aliases for "mov(shifted register)"
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rdar://10549767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146520 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 22:45:11 +00:00
Jim Grosbach
27debd60a1
ARM LDM/STM system instruction variants.
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rdar://10550269
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146519 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 21:48:29 +00:00
Jim Grosbach
0da6e867cf
Test for 146516
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 21:06:59 +00:00
Jim Grosbach
55b02f28c1
ARM thumb2 parsing of "rsb rd, rn, #0 ".
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rdar://10549741
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146515 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 20:50:38 +00:00
Jim Grosbach
0f293de207
ARM NEON two-operand aliases for VQDMULH.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146514 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 20:40:37 +00:00
Jim Grosbach
e91e7bcadc
ARM pre-UAL NEG mnemonic for convenience when porting old code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146511 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-13 20:23:22 +00:00
Jim Grosbach
840bf7eda7
ARM assembly aliases for BIC<-->AND (immediate).
...
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.
rdar://10550057
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146283 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 22:02:17 +00:00
Jim Grosbach
a4e3c7fc4b
ARM assembly parsing and encoding for VLD2 with writeback.
...
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146278 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-09 21:28:25 +00:00
Jim Grosbach
8759c3f548
ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146194 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:19:04 +00:00
Jim Grosbach
6b044c2609
ARM VSHR implied destination operand form aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146192 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:06:06 +00:00
Jim Grosbach
318df74104
Tidy up a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146190 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:04:40 +00:00
Jim Grosbach
120313435d
ARM VSUB implied destination operand form aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146182 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 20:56:26 +00:00
Jim Grosbach
beef39ab63
Tidy up a bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146181 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 20:53:19 +00:00
Jim Grosbach
9e7b42a40e
ARM VQADD implied destination operand form aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146179 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 20:49:43 +00:00
Jim Grosbach
1c2c8a9389
ARM a few more VMUL implied destination operand form aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146177 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 20:42:35 +00:00
Jim Grosbach
730fe6c1b6
ARM NEON two-operand aliases for VSHL(immediate).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 01:30:04 +00:00
Jim Grosbach
ff4cbb4c9a
ARM NEON two-operand aliases for VSHL(register).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146123 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 01:12:35 +00:00
Jim Grosbach
a44f2c4a28
ARM optional destination operand variants for VEXT instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146114 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:43:47 +00:00
Jim Grosbach
71a0a2ec0b
Tidy up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146113 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:41:54 +00:00
Jim Grosbach
3bc8a3d3af
ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146111 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 00:31:07 +00:00
Jim Grosbach
af4edea67b
ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
...
For 'gas' compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:40:58 +00:00
Jim Grosbach
9fa0a743e6
ARM two-operand aliases for VAND/VEOR/VORR instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146095 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:08:12 +00:00
Jim Grosbach
30a264eb7f
ARM two-operand aliases for VADDW instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146093 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 23:01:10 +00:00
Jim Grosbach
d900441e13
ARM two-operand aliases for VADD instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146091 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 22:52:54 +00:00
Jim Grosbach
8524bca750
Thumb2 alias for long-form pop and friends.
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rdar://10542474
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146046 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 18:32:28 +00:00
Jim Grosbach
9a70df99ca
ARM support the .arm and .thumb directives for assembly mode switching.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146042 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 18:04:19 +00:00
Jim Grosbach
470855b24f
ARM NEON VCLT(register) is a pseudo aliasing VCGT(register).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146039 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 17:51:15 +00:00
Jim Grosbach
d552a644be
Tidy up. Move MachO tests to MachO directory.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146038 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-07 17:50:28 +00:00
NAKAMURA Takumi
18851edbc4
test/MC: Introduce MC/MachO/ARM, and relocate relax-thumb2-branches.s into it.
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FIXME: Restore more other arch-dependent MachO tests. (eg. r126401 and r133856)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145925 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 06:48:26 +00:00
Jim Grosbach
23261af193
ARM mode 'mul' operand ordering tweak.
...
Same as r145922, just for ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145923 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 05:28:00 +00:00
Jim Grosbach
cf9814ddd2
Thumb2: MUL two-operand form encoding operand order fix.
...
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.
rdar://10532439
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145922 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 05:03:45 +00:00
Jim Grosbach
df33e0d05e
Thumb2 encoding choice correction for PLD.
...
Using encoding T1 for offset of #0 and encoding T2 for #-0.
rdar://10532413
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145919 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 04:49:29 +00:00
NAKAMURA Takumi
286ea03382
test/MC: Move relax-thumb2-branches.s from MC/MachO/ to MC/ARM.
...
MC/MachO assumes x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145916 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-06 03:56:05 +00:00
Jim Grosbach
713c70238c
Tweak ADDrr fix. Bad check for explicit .w
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145863 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 22:27:04 +00:00
Jim Grosbach
6e507c645d
Update tests for r145860. Add a few new ones.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145861 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 22:21:28 +00:00
Jim Grosbach
da84786bee
Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.
...
rdar://10529348
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145851 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 21:06:26 +00:00
Jim Grosbach
253ef7a779
ARM assembly parsing for the rest of the VMUL data type aliases.
...
Finish up rdar://10522016.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145846 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-05 20:29:59 +00:00
Jim Grosbach
c4f0b309ee
ARM tests for VLD1 single lane w/ writeback.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145713 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 22:03:52 +00:00
Jim Grosbach
dad2f8e7fb
Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
...
Add the 16-bit lane variants while I'm at it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145693 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-02 18:52:30 +00:00
Jim Grosbach
e30171ba0c
Add some tests for all-lanes VLD1 parsing.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145512 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-30 19:37:38 +00:00
Jim Grosbach
4c7edb3ad8
ARM assembly parsing and encoding for four-register VST1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145450 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 22:58:48 +00:00
Jim Grosbach
ed1f83f9af
Enable some VST1 tests and add a few more.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145443 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 22:40:32 +00:00
Chris Lattner
d2bf432b2b
Upgrade syntax of tests using volatile instructions to use 'load volatile' instead of 'volatile load', which is archaic.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145171 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-27 06:54:59 +00:00
Jim Grosbach
9b1671bae7
Remove obsolete test.
...
The PLD encoding is checked via the .s file now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144853 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:50:38 +00:00
Jim Grosbach
2abba8496c
Generalize the fixup info for ARM mode.
...
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144852 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:48:37 +00:00
Jim Grosbach
47a906ac23
Update test for r144842.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144851 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:46:27 +00:00
Jim Grosbach
e43862b6a6
ARM assembly parsing for register range syntax for VLD/VST register lists.
...
For example,
vld1.f64 {d2-d5}, [r2,:128]!
Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!
It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.
rdar://10451128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144727 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 23:19:15 +00:00
Jim Grosbach
9f302c4fb3
ARM assembly parsing two operand forms for shift instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144713 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 22:27:54 +00:00
Jim Grosbach
19885de61d
ARM alternate size suffices for VTRN instructions.
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rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144694 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 20:49:46 +00:00
Jim Grosbach
a68e90c36e
ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.
...
Yet more of rdar://10435076.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144691 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 20:29:42 +00:00
Jim Grosbach
bfb0a1717b
ARM assembly parsing for two-operand form of 'mul' instruction.
...
rdar://10449856.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 20:14:51 +00:00
Jim Grosbach
d2586daf06
ARM assembly parsing for two-operand form of 'mul' instruction.
...
Ongoing rdar://10435114.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144688 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 20:02:06 +00:00
Jim Grosbach
908f923cfc
Testcase for r144684.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144685 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 19:56:17 +00:00
Jim Grosbach
1de0bd1945
Thumb2 assembly parsing for mul.w in IT block fix.
...
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.
rdar://10449281
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144679 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 19:29:45 +00:00
Jim Grosbach
dd47e0b5d4
ARM parsing datatype suffix variants for non-writeback VST1 instructions.
...
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144593 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:43:46 +00:00
Jim Grosbach
e052b9afa1
ARM parsing datatype suffix variants for non-writeback VLD1 instructions.
...
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144592 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:32:59 +00:00
Jim Grosbach
ef448767a3
ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions.
...
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144587 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:11:19 +00:00
Jim Grosbach
ffc658b056
ARM VLDR/VSTR instructions don't need a size suffix.
...
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:03:21 +00:00
Jim Grosbach
c7352f8ca0
ARM optional size suffix for VLDR/VSTR syntax.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144427 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 23:34:43 +00:00
Jim Grosbach
ce485e7f70
ARM allow Q registers in vldm/vstm register lists.
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rdar://9672822
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144407 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 21:27:40 +00:00
Jim Grosbach
5402637ff2
Thumb2 parsing for push/pop w/ hi registers in the reglist.
...
rdar://10130228.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144331 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 23:17:11 +00:00
Jim Grosbach
1b332860ae
Thumb MUL assembly parsing for 3-operand form.
...
Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.
rdar://10428630
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144322 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 22:10:12 +00:00
Jim Grosbach
ee10ff89a2
ARM assembly parsing for LSR/LSL/ROR(immediate).
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More of rdar://9704684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144301 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 19:18:01 +00:00
Jim Grosbach
71810ab7c0
ARM assembly parsing for ASR(immediate).
...
Start of rdar://9704684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144293 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10 16:44:55 +00:00
Jim Grosbach
3c5d6e4df4
Thumb2 assembly parsing STMDB w/ optional .w suffix.
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rdar://10422955
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144242 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-09 23:44:23 +00:00
Benjamin Kramer
70be28a5ad
Simplify some uses of utohexstr.
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As a side effect hex is printed lowercase instead of uppercase now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144013 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-07 21:00:59 +00:00
Jim Grosbach
89a6337085
Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm".
...
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
mov r2, #-3
becomes
mvn r2, #2
rdar://10349224
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143235 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-28 22:36:30 +00:00
Jim Grosbach
5d0492cfc4
Thumb2 ADD/SUB instructions encoding selection outside IT block.
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Outside an IT block, "add r3, #2 " should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).
rdar://10348481
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143201 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-28 16:57:07 +00:00
Jim Grosbach
c73d73eb88
ARM Allow 'q' registers in VLD/VST vector lists.
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Just treat it as if the constituent D registers where specified.
rdar://10348896
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143167 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-28 00:06:50 +00:00
Jim Grosbach
88484c0030
Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix.
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rdar://10348844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143110 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-27 17:33:59 +00:00
Jim Grosbach
036a67d670
Thumb2 t2MVNi assembly parsing to recognize ".w" suffix.
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rdar://10348584
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143108 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-27 17:16:55 +00:00
Jim Grosbach
a581328ceb
Thumb2 ldr pc-relative encoding fixes.
...
We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.
More of rdar://10348687
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143068 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-26 22:22:01 +00:00
Jim Grosbach
399cdca4d2
ARM assembly parsing and encoding for VLD1 with writeback.
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Four entry register lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142882 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-25 00:14:01 +00:00
Jim Grosbach
5921675ff5
ARM assembly parsing and encoding for VLD1 w/ writeback.
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Three entry register list variation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142876 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24 23:26:05 +00:00
Jim Grosbach
12431329d6
ARM assembly parsing and encoding for VLD1 w/ writeback.
...
One and two length register list variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142861 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24 22:16:58 +00:00
Jim Grosbach
1028132b90
Update test for r142801.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142806 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24 17:26:26 +00:00
Jim Grosbach
224180e81b
Assembly parsing for 4-register sequential variant of VLD2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142704 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 23:58:57 +00:00
Jim Grosbach
4661d4cac3
Assembly parsing for 2-register sequential variant of VLD2.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142691 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 22:21:10 +00:00
Jim Grosbach
b6310316db
Assembly parsing for 4-register variant of VLD1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 20:35:01 +00:00
Jim Grosbach
cdcfa28056
Assembly parsing for 3-register variant of VLD1.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 20:02:19 +00:00
Jim Grosbach
280dfad489
ARM VLD parsing and encoding.
...
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-21 18:54:25 +00:00
Owen Anderson
cd20c58e98
Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142626 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 22:23:58 +00:00
Owen Anderson
5096503184
Fix tests for corrected MSR encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142622 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 21:53:19 +00:00
Jim Grosbach
6b09c77b7a
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 15:04:25 +00:00
Jim Grosbach
760b46ce18
Tidy up formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142582 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 14:57:47 +00:00
Jim Grosbach
d0b614754e
ARM VTBX (one register) assembly parsing and encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142581 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 14:48:50 +00:00
Jim Grosbach
2933e4b2e6
Tidy up formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142422 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 21:09:01 +00:00
Jim Grosbach
39dc2af7f9
Tidy up formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142421 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 21:08:16 +00:00
Jim Grosbach
0487e459e0
Enable more encoded immediate tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142415 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 20:20:51 +00:00
Jim Grosbach
ca8d1842cf
More vmov lane testcases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142414 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 20:19:48 +00:00
Jim Grosbach
aead579017
ARM vmla/vmls assembly parsing for the lane index operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142413 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 20:14:56 +00:00
Jim Grosbach
687656c630
ARM vmov assembly parsing for the lane index operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142412 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 20:10:47 +00:00
Jim Grosbach
9120088979
ARM vmla/vmls assembly parsing for the lane index operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142389 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 18:27:07 +00:00
Owen Anderson
e8692ed5a6
Another failing encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142388 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 18:23:03 +00:00
Jim Grosbach
82fa5fc709
Fix NEON mul encoding tests. Wrong file contents previously.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142387 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 18:14:55 +00:00
Jim Grosbach
0a0374018f
ARM vqdmulh assembly parsing for the lane index operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142386 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 18:12:09 +00:00
Jim Grosbach
37a3ed21c4
Remove duplicate test.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142383 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 18:05:50 +00:00
Jim Grosbach
9e7df4ad5b
Tidy up formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142382 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 18:05:16 +00:00
Jim Grosbach
970f787a7e
ARM vmul assembly parsing for the lane index operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142381 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 18:01:52 +00:00
Jim Grosbach
ec11d2a1b8
Tidy up.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142380 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 18:01:09 +00:00
Owen Anderson
aff187a19a
Add a few more testcases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142379 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 17:57:31 +00:00
Owen Anderson
de1ff7f552
Add several FIXME cases for ARM encodings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142377 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 17:50:22 +00:00
Jim Grosbach
5e3e811bf6
Tests for 142365.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142368 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 17:23:34 +00:00
Jim Grosbach
4442824614
Tidy up formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142367 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 17:22:53 +00:00
Jim Grosbach
f2f5bc60f6
ARM assembly parsing and encoding for VMOV.i64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142356 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 16:18:11 +00:00
Jim Grosbach
6248a546f2
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142321 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-18 00:22:00 +00:00
Jim Grosbach
7c81013c45
Enable a few more NEON immediate tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142313 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 23:50:19 +00:00
Jim Grosbach
ea46110f57
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142303 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 23:09:09 +00:00
Jim Grosbach
0e387b2877
ARM NEON "vmov.i8" immediate assembly parsing and encoding.
...
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142293 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 22:26:03 +00:00
Owen Anderson
008c838434
Update test for disabling of code/data marker labels in ELF.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-14 21:12:55 +00:00
Jim Grosbach
c66e7afcf2
Thumb2 assembly parsing and encoding for LDC/STC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 20:54:17 +00:00
Jim Grosbach
9f45754750
ARM encoding tests for STC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141787 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 17:36:13 +00:00
Jim Grosbach
9b8f2a0b36
ARM parsing and encoding for the <option> form of LDC/STC instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-12 17:34:41 +00:00
Jim Grosbach
2bd0118472
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.
...
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141721 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-11 21:55:36 +00:00
Jim Grosbach
051fee0312
Enable ARM mode VDUP(scalar) tests.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141447 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 23:57:03 +00:00
Jim Grosbach
460a90540b
ARM NEON assembly parsing and encoding for VDUP(scalar).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141446 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 23:56:00 +00:00
Jim Grosbach
bee5d2fac8
Tidy up tests. Un-XFAIL file and mark individual tests as FIXME instead.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141321 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 22:04:05 +00:00
Jim Grosbach
7abb795635
Fix and clean up tests. Un-XFAIL.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141318 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 21:32:50 +00:00
Jim Grosbach
d6f85098e1
Fix and clean up tests. Un-XFAIL.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141316 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 21:28:30 +00:00
Owen Anderson
2dbb46a0a0
Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141190 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 17:16:40 +00:00
Owen Anderson
2fec6c5ff1
Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141135 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 23:26:17 +00:00
Jim Grosbach
0ebefdf834
Tidy up formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141123 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 21:43:51 +00:00
Jim Grosbach
fdf6bb41a4
Un-XFAIL file. Comment out individual failing instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141117 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 21:16:42 +00:00
Jim Grosbach
20f8eb2fc1
Tidy up formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141115 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 20:52:57 +00:00
Jim Grosbach
e5c933848a
Un-XFAIL file. Fix incorrect CHECK lines. General format cleanup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141114 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 20:50:05 +00:00
Jim Grosbach
dc6c93531d
Un-XFAIL file. Fix incorrect CHECK line. General format cleanup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141113 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 20:46:49 +00:00
Jim Grosbach
100902c6da
Tidy up formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141111 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 20:42:35 +00:00
Jim Grosbach
0c0cf47ed5
Un-XFAIL file. Fix incorrect CHECK line.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141110 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 20:42:09 +00:00
Jim Grosbach
62ea269b9a
Un-XFAIL the file. Disable only the individual tests that aren't working yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141108 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 20:34:11 +00:00
Jim Grosbach
a02dfe7a6b
Un-XFAIL the file. Disable only the individual tests that aren't working yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141099 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 18:43:15 +00:00
Jim Grosbach
36db6fbe57
Tidy up. Formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141096 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-04 17:49:45 +00:00
Jim Grosbach
3207e6c6b7
Tidy up. These tests are covered in the .s file tests now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141047 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 23:40:13 +00:00
Jim Grosbach
9d39036f62
ARM assembly parsing and encoding for VMOV immediate.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141046 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 23:38:36 +00:00
Jim Grosbach
68259145d9
ARM parsing/encoding for VCMP/VCMPE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141038 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 22:30:24 +00:00
Jim Grosbach
5cd5ac6ad4
ARM assembly parsing and encoding for VMRS/FMSTAT.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141025 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 21:12:43 +00:00
Jim Grosbach
f8bf43ec99
Update test for 141010.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 20:58:08 +00:00
Jim Grosbach
c82c101147
Tidy up a bit. Formatting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141010 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 17:59:31 +00:00
James Molloy
acad68da50
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
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Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 14:21:38 +00:00
Jim Grosbach
25ddc2bf7e
ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.
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Add inst alias to handle these assembly forms. Add tests, too.
rdar://10178799
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140647 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-27 22:18:54 +00:00