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35 Commits

Author SHA1 Message Date
Venkatraman Govindaraju
c594f39acb [Sparc] Add trap on integer condition codes (Ticc) instructions to Sparc backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202670 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-02 23:39:07 +00:00
Venkatraman Govindaraju
2871375882 [SparcV9] Adds support for branch on integer register instructions (BPr) and conditional moves on integer register (MOVr/FMOVr). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202628 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-02 09:46:56 +00:00
Venkatraman Govindaraju
18fe44cb05 [Sparc] Make floating point branch instruction formats to accept %fcc0-%fcc1 conditional registers as input. 
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202614 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-02 04:43:45 +00:00
Venkatraman Govindaraju
afad335cae [Sparc] Add support for parsing fcmp with %fcc registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202610 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-02 03:39:39 +00:00
Venkatraman Govindaraju
628886b1d2 [SparcV9] Add support for parsing branch instructions with prediction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202602 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-01 22:03:07 +00:00
Venkatraman Govindaraju
e4c88dd909 [Sparc] Add support for parsing annulled branch instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202599 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-01 20:08:48 +00:00
Venkatraman Govindaraju
464d664971 [Sparc] Emit correct encoding for atomic instructions. Also, add support for parsing CAS instructions to test the CAS encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200963 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-07 07:34:49 +00:00
Venkatraman Govindaraju
8f5124903f [SparcV9] Rename operands in some sparc64 instructions so that TableGen can encode them correctly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198740 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-08 07:47:57 +00:00
Venkatraman Govindaraju
9429f47d83 [Sparc] Add initial implementation of disassembler for sparc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198591 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-06 08:08:58 +00:00
Venkatraman Govindaraju
0821c72f11 [Sparc] Make SPARC instructions' encoding well defined such that TableGen can automatically generate code emitter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191168 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-22 09:54:42 +00:00
Venkatraman Govindaraju
69ae8f1abd [Sparc] Clean up MOVcc instructions so that TableGen can encode them correctly. No functionality change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191167 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-22 09:18:26 +00:00
Venkatraman Govindaraju
a432a97b62 [Sparc] Clean up branch instructions, so that TableGen can encode branch conditions as well. No functionality change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191166 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-22 08:51:55 +00:00
Venkatraman Govindaraju
1e06bcbd63 Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183243 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 18:33:25 +00:00
Jakob Stoklund Olesen
d9f88da7b3 Use i32 for all SPARC shift amounts, even in 64-bit mode. 
Test case by llvm-stress.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179477 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-14 05:48:50 +00:00
Jakob Stoklund Olesen
c3ff3f42ee Add 64-bit shift instructions. 
SPARC v9 defines new 64-bit shift instructions. The 32-bit shift right
instructions are still usable as zero and sign extensions.

This adds new F3_Sr and F3_Si instruction formats that probably should
be used for the 32-bit shifts as well. They don't really encode an
simm13 field.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178525 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-02 04:09:12 +00:00
Jia Liu
31d157ae1a Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-02-18 12:03:15 +00:00
Chris Lattner
4ee451de36 Remove attribution from file headers, per discussion on llvmdev. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-12-29 20:36:04 +00:00
Evan Cheng
64d80e3387 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-07-19 01:14:50 +00:00
Chris Lattner
aca36b9329 Use a couple of multiclass patterns to factor some integer ops. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30039 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-09-01 22:28:02 +00:00
Chris Lattner
7c90f73a1b Rename SPARC V8 target to be the LLVM SPARC target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25985 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-05 05:50:24 +00:00
Chris Lattner
eee99bd459 Push ops list, asm string, and pattern all the way up to InstV8. Move the 
InstV8 class to the InstrFormats file where it belongs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24824 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-18 08:21:00 +00:00
Chris Lattner
4d55aca87a Add initial conditional branch support. This doesn't actually work yet due 
to a bug in the scheduler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24807 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-18 01:20:35 +00:00
Chris Lattner
558bfe0cf5 Give patterns to F3_3 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24800 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-17 23:05:35 +00:00
Chris Lattner
57dd3bc460 Use sethi to build large immediates with zeros at the bottom 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24779 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-17 19:37:00 +00:00
Chris Lattner
e33a3ff942 Add empty patterns to all F3_1 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24776 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-17 18:49:14 +00:00
Chris Lattner
f3bf50d2c8 Add empty patterns for F3_2 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24771 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-17 08:06:43 +00:00
Chris Lattner
0d8fcd3218 Convert the remaining instructions over, branches and calls. Fix a couple 
minor bugs


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24762 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-17 06:54:41 +00:00
Chris Lattner
dc6938ac23 convert FP instructions to use an asmstring and operand list, allowing FP 
programs to work on V8 again


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24761 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-17 06:32:52 +00:00
Chris Lattner
13e1501c91 Add a couple more instrs 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24744 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-16 07:18:48 +00:00
Chris Lattner
d4f2ab5e00 Autogenerate asmprinter for F3_2 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24741 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-16 07:10:02 +00:00
Chris Lattner
1c4f435603 Switch F3_1 instructions over to use AsmStrings 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24740 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-16 06:52:00 +00:00
Chris Lattner
96b84beb77 Add operand info for F3_[12] instructions, getting V8 back to basic functionality. 
With this, Regression/CodeGen/SparcV8/basictest.ll now passes.  Lets hear it
for regression tests :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24738 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-16 06:25:42 +00:00
Misha Brukman
45a68268a4 Class F2_1 already inherits the imm22 field from class F2 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17001 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-14 22:32:24 +00:00
Misha Brukman
17187e936a * In the F3_1 class, default asi to 0 because it's not currently used 
* In the F3_3 class, remove mention of asi because it's not part of the format


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16999 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-14 21:53:39 +00:00
Misha Brukman
c42077d371 Combine the F2 and F3 instruction classes into one file for simplicity 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16484 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-22 21:38:42 +00:00