Evan Cheng
eaa91b0a1f
Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37643 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-19 01:26:51 +00:00
Evan Cheng
d42e56e166
Instructions with unique labels or embedded jumptables cannot be duplicated during ifcvt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37606 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-15 21:15:00 +00:00
Dale Johannesen
13e8b51e3e
Handle blocks with 2 unconditional branches in AnalyzeBranch.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37571 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-13 17:59:52 +00:00
Evan Cheng
bfd2ec4a8e
Add a utility routine to check for unpredicated terminator instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37528 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-08 21:59:56 +00:00
Lauro Ramos Venancio
61718a6285
Define AsmTransCBE for ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37527 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-08 21:06:23 +00:00
Evan Cheng
1fc7cb695c
Fix ARM condition code subsumission check.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37517 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-08 09:14:47 +00:00
Evan Cheng
f81dea45b5
tBcc is not a barrier.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37516 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-08 09:13:23 +00:00
Evan Cheng
9328c1ac66
Stupid cut-n-paste bug caused me soooo much grief. Why wasn't there a compilation warning? I blame it on the FE folks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37484 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-07 01:37:54 +00:00
Evan Cheng
2c614c5c69
Mark these instructions clobbersPred. They modify the condition code register.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37468 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-06 10:17:05 +00:00
Evan Cheng
5e148a37d3
Print predicate of the second instruction of the two-piece constant MI.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37437 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-05 18:55:18 +00:00
Evan Cheng
341dcccb4e
PIC label asm printing cosmetic changes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37434 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-05 07:36:38 +00:00
Chris Lattner
c621ae7bba
update this entry, now that Anton implemented shift/and lowering for
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switches. There is one really easy isel thing here with tst we are not
getting.
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2007-06-02 18:45:14 +00:00
Evan Cheng
c354334ac4
Opcode modifier s comes after condition code. e.g. addlts, not addslt.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37388 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-01 20:51:29 +00:00
Evan Cheng
144fd1ff0f
Set ARM ifcvt duplication limit to 3 for now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37385 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-01 08:28:59 +00:00
Evan Cheng
df4da14948
Make jumptable non-predicable for now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37381 91177308-0d34-0410-b5e6-96231b3b80d8
2007-06-01 00:56:15 +00:00
Chris Lattner
3a4205367d
Fix the asmprinter so that a globalvalue can specify an explicit alignment
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smaller than the preferred alignment, but so that the target can actually
specify a minimum alignment if needed. This fixes some objc protocol
failures Devang tracked down.
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2007-05-31 18:57:45 +00:00
Evan Cheng
c6f2f6fbb9
For VFP2 fldm, fstm instructions, the condition code is printed after the address mode and size specifier. e.g. fstmiaseq, not fstmeqias.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37351 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-29 23:34:19 +00:00
Evan Cheng
fd488edb1d
For ldrb, strh, etc., the condition code is before the width specifier. e.g. streqh, not strheq.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37349 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-29 23:32:06 +00:00
Evan Cheng
62ccdbf0b3
Add missing const qualifiers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37342 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-29 18:42:18 +00:00
Evan Cheng
69d555611a
Hooks for predication support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37308 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-23 07:22:05 +00:00
Evan Cheng
94679e66bb
Fix some -march=thumb regressions. tBR_JTr is not predicable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37272 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-21 23:17:32 +00:00
Dale Johannesen
f23b8cf239
Use AXI3 not AXI2 for appropriate PIC PC-relative loads and stores. Cosmetic.
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2007-05-21 22:42:04 +00:00
Dale Johannesen
86d4069666
Add some patterns for PIC PC-relative loads and stores.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37269 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-21 22:14:33 +00:00
Evan Cheng
5a18ebc70c
BlockHasNoFallThrough() now returns true if block ends with a return instruction; AnalyzeBranch() should ignore predicated instructionsd.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37268 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-21 18:56:31 +00:00
Evan Cheng
dcc50a4aee
Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37199 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-18 01:53:54 +00:00
Evan Cheng
e5e7ce458a
Silence some compilation warnings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37197 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-18 01:19:57 +00:00
Evan Cheng
9f8cbd147c
Set ARM if-conversion block size threshold to 10 instructions for now.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37194 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-18 00:19:34 +00:00
Evan Cheng
6ae3626a4f
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37193 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-18 00:18:17 +00:00
Dale Johannesen
8dd86c14d4
More effective breakdown of memcpy into repeated load/store. These are now
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in the order lod;lod;lod;sto;sto;sto which means the load-store optimizer
has a better chance of producing ldm/stm. Ideally you would get cooperation
from the RA as well but this is not there yet.
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2007-05-17 21:31:21 +00:00
Evan Cheng
3f8602cf20
ARM::tB is also predicable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37125 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-16 21:53:43 +00:00
Evan Cheng
02c602b333
PredicateInstruction returns true if the operation was successful.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37124 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-16 21:53:07 +00:00
Evan Cheng
75604f81b7
Move if-conversion after all passes that may use register scavenger.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37120 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-16 20:52:46 +00:00
Evan Cheng
b5f8eff566
Removed isPredicable().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37119 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-16 20:50:23 +00:00
Evan Cheng
5ada199246
Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37118 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-16 20:50:01 +00:00
Evan Cheng
aeafca0a25
Conditional branch is not a barrier.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37103 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-16 07:45:54 +00:00
Evan Cheng
2706f9771d
Fix comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37098 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-16 05:14:06 +00:00
Evan Cheng
9307292ae2
Hooks for predication support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37093 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-16 02:01:49 +00:00
Evan Cheng
44bec52b1b
Add PredicateOperand to all ARM instructions that have the condition field.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37066 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-15 01:29:07 +00:00
Lauro Ramos Venancio
5d3d44a848
Fix previous patch. GOTOFF can be used only when the symbol has internal
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linkage or hidden visibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37055 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-14 23:20:21 +00:00
Lauro Ramos Venancio
930d161ba2
Optimize PIC implementation. GOTOFF can be used when the symbol is defined
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and used in the same module.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37044 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-14 18:46:23 +00:00
Lauro Ramos Venancio
69642f11ed
Enable aliases on arm-linux.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37042 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-14 18:32:56 +00:00
Evan Cheng
42d712b306
Switch BCC, MOVCCr, etc. to PredicateOperand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36948 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-08 21:08:43 +00:00
Lauro Ramos Venancio
356e72c4f1
Fix PR1390 in a better way.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36916 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-07 23:15:16 +00:00
Evan Cheng
c4e600362e
This is no longer needed after enabling the DAG combiner xform.
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2007-05-07 21:29:41 +00:00
Lauro Ramos Venancio
8f57667a5d
Fix PR1390.
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Don't spill extra register to align the stack.
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2007-05-05 23:44:41 +00:00
Lauro Ramos Venancio
a8e9562906
Add a processor.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36765 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-04 22:16:30 +00:00
Evan Cheng
97c9bb5cc6
On Mac OS X, GV requires an extra load only when relocation-model is non-static.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36718 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-04 00:26:58 +00:00
Evan Cheng
bdc9869dbf
Should never see an indexed load / store with zero offset.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36714 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-03 23:30:36 +00:00
Dale Johannesen
4ac075c859
Evan's patch to avoid FPreg->intreg copy for cvt; store to mem
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36693 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-03 20:54:42 +00:00
Lauro Ramos Venancio
e8e5495474
Debug support for arm-linux.
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Patch by Raul Herbster.
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2007-05-03 20:28:35 +00:00
Chris Lattner
388488d604
add support for printing offset from global
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36669 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-03 16:42:23 +00:00
Evan Cheng
0b0a9a90a4
Typo. It's checking if V is multiple of 4, not multiple of 3. :-)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36663 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-03 02:00:18 +00:00
Devang Patel
1997473cf7
Drop 'const'
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36662 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-03 01:11:54 +00:00
Chris Lattner
72939126d4
match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.ll
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36660 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-03 00:32:00 +00:00
Devang Patel
3e15bf33e0
Use 'static const char' instead of 'static const int'.
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Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36652 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-02 21:39:20 +00:00
Dale Johannesen
67cf561b7f
Add some support for (Darwin) code-generating directives in getInlineAsmLength.
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Support is incomplete, but more accurate than gcc's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36634 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-02 01:02:40 +00:00
Devang Patel
794fd75c67
Do not use typeinfo to identify pass in pass manager.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36632 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-01 21:15:47 +00:00
Evan Cheng
1b20168433
Doh. PC displacement is between the constantpool and the add instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36630 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-01 20:27:19 +00:00
Evan Cheng
97de913821
eliminateFrameIndex() change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36626 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-01 09:13:03 +00:00
Evan Cheng
5c3885ce8e
Under normal circumstances, when a frame pointer is not required, we reserve
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argument space for call sites in the function immediately on entry to the
current function. This eliminates the need for add/sub sp brackets around call
sites. However, this is not always a good idea. If the "call frame" is large and
the target load / store instructions have small immediate field to encode sp
offset, this can cause poor codegen. In the worst case, this can make it
impossible to scavenge a register if the reserved spill slot is pushed too far
apart from sp / fp.
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2007-05-01 00:52:08 +00:00
Dale Johannesen
9118dbc7bd
Remove item: thumb padding in constant islands
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2007-04-30 00:32:06 +00:00
Dale Johannesen
23c968478e
remove unused variable
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36585 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-30 00:30:48 +00:00
Lauro Ramos Venancio
0a1817392d
Enable protected visibility on ARM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36583 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-30 00:23:51 +00:00
Dale Johannesen
8593e41855
Rewrite of Thumb constant islands handling (exact allowance for padding
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around islands and jump tables).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36573 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-29 19:19:30 +00:00
Dale Johannesen
8650199fbb
Make ARM-specific version of getInlineAsmLength
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36572 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-29 19:17:45 +00:00
Dale Johannesen
caa8055cf5
change per review
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2007-04-28 00:36:37 +00:00
Dale Johannesen
25c1f9e125
Prevent Thumb code from generating ARM instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36518 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-27 22:17:18 +00:00
Lauro Ramos Venancio
4c6d20a096
add parenthesis.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36514 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-27 20:10:08 +00:00
Evan Cheng
185ea1e2aa
Doh. ARM::LEApcrel is a single instruction MI.
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2007-04-27 18:27:13 +00:00
Lauro Ramos Venancio
fdc9692f97
In Thumb mode, the frame register must be R7.
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2007-04-27 17:58:03 +00:00
Lauro Ramos Venancio
64f4fa5e0e
ARM TLS: implement "general dynamic", "initial exec" and "local exec" models.
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2007-04-27 13:54:47 +00:00
Evan Cheng
b1df8f2750
Darwin runtime library does not have these.
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2007-04-27 08:15:43 +00:00
Evan Cheng
768c9f725b
Special handling of LEApcrel and tLEApcrel.
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2007-04-27 08:14:15 +00:00
Evan Cheng
eec041a037
Back out previous check-in. Incorrect.
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2007-04-27 07:50:02 +00:00
Evan Cheng
33fdc983fd
tLEApcrel is a AddrModeTs, i.e. pc relative.
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2007-04-27 07:37:22 +00:00
Evan Cheng
faa510726f
Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion.
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2007-04-26 19:00:32 +00:00
Evan Cheng
6c087e5585
Match MachineFunction::UsedPhysRegs changes.
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2007-04-25 22:13:27 +00:00
Lauro Ramos Venancio
305b8a5f62
remember to emit weak reference in one more case.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36438 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-25 14:50:40 +00:00
Evan Cheng
1e341729dd
Relex assertions to account for additional implicit def / use operands.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36430 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-25 07:12:14 +00:00
Dale Johannesen
56c42ef3e4
Make Thumb funcs containing islands 4-byte aligned. Fix bugs maintaining
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BBOffsets and BBSizes when adjusting conditional branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36372 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-23 20:09:04 +00:00
Dale Johannesen
bd24f3f398
add Align field, and use when generating function alignment
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36371 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-23 20:07:25 +00:00
Dale Johannesen
24fb52da3c
add isThumb (unused as yet)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36370 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-23 20:04:35 +00:00
Lauro Ramos Venancio
0ae4a3357a
Implement PIC for arm-linux.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36324 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-22 00:04:12 +00:00
Evan Cheng
ba647becb9
Specify S registers as D registers' sub-registers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36280 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-20 21:20:10 +00:00
Chris Lattner
93305bc462
add a crazy idea
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36273 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-20 20:18:43 +00:00
Lauro Ramos Venancio
267bfb553e
Fix a bug in getFrameRegister.
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Reported by Raul Herbster.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36262 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-19 14:09:38 +00:00
Chris Lattner
120fba91a3
dag combiner just got better at pruning bits. This fixes CodeGen/ARM/rev.ll
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36222 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-17 22:39:58 +00:00
Chris Lattner
3c30d10b04
add a note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36203 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-17 18:03:00 +00:00
Anton Korobeynikov
bed2946a96
Removed tabs everywhere except autogenerated & external files. Add make
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target for tabs checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36146 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-16 18:10:23 +00:00
Chris Lattner
5a3d40d88f
arm has r+r*s and r+i addr modes, but no r+i+r*s addr modes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35962 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-13 06:50:55 +00:00
Chris Lattner
e11529438c
Fix incorrect fall-throughs in addr mode code. This fixes CodeGen/ARM/arm-negative-stride.ll
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35909 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-11 16:17:12 +00:00
Chris Lattner
eb13d1b710
restore support for negative strides
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35859 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-10 03:48:29 +00:00
Chris Lattner
37caf8c68e
remove dead target hooks
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35846 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09 23:33:39 +00:00
Chris Lattner
b445d0cbb9
remove some dead target hooks, subsumed by isLegalAddressingMode
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35840 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-09 22:27:04 +00:00
Evan Cheng
e21e39666e
Implement inline asm modifier P.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35640 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-04 00:13:29 +00:00
Evan Cheng
0a7baa24d1
Typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35639 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-04 00:06:07 +00:00
Evan Cheng
ed884f3a2f
Remove unused constant pool entries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35635 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-03 23:39:48 +00:00
Evan Cheng
b03eacdbf3
Fixed a bug that causes codegen of noop like add r0, r0, #0 .
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35627 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-03 21:31:21 +00:00
Evan Cheng
3c5ad82ba2
Inverted logic.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35619 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-03 06:44:25 +00:00
Chris Lattner
b2c594f350
Arm supports negative strides as well, add them. This lets us compile:
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CodeGen/ARM/arm-negative-stride.ll to:
LBB1_2: @bb
str r1, [r3, -r0, lsl #2 ]
add r0, r0, #1
cmp r0, r2
bne LBB1_2 @bb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35609 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-03 00:13:57 +00:00