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18983 Commits

Author SHA1 Message Date
Benjamin Kramer
aeb7de764a Fix cmake again :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135613 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 20:00:06 +00:00
Evan Cheng
203576aa0c Goodbye TargetAsmInfo. This eliminate last bit of CodeGen and Target in llvm-mc. 
There is still a bit more refactoring left to do in Targets. But we are now very
close to fixing all the layering issues in MC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135611 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 19:50:42 +00:00
Eli Friedman
a4d0bd84f7 Extend the hack for _GLOBAL_OFFSET_TABLE_ slightly; PR10389. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135607 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 19:36:11 +00:00
Jim Grosbach
ab40f4b737 ARM assembly parsing of MUL instruction. 
Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135596 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 18:20:31 +00:00
Evan Cheng
34ad6db8b9 - Move CodeModel from a TargetMachine global option to MCCodeGenInfo. 
- Introduce JITDefault code model. This tells targets to set different default
  code model for JIT. This eliminates the ugly hack in TargetMachine where
  code model is changed after construction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135580 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 07:51:56 +00:00
Evan Cheng
e76a33b956 Add MCObjectFileInfo and sink the MCSections initialization code from 
TargetLoweringObjectFileImpl down to MCObjectFileInfo.

TargetAsmInfo is done to one last method. It's *almost* gone!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135569 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 05:58:47 +00:00
NAKAMURA Takumi
e3345c4e4a X86Subtarget.h: Assume "x86_64-cygwin", though it has not been released yet, to appease test/CodeGen/X86 on cygwin. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135564 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 04:02:20 +00:00
Benjamin Kramer
e236dc6553 Don't leak CodeGenInfos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135555 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 01:27:58 +00:00
Akira Hatanaka
de9416e261 Change name of class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135550 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 00:53:09 +00:00
Akira Hatanaka
32b7ebb163 Define classes for definitions of atomic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135546 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 00:23:01 +00:00
Akira Hatanaka
db54826f20 Lower memory barriers to sync instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135537 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 23:30:50 +00:00
Jim Grosbach
b29b4dd988 Tweak ARM assembly parsing and printing of MSR instruction. 
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135532 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 22:45:10 +00:00
Jim Grosbach
80d01dd3d1 ARM assembly parsing of MRS instruction. 
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135527 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 21:59:29 +00:00
Owen Anderson
f1a0090073 Enhance the FixedLengthDecoder to be able to generate plausible-looking decoders for ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135524 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 21:06:00 +00:00
Akira Hatanaka
bdd83fe382 Change variable name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135522 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 20:56:53 +00:00
Jim Grosbach
ccfd9313d1 ARM assembly parsing for MRC/MRC2/MRRC/MRRC2. 
Add range checking to the immediate operands. Update tests accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135521 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 20:35:35 +00:00
Akira Hatanaka
cc7ecc7290 Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or 
ANDi, when the instruction does not have any immediate operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135520 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 20:34:00 +00:00
Akira Hatanaka
4061da1403 Use descriptive variable names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135514 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 20:11:17 +00:00
Jim Grosbach
5f16057d1e ARM assembly parsing for MOV (register). 
Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135513 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 20:10:31 +00:00
Jim Grosbach
558b66d3cd Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135507 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 19:47:11 +00:00
Jim Grosbach
731f209794 Tighten conditional for 'mov' cc_out. 
Make sure we only clobber the cc_out operand if it is indeed a default
non-setting operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135506 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 19:45:44 +00:00
Jim Grosbach
ffa3225e26 ARM assembly parsing for MOV (immediate). 
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135500 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 19:13:28 +00:00
Jim Grosbach
5a18700470 Remove unused code. 
cc_out and pred operands are added during parsing via custom C++ now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135497 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 18:32:48 +00:00
Akira Hatanaka
29af0918ce Fix comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135496 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 18:19:40 +00:00
Akira Hatanaka
70564a9c19 Remove redundant instructions. 
- In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the
  instruction being expanded, instead of masking it in thisMBB. 
- Remove redundant Or in EmitAtomicCmpSwap. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135495 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 18:14:26 +00:00
Akira Hatanaka
81b441151f Separate code that modifies control flow from code that adds instruction to 
basic blocks.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135490 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 17:09:53 +00:00
Jim Grosbach
6bc1dbc376 ARM range checking for so_imm operands in assembly parsing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135489 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 16:50:30 +00:00
Jay Foad
ca12a2139e Convert gep_type_begin and gep_type_end to use ArrayRef. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135481 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 14:42:50 +00:00
Jay Foad
8fbbb39807 Convert TargetData::getIndexedOffset to use ArrayRef. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135478 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 14:01:37 +00:00
Richard Osborne
c8007ab582 Add intrinsics for the zext / sext instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135476 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 13:28:50 +00:00
Richard Osborne
829bef1a46 Add intrinsics for the testct, testwct instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135475 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 13:00:40 +00:00
Richard Osborne
dee3dd9129 Add intrinsics for the peek and endin instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135474 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 12:50:25 +00:00
Evan Cheng
439661395f Introduce MCCodeGenInfo, which keeps information that can affect codegen 
(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135468 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 06:37:02 +00:00
Akira Hatanaka
939ece1b5c Make EmitAtomic functions return the correct MachineBasicBlocks so that 
ExpandISelPseudos::runOnMachineFunction does not visit instructions that have
just been added.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135465 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 03:42:13 +00:00
Akira Hatanaka
a308c670b4 Do not insert instructions in reverse order. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135464 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 03:14:58 +00:00
Owen Anderson
565a036697 Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having multiple instructions with the same encoding. This resolves another conflict when bringing up the new-style disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135442 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 23:25:34 +00:00
Evan Cheng
c8c3acfea4 Eliminate TargetAsmInfo::getCompactUnwindEncoding. This get rid of the 
use of TargetFrameLowering in TargetAsmInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135439 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 22:32:12 +00:00
Evan Cheng
2d28617de2 Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for 
better location welcome).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135438 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 22:29:13 +00:00
Owen Anderson
91614aec48 Mark the Darwin assembler workout as isCodeGenOnly, so that it doesn't cause decoding conflicts in the new-style disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135434 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 22:14:02 +00:00
Evan Cheng
0e6a052331 Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down 
to MCRegisterInfo. Also initialize the mapping at construction time.

This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 20:57:22 +00:00
Akira Hatanaka
a921164f39 Do not treat atomic.load.sub differently than other atomic binary intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135418 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 19:58:59 +00:00
Akira Hatanaka
0d7d0b5cb7 Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from 
moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135415 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 18:52:12 +00:00
Owen Anderson
0af0dc8ac6 Re-apply r135319 with a fix for the constant island pass. 
Original Log: Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode.  Update the ARM disassembler for this change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135414 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 18:50:52 +00:00
Bruno Cardoso Lopes
3f6a8dd4ce Be more smart with VCVTSS2SD. Also place the patterns close to the 
definitions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135407 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 18:11:25 +00:00
Bruno Cardoso Lopes
3aaa010ece Add AVX 128-bit sqrt versions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135404 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 17:51:40 +00:00
Akira Hatanaka
45473c1b15 Change destination register operands of SC instructions so that unique 
virtual registers are used. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135403 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 17:44:27 +00:00
Frits van Bommel
39b5abf507 Migrate LLVM and Clang to use the new makeArrayRef(...) functions where previously explicit non-default constructors were used. 
Mostly mechanical with some manual reformatting.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135390 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 12:00:32 +00:00
Chris Lattner
db125cfaf5 land David Blaikie's patch to de-constify Type, with a few tweaks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135375 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 04:54:35 +00:00
Owen Anderson
91ddfc4723 Revert r135319 in an attempt to get to unbreak testers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135343 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-16 09:17:43 +00:00
Bruno Cardoso Lopes
4201ecae92 Add AVX 128-bit patterns for sint_to_fp 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135332 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-16 00:50:20 +00:00
Owen Anderson
49e163b6c7 Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode. Update the ARM disassembler for this change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135319 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 22:49:31 +00:00
Bruno Cardoso Lopes
5bc37dd131 Fix a couple of things: 
1) Make non-legal 256-bit loads to be promoted to v4i64. This lets us
canonize the loads and handle things the same way we use to handle
for 128-bit registers. Despite of what one of the removed comments
explained, the load promotion would not mess with VPERM, it's only a
matter of doing the appropriate bitcasts when this instructions comes
to be introduced. Also make LOAD v8i32 legal.

2) Doing 1) exposed two bugs:
- v4i64 was being promoted to itself for several opcodes (introduced
in r124447 by David Greene) causing endless recursion and the stack to
explode.
- there was no support for allOnes BUILD_VECTORs and ANDNP would fail to
match because it was generating early target constant pools during
lowering.

3) The testcases are already checked-in, doing 1) exposed the
bugs in the current testcases.

4) Tidy up code to be more clear and explicit about AVX.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135313 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 22:24:33 +00:00
Bruno Cardoso Lopes
983d19dd10 Add a few patterns for 256-bit bitcasts. No testcases now, they are 
comming together with other tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135312 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 22:24:17 +00:00
Eli Friedman
5232cc675c PR10370: Make sure we know how to relax push correctly on x86-64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135303 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 21:28:39 +00:00
Owen Anderson
43967a97cf Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135290 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 18:46:47 +00:00
Owen Anderson
167eb1f903 Remove unnecessary duplicate instruction definitions that simply overloaded the type of VEXT. This can be achieved with a Pat definition, and is much more disassembler friendly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135283 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 17:48:05 +00:00
NAKAMURA Takumi
20722b6cda Eliminate "const" from extern const to fix breakeage since r135184 on msvc. 
MSVC decorates (and distinguishes) "const" in mangler. It brought linkage error between "extern const" declarations and definitions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135269 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 12:50:21 +00:00
Chris Lattner
ef58218b8d remove the InvalidateStructLayoutInfo API, which is dead and unnecessary now 
that type refinement is toast.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135245 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 05:21:59 +00:00
Chandler Carruth
ed0e021643 Remove an unnecessary header from this file. I don't think this header 
was really intended, and it may have been required prior to some of the
recent refactors. Including it however causes LLVMX86Desc to need
symbols from LLVMX86CodeGen, forming a dependency cycle. This was masked
in almost all builds: Clang, and GCC w/ optimizations didn't actually
emit the symbols!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135242 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 04:16:38 +00:00
Evan Cheng
1be0e271a0 Move some parts of TargetAsmInfo down to MCAsmInfo. This is not the greatest 
solution but it is a small step towards removing the horror that is
TargetAsmInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135237 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 02:09:41 +00:00
Chandler Carruth
4afa2b842b Major update to CMake build to reflect changes in r135219 in the 
backend. Moved some MCAsmInfo files down into the MCTargetDesc
sublibraries, removed some (i suspect long) dead files from other parts
of the CMake build, etc. Also copied the include directory hack from the
Makefile.

Finally, updated the lib deps. I spot checked this, and think its
correct, but review appreciated there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135234 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 00:40:52 +00:00
Evan Cheng
1abf2cb59b Rename createAsmInfo to createMCAsmInfo and move registration code to MCTargetDesc to prepare for next round of changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135219 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 23:50:31 +00:00
Jim Grosbach
33c16a2737 ARM diagnostic when 's' suffix on mnemonic that can't set flags. 
For example, "mlss r0, r1, r2, r3".

The MLS instruction does not have a flag-setting variant.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135203 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 22:04:21 +00:00
Bill Wendling
13123d9463 * Redo the permutation encoding for frameless stacks to be more like what the 
unwind library expects.
* Comment the permutation encoding for frameless stacks.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135202 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 22:01:34 +00:00
Benjamin Kramer
151bd17a8f Add OperandTypes for Thumb branch targets. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135199 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 21:47:24 +00:00
Benjamin Kramer
3be41b748e Port operand types for ARM and X86 over from EDIS to the .td files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135198 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 21:47:22 +00:00
Jim Grosbach
c8ae39e746 ARM MCRR/MCRR2 immediate operand range checking. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135192 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 21:26:42 +00:00
Jim Grosbach
e540c7422c ARM MCR/MCR2 assembly parsing operand constraints. 
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 21:19:17 +00:00
Nicolas Geoffray
5cf9fcdad1 After type-system-rewrite branch update the Cpp backend to not use OpaqueType. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135186 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 21:04:35 +00:00
Evan Cheng
c60f9b7523 Next round of MC refactoring. This patch factor MC table instantiations, MC 
registeration and creation code into XXXMCDesc libraries.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 20:59:42 +00:00
Eric Christopher
5427edeb68 Check register class matching instead of width of type matching 
when determining validity of matching constraint. Allow i1
types access to the GR8 reg class for x86.

Fixes PR10352 and rdar://9777108

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135180 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 20:13:52 +00:00
Jim Grosbach
c83d504085 Reorganize ARM assembler aliases. 
Consolidate the individual declarations together for ease of reference. This
mirrors the organization in X86, as well, so is good for consistency. No
functional change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135179 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 19:47:47 +00:00
Bruno Cardoso Lopes
62f67f86fe Add 256-bit load/store recognition and matching in several places. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135171 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 18:50:58 +00:00
Benjamin Kramer
eac0796542 Don't leak operands when putting them into a shift. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135169 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 18:41:22 +00:00
Jim Grosbach
3b14a5c546 Update ARM Assembly of LDM/STM. 
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135168 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 18:35:38 +00:00
Jim Grosbach
9dec507ecb ARM ISB instruction assembly parsing. 
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135156 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 18:00:31 +00:00
Richard Osborne
c7e33965f0 Update XCoreRegisterInfo::eliminateFrameIndex() to handle DBG_VALUE 
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135146 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 14:03:48 +00:00
Nadav Rotem
d0f3ef807e [VECTOR-SELECT] 
During type legalization we often use the SIGN_EXTEND_INREG SDNode.
When this SDNode is legalized during the LegalizeVector phase, it is
scalarized because non-simple types are automatically marked to be expanded.
In this patch we add support for lowering SIGN_EXTEND_INREG manually.
This fixes CodeGen/X86/vec_sext.ll when running with the '-promote-elements'
flag.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135144 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 11:11:14 +00:00
Evan Cheng
672b93a332 Unfortunately several files in MC are badly violating layering rule by using 
TargetAsmInfo, which in turn pulls in TargetRegisterInfo, etc. :-( There are
other cases of violations, but this is probably the worst.

This patch is but one small step towards fixing this. 500 more steps to go. :-(


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135131 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 05:43:07 +00:00
Benjamin Kramer
3ff25514ce Don't emit a bit test if there is only one case the test can yield false. A simple SETNE is sufficient. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135126 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 01:38:42 +00:00
Eli Friedman
7e94501071 Fix up assertion in r135018 so it doesn't trigger on 32-bit; when we're in 32-bit, it doesn't matter whether the operation overflows because the computed address is not wider than the immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135120 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 00:22:31 +00:00
Jim Grosbach
e77494e3e3 ARM Assembler support for DSB instruction. 
Add instalias for default 'sy' option. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135116 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 00:18:13 +00:00
Jim Grosbach
77f379e2a1 DMB instalias needs the same predicate as the instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135112 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-14 00:10:26 +00:00
Jim Grosbach
032434d622 ARM Assembler support for DMB instruction. 
Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135109 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 23:40:38 +00:00
Jim Grosbach
20fcaffaf7 Update comments. These are for assembler, too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135107 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 23:33:10 +00:00
Owen Anderson
16884415db Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135106 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 23:22:26 +00:00
Bill Wendling
efe2a6557d Add code to handle a "frameless" unwind stack. 
The frameless unwind stack has a special encoding, the algorithm for which is in
"permuteEncode".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135103 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 23:03:31 +00:00
Jim Grosbach
6f9f884502 ARM Assembler support for DBG instruction. 
Add range checking and testing for parsing and encoding of DBG instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135102 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 22:59:38 +00:00
Jim Grosbach
1cbb0c16a1 Revert 135093. Think-o. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135094 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 22:06:11 +00:00
Jim Grosbach
91eb0aa5de Correct range for thumb co-processor immediate 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135093 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 22:03:11 +00:00
Jim Grosbach
83ab070fc1 Range checking for CDP[2] immediates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135092 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 22:01:08 +00:00
Bruno Cardoso Lopes
466b022c99 Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A more 
general version of X86ISD::ANDNP also opened the room for a little bit
of refactoring.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135088 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 21:36:51 +00:00
Bruno Cardoso Lopes
c1af4772f1 The target specific node PANDN name is misleading. That happens because 
it's later selected to a ANDNPD/ANDNPS instruction instead of the PANDN
instruction. Rename it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135087 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 21:36:47 +00:00
Jim Grosbach
e35c5e06fe Cleanup Thumb co-processor instructions a bit. 
Combine redundant base classes and such. No indended functional change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135085 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 21:35:10 +00:00
Eli Friedman
2a01946de4 Make sure we don't combine a large displacement and a frame index in the same addressing mode on x86-64. It can overflow, leading to a crash/miscompile. 
<rdar://problem/9763308>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135084 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 21:29:53 +00:00
Jim Grosbach
0d8dae292a Parameterize away the ARM T1Cop class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135082 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 21:17:59 +00:00
Jim Grosbach
9bb098ad3a Fix predicates for Thumb co-processor instructions. 
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135081 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 21:14:23 +00:00
Eli Friedman
4977eb5eb5 Refactor out checking for displacements on x86-64 addressing modes. No functionality change. Refactoring in preparation for an additional safety check in FoldOffsetIntoAddress. 
Part of <rdar://problem/9763308>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135079 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 20:44:23 +00:00
Jim Grosbach
898e7e26a5 Fix encoding for ARM BXJ instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135077 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 20:25:01 +00:00
Jim Grosbach
d447ac6c8c Fix encoding of predicate bits on ARM BX_pred. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135076 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 20:21:31 +00:00