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373 Commits

Author SHA1 Message Date
Akira Hatanaka
480eeb5431 Pass the correct call frame size to callseq_start node. This is needed to 
replace uses of function getMaxCallFrameSize defined in MipsFunctionInfo with
the one MachineFrameInfo has.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160841 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-26 23:27:01 +00:00
Akira Hatanaka
e11246c64e Fix call setup for PIC. 
Patch by Reed Kotler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160774 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-26 02:24:43 +00:00
Akira Hatanaka
3ee306cbc0 Add basic ability to setup call frame, and make procedure calls. 
Hello world will compile and execute with this patch.

Patch by Reed Kotler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160651 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-23 23:45:54 +00:00
Akira Hatanaka
fef904d0e8 Revert accidental commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160598 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-21 02:20:33 +00:00
Akira Hatanaka
b7dd9fc678 Add VK_Mips_HIGHER and VK_Mips_HIGHEST to MCSymbolRefExpr::VariantKind. 
Test case will be added later when long branch patch is checked in.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160597 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-21 02:15:19 +00:00
Akira Hatanaka
3fef29d881 Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160064 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-11 19:32:27 +00:00
Akira Hatanaka
ba584fe8fe Lower RETURNADDR node in Mips backend. 
Patch by Sasa Stankovic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160031 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-11 00:53:32 +00:00
Akira Hatanaka
182ef6fcaa Make register Mips::RA allocatable if not in mips16 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159971 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-10 00:19:06 +00:00
Jack Carter
10de025a67 mips32 long long register inline asm constraint support. 
inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed.    This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll)
    


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159625 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-02 23:35:23 +00:00
Eric Christopher
80c1b38eff Revert " mips32 long long register inline asm constraint support." as 
it appears to be breaking the bots.

This reverts commit 1b055ce320.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159619 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-02 23:22:25 +00:00
Jack Carter
1b055ce320 mips32 long long register inline asm constraint support. 
inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed.    This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll)
    


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159610 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-07-02 22:39:45 +00:00
Akira Hatanaka
864f66085c Fix coding style violations. Remove white spaces and tabs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158471 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-14 21:10:56 +00:00
Akira Hatanaka
8782707f50 Implement a DAGCombine in MipsISelLowering.cpp which transforms the following 
pattern:

(add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))

"tjt" is a TargetJumpTable node. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158419 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-13 20:33:18 +00:00
Akira Hatanaka
e193b32583 Set a higher value for maxStoresPerMemcpy in MipsISelLowering.cpp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158414 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-13 19:33:32 +00:00
Akira Hatanaka
2bd7e532b4 Simplify CreateLoadLR and CreateStoreLR in MipsISelLowering.cpp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158413 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-13 19:06:08 +00:00
Akira Hatanaka
777a120285 Implement fastcc calling convention for MIPS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158410 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-13 18:06:00 +00:00
Akira Hatanaka
94ccee2222 Fix a bug in MipsTargetLowering::LowerLOAD. A shift-right-logical node is 
inserted after the shift-left-logical node.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157937 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-04 17:46:29 +00:00
Hans Wennborg
70a07c7fc4 MIPS TLS: use the model selected by TargetMachine::getTLSModel(). 
This was mostly done already in r156162, but I missed one place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157929 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-04 14:02:08 +00:00
Chris Lattner
00edc3dea2 remove an unused variable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157872 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-02 01:03:42 +00:00
Akira Hatanaka
7664f05326 Set operation actions for load/store nodes in the Mips backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157866 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-02 00:04:42 +00:00
Akira Hatanaka
1cd0ec007a Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which 
custom-lower unaligned load and store nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157864 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-02 00:03:49 +00:00
Akira Hatanaka
b6f1dc2f09 Define Mips specific unaligned load/store nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157863 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-02 00:03:12 +00:00
Akira Hatanaka
f66b7b1ff6 Expand unaligned i16 loads/stores for the Mips backend. 
This is the first of a series of patches which make changes to the backend to
emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction
selection.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157862 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-06-02 00:02:45 +00:00
Akira Hatanaka
28ee4fdf20 Cleanup and factoring of mips16 tablegen classes. Make register classes 
CPU16RegsRegClass and CPURARegRegClass available. Add definition of mips16
jalr instruction.

Patch by Reed Kotler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157730 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-31 02:59:44 +00:00
Justin Holewinski
d2ea0e10cb Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall 
to pass around a struct instead of a large set of individual values.  This
cleans up the interface and allows more information to be added to the struct
for future targets without requiring changes to each and every target.

NV_CONTRIB

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157479 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-25 16:35:28 +00:00
Akira Hatanaka
92d4aec573 Make the following changes in MipsISelLowering.cpp: 
- Stop creating stack frame objects needed for saving $gp.
- Insert a node that copies the global pointer register to register $gp
  before the call node. This will ensure $gp is valid at the entry of the
  called function.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156692 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-12 03:19:04 +00:00
Akira Hatanaka
a284acb8a7 Expand 64-bit shifts if target ABI is O32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156457 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-09 00:55:21 +00:00
Eric Christopher
af97f73ca0 Add support for the 'x' constraint. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156295 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 06:25:19 +00:00
Eric Christopher
4adbefebd2 Add support for the 'l' constraint. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156294 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 06:25:15 +00:00
Eric Christopher
1d5a392e2c Add support for the 'c' constraint. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156293 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 06:25:10 +00:00
Eric Christopher
54412a789a Add support for the 'P' constraint. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156292 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 06:25:02 +00:00
Eric Christopher
1ce2034e43 Add support for the 'O' constraint. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156285 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 05:46:48 +00:00
Eric Christopher
60cfc7908e Add support for the 'N' inline asm constraint. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156284 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 05:46:43 +00:00
Eric Christopher
5ac47bba83 Add support for the 'L' inline asm constraint. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156283 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 05:46:37 +00:00
Eric Christopher
f49f846eec Add support for the inline asm constraint 'K'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156282 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 05:46:29 +00:00
Eric Christopher
e5076d484b Support the 'J' constraint. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156280 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 03:13:42 +00:00
Eric Christopher
50ab03954e Add support for the 'I' inline asm constraint. Also add tests 
from the previous 2 patches.

Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156279 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 03:13:32 +00:00
Eric Christopher
0ed1f764f4 Allow 64 bit integer values in gpu registers if arch and abi are 64 bit. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156278 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 03:13:22 +00:00
Eric Christopher
3ccbd47ecb When using inline asm constraints representing 
non-floating point general registers allow 8 and 16-bit
elements.

Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156277 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 03:13:16 +00:00
Hans Wennborg
fd5abd546e Make ARM and Mips use TargetMachine::getTLSModel() 
This moves the logic for selecting a TLS model to a single place,
instead of the previous three (ARM, Mips, and X86 which already
uses this function).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156162 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 09:40:39 +00:00
NAKAMURA Takumi
8959393533 llvm/lib/Target: [PR12611] Add "llvm/Support/raw_ostream.h" for Debug build on MSVC. 
Thanks to Andy Gibbs, to report the issue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155287 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-21 15:31:45 +00:00
Craig Topper
420761a0f1 Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-20 07:30:17 +00:00
Akira Hatanaka
1cc6333161 Emit neg.s or neg.d only if -enable-no-nans-fp-math is supplied by user, 
otherwise expand FNEG during legalization.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154546 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 22:59:08 +00:00
Akira Hatanaka
c12a6e6b53 Emit abs.s or abs.d only if -enable-no-nans-fp-math is supplied by user. 
Invalid operation is signaled if the operand of these instructions is NaN.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154545 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 22:49:04 +00:00
Akira Hatanaka
056c51e598 Fix bugs in lowering of FCOPYSIGN nodes. 
- FCOPYSIGN nodes that have operands of different types were not handled.
- Different code was generated depending on the endianness of the target.

Additionally, code is added that emits INS and EXT instructions, if they are
supported by target (they are R2 instructions).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154540 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-11 22:13:04 +00:00
Akira Hatanaka
56ce6b3520 Reapply 154038 without the failing test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154062 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-04 22:16:36 +00:00
Owen Anderson
657a4e774c Revert r154038. It was causing make check failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154054 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-04 21:18:58 +00:00
Akira Hatanaka
e825fb3888 Fix LowerGlobalAddress to produce instructions with the correct relocation 
types for N32 ABI. Add new test case and update existing ones.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154038 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-04 19:02:38 +00:00
Akira Hatanaka
c75ceb7809 Fix LowerJumpTable to produce instructions with the correct relocation 
types for N32 ABI. Test case will be updated after the patch that fixes
TargetLowering::getPICJumpTableRelocBase is checked in.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154036 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-04 18:31:32 +00:00
Akira Hatanaka
86a2733055 Fix LowerConstantPool to produce instructions with the correct relocation 
types for N32 ABI and update test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154034 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-04 18:26:12 +00:00