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ca8a2aa921
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4940 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
ca8a2aa921 Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127027 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 20:01:52 +00:00
Devang Patel
c8888c7d80 XFAIL for all. These tests are darwin specific anyway. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127022 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 19:38:10 +00:00
Devang Patel
53dc40a45f Disable ARMGlobalMerge on darwin. The debugger is not yet able to extract individual variable's info from merged global. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127019 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 19:11:05 +00:00
Kalle Raiskila
31cbac1cfe Allow vector shifts (shl,lshr,ashr) on SPU. 
There was a previous implementation with patterns that would 
have matched e.g. 
	shl <v4i32> <i32>,
but this is not valid LLVM IR so they never were selected.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126998 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 13:19:18 +00:00
Kalle Raiskila
7f5de8b4c6 Allow load from constant on SPU. 
A 'load <4 x i32>* null' crashes llc before this fix.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126995 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-04 12:00:11 +00:00
Eli Friedman
81c5ef8649 Revert r123908; the code in question is completely untested and wrong. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126964 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 22:33:23 +00:00
Joerg Sonnenberger
ea83b13350 Bug#9033: For the ELF assembler output, always quote the section name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126963 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-03 22:31:08 +00:00
Stuart Hastings
44456e86c8 Test case for r126864. Radar 9056407. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126900 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 23:41:40 +00:00
David Greene
a20244d1ba [AVX] Fix mask predicates for 256-bit UNPCKLPS/D and implement 
missing patterns for them.

      Add a SIMD test subdirectory to hold tests for SIMD instruction
      selection correctness and quality.
'


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126845 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 17:23:43 +00:00
Cameron Zwarich
56e3793acf Eliminate the unused CodeGenPrepare option to split critical edges. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126825 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 03:31:46 +00:00
Che-Liang Chiou
fd8978b021 Extend initial support for primitive types in PTX backend 
- Allow i16, i32, i64, float, and double types, using the native .u16,
  .u32, .u64, .f32, and .f64 PTX types.
- Allow loading/storing of all primitive types.
- Allow primitive types to be passed as parameters.
- Allow selection of PTX Version and Shader Model as sub-target attributes.
- Merge integer/floating-point test cases for load/store.
- Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler.

Patch by Justin Holewinski



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126824 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 03:20:28 +00:00
Dan Gohman
0cbe91ba3b Don't re-use existing addrec expansions if they contain casts. 
This fixes PR9259.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126812 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 01:34:10 +00:00
Evan Cheng
f06e6c2ba7 Catch more cases where 2-address pass should 3-addressify instructions. rdar://9002648. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126811 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-02 01:08:17 +00:00
Bill Wendling
a656b63ee4 Narrow right shifts need to encode their immediates differently from a normal 
shift.

   16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
   32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
   64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126723 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-03-01 01:00:59 +00:00
Jakob Stoklund Olesen
bafd516d3e Fix typo introduced by r126661: "Fix a typo which ..." 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126666 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 19:18:59 +00:00
Evan Cheng
c24ab5c654 Fix a typo which cause dag combine crash. rdar://9059537. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126661 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 18:45:27 +00:00
Duncan Sands
377ffe3b11 Windows codegen also dies on this, so restrict to the platform it was 
actually tested on.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126652 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 14:22:08 +00:00
Duncan Sands
443612e165 Make this test x86 specific because the ARM backend can't handle it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126650 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 12:30:47 +00:00
Che-Liang Chiou
f71720231f Add preliminary support for .f32 in the PTX backend. 
- Add appropriate TableGen patterns for fadd, fsub, fmul.
- Add .f32 as the PTX type for the LLVM float type.
- Allow parameters, return values, and global variable declarations
  to accept the float type.
- Add appropriate test cases.

Patch by Justin Holewinski



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126636 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-28 06:34:09 +00:00
Duncan Sands
9c45251e11 Legalize support for fpextend of vector. PR9309. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126574 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-27 14:41:27 +00:00
NAKAMURA Takumi
419f232783 Target/X86: Always emit "push/pop GPRs" in prologue/epilogue and emit "spill/reload frames" for XMMs. 
It improves Win64's prologue/epilogue but it would not affect ia32 and amd64 (lack of nonvolatile XMMs).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126568 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-27 08:47:19 +00:00
Cameron Zwarich
eee444cc4e Fix PR9324 / <rdar://problem/9052489> by handling the case where a PHI has no uses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126567 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-27 08:06:01 +00:00
Cameron Zwarich
60c8b22dad Give a test file a more sensible name so that it can hold more test cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126566 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-27 08:05:57 +00:00
Benjamin Kramer
7466678003 Add some DAGCombines for (adde 0, 0, glue), which are useful to optimize legalized code for large integer arithmetic. 
1. Inform users of ADDEs with two 0 operands that it never sets carry
2. Fold other ADDs or ADDCs into the ADDE if possible

It would be neat if we could do the same thing for SETCC+ADD eventually, but we can't do that in target independent code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126557 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-26 22:48:07 +00:00
Bob Wilson
da52506792 Add patterns to use post-increment addressing for Neon VST1-lane instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126477 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-25 06:42:42 +00:00
Nadav Rotem
8c20ec54d9 Enable support for vector sext and trunc: 
Limit the folding of any_ext and sext  into the load operation to scalars.
Limit the active-bits trunc optimization to scalars.
Document vector trunc and vector sext in LangRef.

Similar to commit 126080 (for enabling zext).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126424 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-24 21:01:34 +00:00
Devang Patel
3fe3424a21 Move arch specific tests in arch specific directories. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126401 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-24 19:06:27 +00:00
Richard Osborne
21d7eb3f3b Add XCore intrinsic for eeu instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126384 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-24 13:39:18 +00:00
Cameron Zwarich
8ca814c4e0 Merge information about the number of zero, one, and sign bits of live-out 
registers at phis. This enables us to eliminate a lot of pointless zexts during
the DAGCombine phase. This fixes <rdar://problem/8760114>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126380 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-24 10:00:25 +00:00
Evan Cheng
7558e2e415 Fix bug in X86 folding / unfolding table. Int_CMPSDrm and Int_CMPSSrm memory 
operands starts at index 2, not 1.
rdar://9045024
PR9305


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126359 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-24 02:36:52 +00:00
Devang Patel
3a4ae32ed7 Use DW_FORM_data2 for DW_AT_language and let users use DW_LANG_lo_user=0x8000 to DW_LANG_hi_user=0xffff range. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126339 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-23 22:37:04 +00:00
Devang Patel
1d6b2c74c0 Check only relevant strings in output to increase stability of the tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126338 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-23 22:35:57 +00:00
Richard Osborne
d04b4937d1 Add XCore intrinsic for clre instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126322 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-23 18:52:05 +00:00
Richard Osborne
9935bd0819 Add llvm.xcore.waitevent intrinsic. The effect of this intrinsic is to enable 
events on the thread and wait until a resource is ready to event. The vector
of the resource that is ready is returned.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126320 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-23 18:35:59 +00:00
Richard Osborne
292f62e06f Add XCore intrinsic for the setv instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126315 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-23 16:46:37 +00:00
Richard Osborne
2a2cb28526 Add XCore intrinsic for settw instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126313 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-23 14:45:03 +00:00
Evan Cheng
e573fb3255 More fcopysign correctness and performance fix. 
The previous codegen for the slow path (when values are in VFP / NEON
registers) was incorrect if the source is NaN.

The new codegen uses NEON vbsl instruction to copy the sign bit. e.g.
        vmov.i32        d1, #0x80000000
        vbsl    d1, d2, d0
If NEON is not available, it uses integer instructions to copy the sign bit.
rdar://9034702


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126295 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-23 02:24:55 +00:00
NAKAMURA Takumi
6023efb45d Revert r126195, "test/CodeGen/X86/vec_cast.ll: Mark as XFAIL: migw,win32 for workaround of PR8311." 
It seems it affected configuration --target=i686-pc-mingw32, I don't know and will investigate why.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126217 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-22 08:22:54 +00:00
NAKAMURA Takumi
0de102b9d8 Relax expressions and add explicit triplets -linux and -win32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126216 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-22 07:21:59 +00:00
NAKAMURA Takumi
65e9404646 Relax expressions and add explicit triplets -linux and -win32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126215 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-22 07:21:51 +00:00
NAKAMURA Takumi
3f38d20f95 Relax expressions and add explicit triplets -linux and -win32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126214 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-22 07:21:42 +00:00
NAKAMURA Takumi
aef8871177 Relax expressions and add explicit triplets -linux and -win32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126213 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-22 07:21:33 +00:00
NAKAMURA Takumi
88234f14a8 Relax expressions and add explicit triplets -linux and -win32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126212 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-22 07:21:25 +00:00
NAKAMURA Takumi
902f128141 Relax expressions and add explicit triplets -linux and -win32. 
On @foobar(double %d, double* %x),
AMD64: (%xmm0, %rdi)
Win64: (%xmm0, %rdx) (not %rcx!)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126211 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-22 07:21:17 +00:00
NAKAMURA Takumi
166b79fb24 Relax expressions and add explicit triplets -linux and -win32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126210 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-22 07:21:08 +00:00
NAKAMURA Takumi
661cae4b58 Relax expressions and add explicit triplets -linux and -win32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126209 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-22 07:21:01 +00:00
NAKAMURA Takumi
db2649995d Relax expressions and add explicit triplets -linux and -win32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126208 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-22 07:20:52 +00:00
NAKAMURA Takumi
20cee65fd1 Relax expressions and add explicit triplets -linux and -win32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126207 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-22 07:20:44 +00:00
NAKAMURA Takumi
5731b5c8ce Relax expressions and add explicit triplets -linux and -win32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126206 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-22 07:20:35 +00:00
NAKAMURA Takumi
22bc92baa4 Relax expressions and add explicit triplets -linux and -win32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126205 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-02-22 07:20:26 +00:00