Commit Graph

723 Commits

Author SHA1 Message Date
Duncan Sands
cdd4f8c7cb Correct bogus module triple specifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112469 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30 10:48:29 +00:00
Bob Wilson
04d6c289ab Remove NEON vaddl, vaddw, vsubl, and vsubw intrinsics. Instead, use llvm
IR add/sub operations with one or both operands sign- or zero-extended.
Auto-upgrade the old intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112416 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29 05:57:34 +00:00
Bob Wilson
d4bfd54ec2 Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like
all the other LDM/STM instructions.  This fixes asm printer crashes when
compiling with -O0.  I've changed one of the NEON tests (vst3.ll) to run
with -O0 to check this in the future.

Prior to this change VLDM/VSTM used addressing mode #5, but not really.
The offset field was used to hold a count of the number of registers being
loaded or stored, and the AM5 opcode field was expanded to specify the IA
or DB mode, instead of the standard ADD/SUB specifier.  Much of the backend
was not aware of these special cases.  The crashes occured when rewriting
a frameindex caused the AM5 offset field to be changed so that it did not
have a valid submode.  I don't know exactly what changed to expose this now.
Maybe we've never done much with -O0 and NEON.  Regardless, there's no longer
any reason to keep a count of the VLDM/VSTM registers, so we can use
addressing mode #4 and clean things up in a lot of places.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112322 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27 23:18:17 +00:00
Bob Wilson
7a9ef44b3b Add alignment arguments to all the NEON load/store intrinsics.
Update all the tests using those intrinsics and add support for
auto-upgrading bitcode files with the old versions of the intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112271 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27 17:13:24 +00:00
Bob Wilson
2ac124c561 Revert svn 107892 (with changes to work with trunk). It caused a crash if
a VLD result was not used (Radar 8355607).  It should also fix pr7988, but
I haven't verified that yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112118 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26 00:13:36 +00:00
Eric Christopher
c430223677 Add another basic test cribbed from the x86 fast-isel tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112036 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25 07:57:29 +00:00
Eric Christopher
e8d274c8c9 Run this on thumb and arm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112035 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25 07:53:15 +00:00
Eric Christopher
dc3d8b812f Make this testcase actually executed with fast-isel on arm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112033 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25 07:47:00 +00:00
Bob Wilson
d58b51e67c Replace some NEON vmovl intrinsic that I missed earlier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111696 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-20 23:22:43 +00:00
Bob Wilson
b31a11b466 Replace the arm.neon.vmovls and vmovlu intrinsics with vector sign-extend and
zero-extend operations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111614 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-20 04:54:02 +00:00
Dan Gohman
4bb4641784 When sending stats output to stdout for grepping, don't emit normal
output to standard output also.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18 22:22:44 +00:00
Bob Wilson
2003bcfbd2 Expand ZERO_EXTEND operations for NEON vector types.
Testcase from Nick Lewycky.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111341 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18 01:45:52 +00:00
Bob Wilson
f955f290c9 Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid
printing "lsl #0".  This fixes the remaining parts of pr7792.  Make
corresponding changes for encoding/decoding these instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111251 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 17:23:19 +00:00
Bob Wilson
7aaf5bf3db Allow more cases of undef shuffle indices and add tests for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111226 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 05:54:34 +00:00
Evan Cheng
97b9b97853 PHI elimination should not break back edge. It can cause some significant code placement issues. rdar://8263994
good:
LBB0_2:
  mov     r2, r0
  . . .
  mov     r1, r2
  bne     LBB0_2

bad:
LBB0_2:
  mov     r2, r0
  . . .
@ BB#3:
  mov     r1, r2
  b       LBB0_2


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111221 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17 01:20:36 +00:00
Bob Wilson
8f58a2e8e1 Add a testcase for svn 111208.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111212 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-16 23:44:29 +00:00
Bob Wilson
dc66edaced Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee
that the high halfword is zero.  The shift need not be exactly 16 bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111196 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-16 22:26:55 +00:00
Bob Wilson
e269ead8c6 Convert a test to use FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111153 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-16 17:05:27 +00:00
Bob Wilson
703af3ab12 Temporarily disable tail calls on ARM to work around some linker problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111050 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-13 22:43:33 +00:00
Bill Wendling
de2b151dbf Consider this code snippet:
float t1(int argc) {
  return (argc == 1123) ? 1.234f : 2.38213f;
}

We would generate truly awful code on ARM (those with a weak stomach should look
away):

_t1:
  movw   r1, #1123
  movs   r2, #1
  movs   r3, #0
  cmp    r0, r1
  mov.w  r0, #0
  it     eq
  moveq  r0, r2
  movs   r1, #4
  cmp    r0, #0
  it     ne
  movne  r3, r1
  adr    r0, #LCPI1_0
  ldr    r0, [r0, r3]
  bx     lr

The problem was that legalization was creating a cascade of SELECT_CC nodes, for
for the comparison of "argc == 1123" which was fed into a SELECT node for the ?:
statement which was itself converted to a SELECT_CC node. This is because the
ARM back-end doesn't have custom lowering for SELECT nodes, so it used the
default "Expand".

I added a fairly simple "LowerSELECT" to the ARM back-end. It takes care of this
testcase, but can obviously be expanded to include more cases.

Now we generate this, which looks optimal to me:

_t1:
  movw   r1, #1123
  movs   r2, #0
  cmp    r0, r1
  adr    r0, #LCPI0_0
  it     eq
  moveq  r2, #4
  ldr    r0, [r0, r2]
  bx     lr
  .align  2
LCPI0_0:
  .long   1075344593  @ float 2.382130e+00
  .long   1067316150  @ float 1.234000e+00



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110799 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 08:43:16 +00:00
Evan Cheng
7b4d31176e Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110798 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 07:17:46 +00:00
Bill Wendling
d771041828 Update test to match output of optimize compares for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110765 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11 01:05:02 +00:00
Bill Wendling
bb47d3b471 The optimize comparisons pass removes the "cmp" instruction this is checking for.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110739 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10 22:16:05 +00:00
Rafael Espindola
55e9587469 Fix eabi calling convention when a 64 bit value shadows r3.
Without this what was happening was:

* R3 is not marked as "used"
* ARM backend thinks it has to save it to the stack because of vaarg
* Offset computation correctly ignores it
* Offsets are wrong

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110446 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06 15:35:32 +00:00
Bill Wendling
547b6ed16e Testcase for r110248.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110249 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-04 21:56:30 +00:00
Bob Wilson
67b453b0d1 Combine NEON VABD (absolute difference) intrinsics with ADDs to make VABA
(absolute difference with accumulate) intrinsics.  Radar 8228576.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110170 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-04 00:12:08 +00:00
Anton Korobeynikov
b5a0ef99f8 Currently EH lowering code expects typeinfo to be global only.
This assumption is not satisfied due to global mergeing.
Workaround the issue by temporary disablinge mergeing of const globals.
Also, ignore LLVM "special" globals. This fixes PR7716

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109423 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-26 18:45:39 +00:00
Evan Cheng
3144687df7 - Allow target to specify when is register pressure "too high". In most cases,
it's too late to start backing off aggressive latency scheduling when most
  of the registers are in use so the threshold should be a bit tighter.
- Correctly handle live out's and extract_subreg etc.
- Enable register pressure aware scheduling by default for hybrid scheduler.
  For ARM, this is almost always a win on # of instructions. It's runtime
  neutral for most of the tests. But for some kernels with high register
  pressure it can be a huge win. e.g. 464.h264ref reduced number of spills by
  54 and sped up by 20%.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109279 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 22:39:59 +00:00
Evan Cheng
4a863e2c75 More register pressure aware scheduling work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 23:53:58 +00:00
Eric Christopher
ab695889c6 Baby steps towards ARM fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109047 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 22:26:11 +00:00
Rafael Espindola
bc56501435 Fix calling convention on ARM if vfp2+ is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109009 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 11:38:30 +00:00
Jim Grosbach
5423856e44 Add combiner patterns to more effectively utilize the BFI (bitfield insert)
instruction for non-constant operands. This includes the case referenced
in the README.txt regarding a bitfield copy.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108608 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-17 03:30:54 +00:00
Jim Grosbach
469bbdb597 Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction
and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16 23:05:05 +00:00
Evan Cheng
60108e96bb Split -enable-finite-only-fp-math to two options:
-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108465 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-15 22:07:12 +00:00
Jim Grosbach
502e0aa628 Improve 64-subtraction of immediates when parts of the immediate can fit
in the literal field of an instruction. E.g.,
long long foo(long long a) {
  return a - 734439407618LL;
}

rdar://7038284



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108339 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 17:45:16 +00:00
Bob Wilson
7e3f0d2690 Add support for NEON VMVN immediate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108324 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 06:31:50 +00:00
Bob Wilson
9e82bf12a0 Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes.
Radar 7373643.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108303 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14 01:22:12 +00:00
Bob Wilson
cba270d042 Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to represent
NEON VMOV-immediate instructions.  This simplifies some things.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108275 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 21:16:48 +00:00
Evan Cheng
218977b53e Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108258 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13 19:27:42 +00:00
Rafael Espindola
cbeeae23c3 Fix va_arg for doubles. With this patch VAARG nodes always contain the
correct alignment information, which simplifies ExpandRes_VAARG a bit.

The patch introduces a new alignment information to TargetLoweringInfo. This is
needed since the two natural candidates cannot be used:

* The 's' in target data: If this is set to the minimal alignment of any
  argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for
  example.
* The getTransientStackAlignment method. It is possible for an architecture to
  have argument less aligned than what we maintain the stack pointer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108072 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 04:01:49 +00:00
Jim Grosbach
6c7d3a16b3 In the presence of variable sized objects, allocate an emergency spill slot.
rdar://8131327

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108008 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 20:27:06 +00:00
Jakob Stoklund Olesen
cfcb2f6898 Fix test to be less sensitive of regalloc accidents
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107951 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 01:32:11 +00:00
Bob Wilson
a0148c360e Print "dregpair" NEON operands with a space between them, for readability and
consistency with other instructions that have lists of register operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107944 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:47:20 +00:00
Bob Wilson
f1d93ca920 Reenable DAG combining for vector shuffles. It looks like it was temporarily
disabled and then never turned back on again.  Adjust some tests, one because
this change avoids an unnecessary instruction, and the other to make it
continue testing what it was intended to test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:38:12 +00:00
Evan Cheng
5d115a0ff9 Check for FiniteOnlyFPMath as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107904 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 20:12:24 +00:00
Evan Cheng
4ff7ab612c r107852 is only safe with -enable-unsafe-fp-math to account for +0.0 == -0.0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107856 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 06:01:49 +00:00
Evan Cheng
515fe3a588 Optimize some vfp comparisons to integer ones. This patch implements the simplest case when the following conditions are met:
1. The arguments are f32.
2. The arguments are loads and they have no uses other than the comparison.
3. The comparison code is EQ or NE.

e.g.
        vldr.32 s0, [r1]
        vldr.32 s1, [r0]
        vcmpe.f32       s1, s0
        vmrs    apsr_nzcv, fpscr
	beq     LBB0_2
=>
        ldr     r1, [r1]
        ldr     r0, [r0]
        cmp     r0, r1
        beq     LBB0_2

More complicated cases will be implemented in subsequent patches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107852 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 02:08:50 +00:00
Dale Johannesen
7835f1fcdb Changes to ARM tail calls, mostly cosmetic.
Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107851 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 01:18:23 +00:00
Rafael Espindola
a5e82a5748 Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion
if profitable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107673 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 16:24:34 +00:00
Bob Wilson
e45f72c833 Fix incorrect asm-printing of some NEON immediates. Fix weak testcase so
that it checks the immediate values, not just the instructions opcodes.
Radar 8110263.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107487 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02 17:23:44 +00:00