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Author SHA1 Message Date
Nate Begeman a0df5d8da5 Remove operand type 'crbit', since it is no longer used 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23106 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-26 22:04:17 +00:00
Nate Begeman 60675f7562 Remove some code made dead by the fsel patch 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23085 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-26 17:45:06 +00:00
Nate Begeman 6718f11feb Fix JIT encoding of conditional branches 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23076 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-26 04:11:42 +00:00
Nate Begeman bb22df31d9 SUBFIC produces two results, not one. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23073 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-26 00:34:06 +00:00
Nate Begeman 6660cd65cf Implement SHL_PARTS and SRL_PARTS 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23072 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-26 00:28:00 +00:00
Nate Begeman 1999b4b974 New fold for SELECT_CC 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23058 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-25 20:04:38 +00:00
Nate Begeman c8e27db5c5 Remove option to make SetCC illegal on PowerPC after long discussion with 
Chris.  This will be accomplished through correctly modeling CR's and
subregs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23056 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-25 20:01:10 +00:00
Nate Begeman 6ef4949a0b Whoops, fix a thinko. All cases except SETNE are now handled by the 
target independent code in SelectionDAG.cpp


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23002 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-24 05:06:48 +00:00
Nate Begeman c6b0717a6c Remove unused statistic 
Prefer 'neg X' to 'subfic 0, X' since neg does not set XER[CA]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23001 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-24 05:03:20 +00:00
Nate Begeman 4b46fc094d Add the "ppc specific" setcc-equivalent select_cc cases 
Prefer 'neg X' to 'subfic 0, X' since it does not set XER[CA]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23000 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-24 04:59:21 +00:00
Nate Begeman cebd433d8d Teach SelectionDAG how to simplify a few more setcc-equivalent select_cc 
nodes so that backends don't have to.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22999 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-24 04:57:57 +00:00
Nate Begeman 0750a40a4f Fix optimization of select_cc seteq X, 0, 1, 0 -> srl (ctlz X), log2 X size 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22995 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-24 00:21:28 +00:00
Nate Begeman 8ca5693c51 Ack, typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22981 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-23 05:45:10 +00:00
Nate Begeman a50d53e5ef Add an option to make SetCC illegal as a beta option 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22979 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-23 05:42:36 +00:00
Nate Begeman 7042f15bde Teach the SelectionDAG how to transform select_cc eq, X, 0, 1, 0 into 
either seteq X, 0 or srl (ctlz X), size(X-1), depending on what's legal
for the target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22978 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-23 05:41:12 +00:00
Nate Begeman b942a3dd5f Teach Legalize how to turn setcc into select_cc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22977 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-23 04:29:48 +00:00
Nate Begeman 354df0ae6d Remove some instructions we no longer generate 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22976 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-23 01:16:46 +00:00
Nate Begeman 27d53ba6dd Fix a bug where we were passing the wrong number of arguments to an 
instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22901 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 03:42:28 +00:00
Nate Begeman 5ce0d308e6 Add support for target nodes with more than 3 operands, required by ppc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22894 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 00:56:28 +00:00
Nate Begeman 02b88a4586 ISD::OR, and it's accompanying SelectBitfieldInsert 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22889 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 00:38:14 +00:00
Nate Begeman 73bfa71524 Remove the X86 and PowerPC Simple instruction selectors; their time has 
passed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22886 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 23:53:15 +00:00
Nate Begeman c15ed447f4 Add shifts. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22884 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 23:38:00 +00:00
Nate Begeman 58dfb08319 Fix int foo() { return 65535; } by using the top 16 bits of the constant 
as the argument to LIS rather than the result of HA16(constant).

The DAG->DAG ISel was already doing the right thing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22865 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 18:14:49 +00:00
Nate Begeman a694047813 Improve ISD::Constant codegen. 
Now for int foo() { return -1; } we generate:
_foo:
        li r3, -1
        blr

instead of
_foo:
        lis r2, -1
        ori r3, r2, 65535
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22864 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 18:01:39 +00:00
Nate Begeman cffc32b6e2 Add support for ISD::AND, and its various optimized forms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22857 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 07:30:46 +00:00
Nate Begeman 294a0a103d Add support for target DAG nodes that take 4 operands, such as PowerPC's 
rlwinm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22856 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 07:30:15 +00:00
Nate Begeman 131a880520 Maintain consistency in negating things 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22855 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 05:44:50 +00:00
Nate Begeman 0f3257a330 Implement XOR, remove a broken sign_extend_inreg case 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22854 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 05:00:13 +00:00
Nate Begeman 43c3c70b10 Add a testcase for load short -> uint, which is currently emitted as a 
zextload + sign_extend_inreg rather than a sextload.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22852 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 03:11:44 +00:00
Nate Begeman 305a1c75cf Add a bunch more simple nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22851 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 03:04:18 +00:00
Nate Begeman 6a7d61179c Add a couple more nodes that are easy to handle 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22850 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 00:53:47 +00:00
Nate Begeman b5a0668d43 Be fruitful and multiply! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22849 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 00:21:41 +00:00
Nate Begeman 26653500bb Teach the DAG->DAG ISel about FNEG, and how it can be used to invert 
several of the PowerPC opcodes that come in both negated and non-negated
forms.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22845 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-17 23:46:35 +00:00
Nate Begeman 0f66a91721 Add two new methods isTargetOpcode() which returns true if the node type 
is greater than the range of building selection dag node types, and
getTargetOpcode(), which returns the node opcode less the value of
isd::builtin_op_end, which specifies the end of the builtin types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22844 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-17 23:44:54 +00:00
Nate Begeman 456f1e890c Implement a couple improvements: 
Remove dead code in ISD::Constant handling
Add support for add long, imm16

We now codegen 'long long foo(long long a) { return ++a; }'
as:
addic r4, r4, 1
addze r3, r3
blr

instead of:
li r2, 1
li r5, 0
addc r2, r4, r2
adde r3, r3, r5
blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22811 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-17 00:20:08 +00:00
Nate Begeman 7cbd525ba8 Implement BR_CC and BRTWOWAY_CC. This allows the removal of a rather nasty 
fixme from the PowerPC backend.  Emit slightly better code for legalizing
select_cc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22805 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-16 19:49:35 +00:00
Nate Begeman 2d56e72f09 Fix last night's PPC32 regressions by 
1. Not selecting the false value of a select_cc in the false arm, which
   isn't legal for nested selects.
2. Actually returning the node we created and Legalized in the FP_TO_UINT
   Expander.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22789 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-14 18:38:32 +00:00
Nate Begeman 889f2c1acf Fix last night's X86 regressions by putting code for SSE in the if(SSE) 
block.  nur.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22788 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-14 18:37:02 +00:00
Nate Begeman 875f360e22 Fix FP_TO_UINT with Scalar SSE2 now that the legalizer can handle it. We 
now generate the relatively good code sequences:
unsigned short foo(float a) { return a; }
_foo:
        movss 4(%esp), %xmm0
        cvttss2si %xmm0, %eax
        movzwl %ax, %eax
        ret

and
unsigned bar(float a) { return a; }
_bar:
        movss .CPI_bar_0, %xmm0
        movss 4(%esp), %xmm1
        movapd %xmm1, %xmm2
        subss %xmm0, %xmm2
        cvttss2si %xmm2, %eax
        xorl $-2147483648, %eax
        cvttss2si %xmm1, %ecx
        ucomiss %xmm0, %xmm1
        cmovb %ecx, %eax
        ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22786 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-14 04:36:51 +00:00
Nate Begeman d2558e3e4a Teach the legalizer how to legalize FP_TO_UINT. 
Teach the legalizer to promote FP_TO_UINT to FP_TO_SINT if the wider
  FP_TO_UINT is also illegal.  This allows us on PPC to codegen
  unsigned short foo(float a) { return a; }

as:
_foo:
.LBB_foo_0:     ; entry
        fctiwz f0, f1
        stfd f0, -8(r1)
        lwz r2, -4(r1)
        rlwinm r3, r2, 0, 16, 31
        blr

instead of:
_foo:
.LBB_foo_0:     ; entry
        fctiwz f0, f1
        stfd f0, -8(r1)
        lwz r2, -4(r1)
        lis r3, ha16(.CPI_foo_0)
        lfs f0, lo16(.CPI_foo_0)(r3)
        fcmpu cr0, f1, f0
        blt .LBB_foo_2  ; entry
.LBB_foo_1:     ; entry
        fsubs f0, f1, f0
        fctiwz f0, f0
        stfd f0, -16(r1)
        lwz r2, -12(r1)
        xoris r2, r2, 32768
.LBB_foo_2:     ; entry
        rlwinm r3, r2, 0, 16, 31
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22785 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-14 01:20:53 +00:00
Nate Begeman 5a01481585 Make FP_TO_UINT Illegal. This allows us to generate significantly better 
codegen for FP_TO_UINT by using the legalizer's SELECT variant.

Implement a codegen improvement for SELECT_CC, selecting the false node in
the MBB that feeds the phi node.  This allows us to codegen:
void foo(int *a, int b, int c) { int d = (a < b) ? 5 : 9; *a = d; }
as:
_foo:
        li r2, 5
        cmpw cr0, r4, r3
        bgt .LBB_foo_2  ; entry
.LBB_foo_1:     ; entry
        li r2, 9
.LBB_foo_2:     ; entry
        stw r2, 0(r3)
        blr

insted of:
_foo:
        li r2, 5
        li r5, 9
        cmpw cr0, r4, r3
        bgt .LBB_foo_2  ; entry
.LBB_foo_1:     ; entry
        or r2, r5, r5
.LBB_foo_2:     ; entry
        stw r2, 0(r3)
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22784 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-14 01:17:16 +00:00
Nate Begeman ff66368a5f Remove an unncessary argument to SimplifySelectCC and add an additional 
assert when creating a select_cc node.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22780 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-13 06:14:17 +00:00
Nate Begeman 32c392a3a5 Fix the fabs regression on x86 by abstracting the select_cc optimization 
out into SimplifySelectCC.  This allows both ISD::SELECT and ISD::SELECT_CC
to use the same set of simplifying folds.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22779 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-13 06:00:21 +00:00
Nate Begeman 8f331325a2 Remove support for 64b PPC, it's been broken for a long time. It'll be 
back once a DAG->DAG ISel exists.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22778 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-13 05:59:16 +00:00
Nate Begeman e1fae4a3ae Add a select_cc optimization for recognizing abs(int). This speeds up an 
integer MPEG encoding loop by a factor of two.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22758 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-11 02:18:13 +00:00
Nate Begeman e5d63829fd Some SELECT_CC cleanups: 
1. move assertions for node creation to getNode()
2. legalize the values returned in ExpandOp immediately
3. Move select_cc optimizations from SELECT's getNode() to SELECT_CC's,
   allowing them to be cleaned up significantly.

This paves the way to pick up additional optimizations on SELECT_CC, such
as sum-of-absolute-differences.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22757 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-11 01:12:20 +00:00
Nate Begeman c24d484b78 Make SELECT illegal on PPC32, switch to using SELECT_CC, which more closely 
reflects what the hardware is capable of.  This significantly simplifies
the CC handling logic throughout the ISel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22756 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-10 20:52:09 +00:00
Nate Begeman 9373a81e53 Add new node, SELECT_CC. This node is for targets that don't natively 
implement SELECT.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22755 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-10 20:51:12 +00:00
Nate Begeman d3ded2d8a7 Factor out some common code, and be smarter about when to emit load hi/lo 
code sequences.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22719 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-08 22:22:56 +00:00
Nate Begeman 394cd13ba3 Fix JIT encoding of ppc mfocrf instruction; the operands were reversed 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22707 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-08 20:04:52 +00:00
Nate Begeman c523f4c096 Add an extra parameter that Chris requested 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22665 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-04 23:50:43 +00:00
Nate Begeman a83ba0f5c9 Fix a fixme in CondPropagate.cpp by moving a PhiNode optimization into 
BasicBlock's removePredecessor routine.  This requires shuffling around
the definition and implementation of hasContantValue from Utils.h,cpp into
Instructions.h,cpp


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22664 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-04 23:24:19 +00:00
Nate Begeman 2ac4fc0320 Fix a fixme in LegalizeDAG 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22661 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-04 21:43:28 +00:00
Nate Begeman 99558806f8 Hack to naturally align doubles in the constant pool. Remove this once we 
know what The Right Thing To Do is.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22660 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-04 21:04:09 +00:00
Nate Begeman 3d72d14887 Use the new subtarget support to automatically choose the correct ABI 
and asm printer for PowerPC if one is not specified.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22659 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-04 20:49:48 +00:00
Nate Begeman f08341457f Remove some more dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22650 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-04 18:13:56 +00:00
Nate Begeman 8c00f8cdc7 Add Subtarget support to PowerPC. Next up, using it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22644 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-04 07:12:09 +00:00
Nate Begeman 1c73c7be9d Scalar SSE: load +0.0 -> xorps/xorpd 
Scalar SSE: a < b ? c : 0.0 -> cmpss, andps
Scalar SSE: float -> i16 needs to be promoted


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22637 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-03 23:26:28 +00:00
Nate Begeman 1b0674c966 Add a couple rlwinm tests for bitfield clears 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22624 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-03 18:27:17 +00:00
Nate Begeman 2bbcca30b7 Update rlwimi tests to catch all the cases we care about 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22623 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-03 18:11:23 +00:00
Nate Begeman f84d5ab5df Ack, typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22560 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-30 00:21:31 +00:00
Nate Begeman 1699748567 Commit a new LoopStrengthReduce pass that can use scalar evolutions and 
target data to decide which loop induction variables to strength reduce
and how to do so.  This work is mostly by Chris Lattner, with tweaks by
me to get it working on some of MultiSource.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22558 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-30 00:15:07 +00:00
Nate Begeman 36f891bdf6 Break SCEVExpander out of IndVarSimplify into its own .h/.cpp file so that 
other passes may use it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22557 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-30 00:12:19 +00:00
Nate Begeman 2a05c8e260 Fold constant adds into loads and stores to frame indices. 
For the following code:
double %ext(int %A.0__, long %A.1__) {
        %A_addr = alloca %typedef.DComplex              ; <%typedef.DComplex*> [#uses=2]
        %tmp.1 = cast %typedef.DComplex* %A_addr to int*                ; <int*> [#uses=1]
        store int %A.0__, int* %tmp.1
        %tmp.2 = getelementptr %typedef.DComplex* %A_addr, int 0, uint 1                ; <double*> [#uses=2]
        %tmp.3 = cast double* %tmp.2 to long*           ; <long*> [#uses=1]
        store long %A.1__, long* %tmp.3
        %tmp.5 = load double* %tmp.2            ; <double> [#uses=1]
        ret double %tmp.5
}

We now generate:
_ext:
.LBB_ext_0:     ;
        stw r3, -12(r1)
        stw r4, -8(r1)
        stw r5, -4(r1)
        lfd f1, -8(r1)
        blr

Instead of:
_ext:
.LBB_ext_0:     ;
        stw r3, -12(r1)
        addi r2, r1, -12
        stw r4, 4(r2)
        stw r5, 8(r2)
        lfd f1, 4(r2)
        blr

This also fires hundreds of times on MultiSource.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22533 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-28 03:02:05 +00:00
Nate Begeman 3dee17581c Fix some comments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22530 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-27 23:11:27 +00:00
Nate Begeman 54eed36da5 Implement the optimization for the Red Zone on Darwin. This removes the 
unnecessary SP manipulation in leaf routines that don't need it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22522 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-27 06:06:29 +00:00
Nate Begeman 4ad870ddcc Update the PPC readme 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22516 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-26 18:59:06 +00:00
Nate Begeman 7b4f0a81ff Fix an optimization put in for accessing static globals. This obviates 
the need to build PIC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22512 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-25 21:15:28 +00:00
Nate Begeman 2497e6391f Support building non-PIC 
Remove the LoadHiAddr pseudo-instruction.
Optimization of stores to and loads from statics.
Force JIT to use new non-PIC codepaths.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22494 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-21 20:44:43 +00:00
Nate Begeman 18ed029a7b Support assembling fsqrt on darwin. This will be implemented better when 
PowerPC gets subtarget support up.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22489 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-21 01:25:49 +00:00
Nate Begeman adeb43ddf4 Generate mfocrf when targeting g5. Generate fsqrt/fsqrts when targetin g5. 
8-byte align doubles.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22486 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-20 22:42:00 +00:00
Nate Begeman a3fd400fa8 Integrate SelectFPExpr into SelectExpr. This gets PPC32 closer to being 
automatically generated from a target description.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22470 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-19 16:51:05 +00:00
Nate Begeman 700a3c97e9 Remove unnecessary FP_EXTEND. This causes worse codegen for SSE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22469 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-19 16:50:03 +00:00
Nate Begeman 5a8441ea3f Teach the legalizer how to promote SINT_TO_FP to a wider SINT_TO_FP that 
the target natively supports.  This eliminates some special-case code from
the x86 backend and generates better code as well.

For an i8 to f64 conversion, before & after:

_x87 before:
        subl $2, %esp
        movb 6(%esp), %al
        movsbw %al, %ax
        movw %ax, (%esp)
        filds (%esp)
        addl $2, %esp
        ret

_x87 after:
        subl $2, %esp
        movsbw 6(%esp), %ax
        movw %ax, (%esp)
        filds (%esp)
        addl $2, %esp
        ret

_sse before:
        subl $12, %esp
        movb 16(%esp), %al
        movsbl %al, %eax
        cvtsi2sd %eax, %xmm0
        addl $12, %esp
        ret

_sse after:
        subl $12, %esp
        movsbl 16(%esp), %eax
        cvtsi2sd %eax, %xmm0
        addl $12, %esp
        ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22452 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-16 02:02:34 +00:00
Nate Begeman 11cefd926a Teach the register allocator that movaps is also a move instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22451 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-16 02:00:20 +00:00
Nate Begeman 9035b99abf A couple more darwinisms 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22450 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-16 01:59:47 +00:00
Nate Begeman 16b04f3d5e Get closer to fully working scalar FP in SSE regs. This gets singlesource 
working, and Olden/power.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22441 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-15 00:38:55 +00:00
Nate Begeman 6c7cb29038 Add support for printing the sse scalar comparison instruction mnemonics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22440 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-14 22:52:25 +00:00
Nate Begeman afc545616a Add support for a TODO; instructions in .td files can now have arguments 
printed as part of the opcode.  This allows something like
cmp${cc}ss in the x86 backed to be printed as cmpltss, cmpless, etc.
depending on what the value of $cc is.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22439 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-14 22:50:30 +00:00
Nate Begeman d3a490a08e Check in the last of the darwin-specific code necessary to get shootout 
working before modifying the asm printer to use the subtarget info.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22408 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-12 18:34:58 +00:00
Nate Begeman 63b3f9acae Remove some code that moved to the generic asm printer a long time ago. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22407 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-12 18:34:15 +00:00
Nate Begeman 8d2623d49a Clean up and add comments to the newly implemented subtarget code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22396 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-12 03:04:49 +00:00
Nate Begeman 0e219eb9b8 Clean up the TargetSubtarget class a bit, removing an unnecessary argument 
to the constructor.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22392 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-12 02:41:19 +00:00
Nate Begeman fb5792f416 Implement Subtarget support 
Implement the X86 Subtarget.

This consolidates the checks for target triple, and setting options based
on target triple into one place.  This allows us to convert the asm printer
and isel over from being littered with "forDarwin", "forCygwin", etc. into
just having the appropriate flags for each subtarget feature controlling
the code for that feature.

This patch also implements indirect external and weak references in the
X86 pattern isel, for darwin.  Next up is to convert over the asm printers
to use this new interface.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22389 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-12 01:41:54 +00:00
Nate Begeman 73213f6c07 Commit some pending darwin changes before subtarget support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22388 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-12 01:37:28 +00:00
Nate Begeman 72b286b0a0 Add support for assembling .s files on mac os x for intel 
Add support for running bugpoint on mac os x for intel


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22351 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-08 00:23:26 +00:00
Nate Begeman b8aa3ac678 Fix a typo in my checkin today that caused regressions. Oops! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22341 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-07 06:32:01 +00:00
Nate Begeman f63be7d395 First round of support for doing scalar FP using the SSE2 ISA extension and 
XMM registers.  There are many known deficiencies and fixmes, which will be
addressed ASAP.  The major benefit of this work is that it will allow the
LLVM register allocator to allocate FP registers across basic blocks.

The x86 backend will still default to x87 style FP.  To enable this work,
you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc.

An example before and after would be for:
double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i)
                        Sum += P[i]; return Sum; }

The inner loop looks like the following:
x87:
.LBB_foo_1:     # no_exit
        fldl (%esp)
        faddl (%eax,%ecx,8)
        fstpl (%esp)
        incl %ecx
        cmpl $1000, %ecx
        #FP_REG_KILL
        jne .LBB_foo_1  # no_exit

SSE2:
        addsd (%eax,%ecx,8), %xmm0
        incl %ecx
        cmpl $1000, %ecx
        #FP_REG_KILL
        jne .LBB_foo_1  # no_exit


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22340 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-06 18:59:04 +00:00
Nate Begeman 4eb74ba602 The statistic needs to be in the correct namespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22327 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-07-01 23:56:38 +00:00
Nate Begeman 9d19eb459c Make the x86 asm printer darwin-aware. This mostly entails doing the same 
thing as cygwin most of the time, and printing our alignments in log2
rather than number of bytes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22316 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-06-30 00:53:20 +00:00
Nate Begeman f1702ac589 Initial set of .td file changes necessary to get scalar fp in xmm registers 
working.  The instruction selector changes will hopefully be coming later
this week once they are debugged.  This is necessary to support the darwin
x86 FP model, and is recommended by intel as the replacement for x87.  As
a bonus, the register allocator knows how to deal with these registers
across basic blocks, unliky the FP stackifier.  This leads to significantly
better codegen in several cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22300 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-06-27 21:20:31 +00:00
Nate Begeman 41aaf7016e Fix bug 537 test 2, which checks to make sure that we fold A+(B-A) -> B for 
integer types.  Add a couple checks to not perform these kinds of transform
on floating point values.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22228 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-06-16 07:06:03 +00:00
Nate Begeman cb647519d3 Add some operators the PowerPC backend needs to efficiently and correctly 
generate conditional branches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22214 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-06-15 18:28:44 +00:00
Nate Begeman 439009c81e Commit fix for generating conditional branch pseudo instructions that 
avoids dereferencing the end() iterator when selecting the fallthrough
block.  This requires an ilist change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22212 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-06-15 18:22:43 +00:00
Nate Begeman a43b176f51 Commit a small improvement that is already in the x86 and ia64 backends to 
not generate unnecessary register copies.  This improves compile time by
2-5% depending on the test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22210 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-06-14 03:55:23 +00:00
Nate Begeman 244e92eaab When compiled with GCC 4.0, a latent bug was exposed where both SparcV9 
and the target independant register allocator were both using a class named
'LiveRange'.  This lead to the target independant code calling code in the
SparcV9 backend, which crashed.  Fixed by renaming SparcV9's LiveRange to
V9LiveRange.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22208 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-06-12 23:52:58 +00:00
Nate Begeman ac609ddf82 Fix a memory smasher caught by Mac OS X's debug malloc library. We were 
incorrectly using an iterator after it was invalid.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22207 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-06-12 23:50:33 +00:00
Nate Begeman b2c4bf3ff6 Handle some more real world cases of rlwimi. These don't come up that 
regularly in "normal" code, but for things like software graphics, they
make a big difference.

For the following code:
unsigned short Trans16Bit(unsigned srcA,unsigned srcB,unsigned alpha)
{
	unsigned tmpA,tmpB,mixed;
	tmpA = ((srcA & 0x03E0) << 15) | (srcA & 0x7C1F);
	tmpB = ((srcB & 0x03E0) << 15) | (srcB & 0x7C1F);
	mixed = (tmpA * alpha) + (tmpB * (32 - alpha));
	return ((mixed >> 5) & 0x7C1F) | ((mixed >> 20) & 0x03E0);
}

We now generate:
_Trans16Bit:
.LBB_Trans16Bit_0:      ; entry
        andi. r2, r4, 31775
        rlwimi r2, r4, 15, 7, 11
        subfic r4, r5, 32
        mullw r2, r2, r4
        andi. r4, r3, 31775
        rlwimi r4, r3, 15, 7, 11
        mullw r3, r4, r5
        add r2, r2, r3
        srwi r3, r2, 5
        andi. r3, r3, 31775
        rlwimi r3, r2, 12, 22, 26
        blr

Instead of:
_Trans16Bit:
.LBB_Trans16Bit_0:      ; entry
        slwi r2, r4, 15
        rlwinm r2, r2, 0, 7, 11
        andi. r4, r4, 31775
        or r2, r2, r4
        subfic r4, r5, 32
        mullw r2, r2, r4
        slwi r4, r3, 15
        rlwinm r4, r4, 0, 7, 11
        andi. r3, r3, 31775
        or r3, r4, r3
        mullw r3, r3, r5
        add r2, r2, r3
        srwi r3, r2, 5
        andi. r3, r3, 31775
        srwi r2, r2, 20
        rlwimi r3, r2, 0, 22, 26
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22201 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-06-08 04:14:27 +00:00
Nate Begeman 6dae3308f5 Fix lli linking on Mac OS X 10.4.1 for Intel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22200 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-06-08 01:02:38 +00:00
Nate Begeman be13634907 C'mon everybody, let's modify X86JITInfo.cpp. This time, we add <iostream> 
so that the shiny new use of std::cerr is defined.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22156 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-05-20 21:29:24 +00:00