Chad Rosier
a166089f36
Don't attempt to tail call optimize for Win64.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131709 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 00:59:28 +00:00
Evan Cheng
2e6496026f
Revert r131664 and fix it in instcombine instead. rdar://9467055
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131708 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 00:54:37 +00:00
Eli Friedman
dc51575a5f
Add fast-isel support for zeroext and signext ret instructions on x86.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 22:16:13 +00:00
Eric Christopher
2bbecd8f6d
Oddly people want to use the 'r' constraint for fp constants on x86.
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Fixes rdar://9218925
Fixes PR9601
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131682 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 21:33:47 +00:00
Jason W Kim
861b9c6a39
This fixes one divergence between LLVM and binutils for ARM in the
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text section.
Assume the following bit of annotated assembly:
.section .data.rel.ro,"aw",%progbits
.align 2
.LAlpha:
.long startval(GOTOFF)
.text
.align 2
.type main,%function
.align 4
main: ;;; assume "main" starts at offset 0x20
0x0 push {r11, lr}
0x4 movw r0, :lower16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-4) + 8) = -20
0x8 movt r0, :upper16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-8) + 8) = -16
0xc ... blah
.LBeta:
0x10 add r0, pc, r0
0x14 ... blah
.LGamma:
0x18 add r1, pc, r1
Above snippet results in the following relocs in the .o file for the
first pair of movw/movt instructions
00000024 R_ARM_MOVW_PREL_NC .LAlpha
00000028 R_ARM_MOVT_PREL .LAlpha
And the encoded instructions in the .o file for main: must be
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec i.e. -20
28: e34f0ff0 movt r0, #65520 ; 0xfff0 i.e. -16
However, llc (prior to this commit) generates the following sequence
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec - i.e. -20
28: e34f0fff movt r0, #65535 ; 0xffff - i.e. -1
What has to happen in the ArmAsmBackend is that if the relocation is PC
relative, the 16 bits encoded as part of movw and movt must be both addends,
not addresses. It makes sense to encode addresses by right shifting the value
by 16, but the result is incorrect for PIC.
i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case.
This change agrees with what GNU as does, and makes the PIC code run.
MC/ARM/elf-movt.s covers this case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131674 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 20:55:25 +00:00
Rafael Espindola
a3bff99f0a
ADD64ri32 sign extends its argument, so we need to use a R_X86_64_32S.
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Fixes PR9934.
We really need to start tblgening the relocation info :-(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131669 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 20:32:34 +00:00
Akira Hatanaka
a1a7ba8382
Align i64 arguments to 64 bit boundaries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131668 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 20:29:48 +00:00
Evan Cheng
0efaa5e6a1
crc32 with 64-bit output zeros upper 32-bits. rdar://9467055
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131664 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 18:57:12 +00:00
Akira Hatanaka
59d266029c
Increase number of available registers when target is MIPS32.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131660 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 18:25:03 +00:00
Akira Hatanaka
95b8ae190e
Simplify CC_MipsO32 and merge it with CC_MipsO32_VarArgs. Patch by Sasa Stankovic.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131657 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 18:06:05 +00:00
Stuart Hastings
d22f036c2a
Reverting 131641 to investigate 'bot complaint.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131654 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 17:54:42 +00:00
Jim Grosbach
6635b04a43
80 columns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131649 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 17:34:53 +00:00
Akira Hatanaka
d48cfaec35
Fix data layout string. i64 is aligned to 64 bit boundaries.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131642 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 17:21:09 +00:00
Stuart Hastings
b6dcf3c514
Revise MOVSX16rr8/MOVZX16rr8 (and rm variants) to no longer be
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pseudos. rdar://problem/8614450
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131641 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 16:59:50 +00:00
Cameron Zwarich
055cdfc541
Use the correct register class for Cell varargs spilling. This fixes all of the
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verifier failures in the CodeGen/CellSPU tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131631 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 04:44:19 +00:00
Mon P Wang
28e2b1d29a
Fixed sdiv and udiv for <4 x i16>. The test from r125402 still applies for this change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131630 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 04:15:07 +00:00
Cameron Zwarich
d76773a221
Make CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll pass with the verifier.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131627 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 03:11:06 +00:00
Cameron Zwarich
0113e4e3f2
Fix PR8828 by removing the explicit def in MovePCToLR as well as the pointless
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piclabel operand. The operand in the tablegen definition doesn't actually turn
into an MI operand, so it just confuses anything checking the TargetInstrDesc
for the number of operands. It suffices to just have an implicit def of LR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131626 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 02:56:28 +00:00
Cameron Zwarich
462b6dc6bf
Reuse the TargetInstrDesc.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131625 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 02:56:23 +00:00
Cameron Zwarich
21803721d5
Correctly constrain a register class when computing frame offsets, as the Thumb2
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add instruction takes an rGPR. This fixes the last of PR8825.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131619 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 02:18:27 +00:00
Eli Friedman
22486c9aba
Revert unintentional commit.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131597 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 23:13:10 +00:00
Eli Friedman
107ffd58f7
More instcombine simplifications towards better debug locations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131596 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 23:11:30 +00:00
Cameron Zwarich
631fcbf810
Add missing mayLoad / mayStore flags to instruction definitions without patterns,
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which fixes all of the CodeGen/MBlaze verifier failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131595 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 23:03:10 +00:00
Cameron Zwarich
e4c6445405
Reserve the segment registers on x86 to fix verifier failures in any code that
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uses them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131591 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 22:24:48 +00:00
Cameron Zwarich
20a41cb2b2
Reserve r29 on Alpha. This fixes all verifier failures in CodeGen/Alpha.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131587 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 21:54:32 +00:00
Tanya Lattner
db28247522
Handle perfect shuffle case that generates a vrev for vectors of floats.
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Add test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131582 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 21:44:54 +00:00
Cameron Zwarich
955db42568
Fix more of PR8825. Now all of CodeGen/ARM passes with VerifyCoalescing turned on.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131578 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 21:25:14 +00:00
Johnny Chen
a96581f4f7
Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131565 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 20:32:41 +00:00
Chad Rosier
871f664093
Enables vararg functions that pass all arguments via registers to be optimized into tail-calls when possible.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131560 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 19:59:50 +00:00
Evan Cheng
b936e3006f
Revise r131553. Just use the type of the input node and forgo the bitcast. rdar://9449159.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131555 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 18:59:17 +00:00
Evan Cheng
d48fda46f5
Fix an ARMTargetLowering::LowerSELECT bug: legalized result must have same type as input. Sorry test cases only trigger when dag combine is disabled. rdar://9449178
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131553 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 18:47:27 +00:00
Justin Holewinski
657d1bed23
PTX: add flag to disable mad/fma selection
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Patch by Dan Bailey
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131537 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 15:42:23 +00:00
Tanya Lattner
2a8eb722c7
In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32.
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Updated test case and reverted change to the PerfectShuffle Table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131529 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 06:42:21 +00:00
Cameron Zwarich
141ec63962
Fix typo.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131519 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 02:29:50 +00:00
Cameron Zwarich
7d336c0c68
Fix more of PR8825 by correctly using rGPR registers when lowering atomic
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compare-and-swap intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 02:20:07 +00:00
Cameron Zwarich
d6ffcd88ba
Actually, the address operand of the Thumb2 LDREX / STREX instructions *can*
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take r13, so we can just make it a GPR. This fixes PR8825.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131507 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 23:26:20 +00:00
Cameron Zwarich
3c60ff4f3d
Correct a minor problem with the Thumb2 LDREX and STREX instruction encodings. They
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were marked as taking a tGPR when in reality they take an rGPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131506 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 23:11:12 +00:00
Tanya Lattner
c81c9709ef
vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 20:48:40 +00:00
Mon P Wang
fee22869ca
Enable autodetect of popcnt
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131476 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 18:33:37 +00:00
Eli Friedman
19515b4e52
Add x86 fast-isel for calls returning first-class aggregates. rdar://9435872.
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This is r131438 with a couple small fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131474 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 18:29:03 +00:00
Eli Friedman
b8e0d3412c
Clean up the mess created by r131467+r131469.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131471 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 18:02:22 +00:00
Stuart Hastings
6db2c2fe21
Revert 131467 due to buildbot complaint.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131469 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 16:59:46 +00:00
Stuart Hastings
504421e327
Fix an obscure issue in X86_64 parameter passing: if a tiny byval is
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passed as the fifth parameter, insure it's passed correctly (in R9).
rdar://problem/6920088
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131467 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 16:45:55 +00:00
Nadav Rotem
86694297ff
Fix a bug in PerformEXTRACT_VECTOR_ELTCombine. The code created an ADD SDNode
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with two different types, in cases where the index and the ptr had different
types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131461 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 08:31:57 +00:00
Eric Christopher
6abb7bae10
Update comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131459 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 08:16:14 +00:00
Eric Christopher
c324f72ab7
Support XOR and AND optimization with no return value.
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Finishes off rdar://8470697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131458 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 08:10:18 +00:00
Eric Christopher
811c2b7110
Couple less magic numbers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131457 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 07:50:41 +00:00
Eric Christopher
8102bf003e
Make this code a little less magic number laden.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131456 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 07:47:55 +00:00
Chris Lattner
5d4718b1c7
add a note
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131455 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 07:22:33 +00:00
Eli Friedman
c93943b6fe
Back out r131444 and r131438; they're breaking nightly tests. I'll look into
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it more tomorrow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131451 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 02:36:59 +00:00
Eli Friedman
cdc9a20561
Add x86 fast-isel for calls returning first-class aggregates. rdar://9435872.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131438 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 00:13:47 +00:00
Jim Grosbach
0c72076190
Kill some dead code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131431 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-16 22:24:07 +00:00
Eli Friedman
57f4b03621
Remove dead code. Fix associated test to use FileCheck.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131424 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-16 21:28:22 +00:00
Eli Friedman
482feb33b2
Make fast-isel work correctly s/uadd.with.overflow intrinsics.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131420 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-16 21:06:17 +00:00
Rafael Espindola
6469540adf
sets bit 0 of the function address of thumb function in .symtab
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("T is 1 if the target symbol S has type STT_FUNC and the
symbol addresses a Thumb instruction ;it is 0 otherwise."
from "ELF for the ARM Architecture" 4.7.1.2)
Patch by Koan-Sin Tan!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131406 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-16 16:17:21 +00:00
Eli Friedman
d0118a2371
Fix a FIXME by moving the fast-isel implementation of the objectsize intrinsic from the x86 code to the generic code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131332 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-14 00:47:51 +00:00
Rafael Espindola
a3f88148e6
Don't produce a vmovntdq if we don't have AVX support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131330 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-14 00:30:01 +00:00
Eli Friedman
d25d16c901
Zap useless code; this hasn't done anything useful since fast-isel switched to being bottom-up (a very long time ago).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131329 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-14 00:19:32 +00:00
Julien Lerouge
eea6c95d5d
Fix a source of non determinism in FindUsedTypes, use a SetVector instead of a
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set.
rdar://9423996
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131283 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-13 05:20:42 +00:00
Akira Hatanaka
01765eb0a1
Fix setting of isCommutable flag.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131233 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-12 17:42:08 +00:00
Eric Christopher
c493a1f317
Turn this into a table, this will make more sense shortly.
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Part of rdar://8470697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131200 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-11 21:44:58 +00:00
Owen Anderson
18901d63bf
Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-11 17:00:48 +00:00
Nadav Rotem
4301222525
Add custom lowering of X86 vector SRA/SRL/SHL when the shift amount is a splat vector.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131179 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-11 08:12:09 +00:00
Bill Wendling
61512ba251
Give the 'eh.sjlj.dispatchsetup' intrinsic call the value coming from the setjmp
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intrinsic call. This prevents it from being reordered so that it appears
*before* the setjmp intrinsic (thus making it completely useless).
<rdar://problem/9409683>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131174 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-11 01:11:55 +00:00
Eric Christopher
b38fe4b52d
Optimize atomic lock or that doesn't use the result value.
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Next up: xor and and.
Part of rdar://8470697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131171 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-10 23:57:45 +00:00
Eric Christopher
988397dcbc
Refactor lock versions of binary operators to be a little less
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cut and paste.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131139 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-10 18:36:16 +00:00
Jason W Kim
f4351ceb93
First cut at getting debugging support for ARM/MC/ELF/.o
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DWARF stuff also gets fixed up by ELFARMAsmBackend::ApplyFixup(),
but the offset is not guaranteed to be mod 4 == 0 as in text/data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131137 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-10 18:07:25 +00:00
Justin Holewinski
0d10970789
PTX: add PTX 2.3 setting in PTX sub-target.
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Patch by Wei-Ren Chen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131123 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-10 12:32:11 +00:00
Eric Christopher
49ac3d7da9
Fix td file comments for Mips.
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Patch by Liu <proljc@gmail.com>!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131086 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-09 18:16:46 +00:00
Mon P Wang
183c627d89
Fixed MC encoding for index_align for VLD1/VST1 (single element from one lane) for size 32
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131085 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-09 17:47:27 +00:00
Benjamin Kramer
f51190b697
X86: Add a bunch of peeps for add and sub of SETB.
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"b + ((a < b) ? 1 : 0)" compiles into
cmpl %esi, %edi
adcl $0, %esi
instead of
cmpl %esi, %edi
sbbl %eax, %eax
andl $1, %eax
addl %esi, %eax
This saves a register, a false dependency on %eax
(Intel's CPUs still don't ignore it) and it's shorter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131070 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-08 18:36:07 +00:00
Jakob Stoklund Olesen
ca66226e7e
Eliminate the ARM sub-register indexes that are not needed by the sources.
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Tablegen will invent its own names for these indexes, and the register file is a
bit simpler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131059 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-07 21:22:42 +00:00
Eric Christopher
33c110e602
Fix the non-MC encoding of pkhbt and pkhtb.
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Patch by Stephen Hines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131045 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-07 04:37:27 +00:00
Akira Hatanaka
325e66d81a
1. Keep lines in 80 columns.
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2. Remove unused function.
3. Correct indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131028 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-06 22:11:29 +00:00
Eli Friedman
fc5d305597
Make the logic for determining function alignment more explicit. No functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131012 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-06 20:34:06 +00:00
Rafael Espindola
f2b0423200
Dead code elimination.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130984 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-06 14:56:22 +00:00
Justin Holewinski
ab0145d2a9
PTX: add PTX 2.3 language target
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Patch by Wei-Ren Chen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130980 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-06 11:40:36 +00:00
Rafael Espindola
108709d4d1
Move PPC Linux to CFI.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130951 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-05 21:34:33 +00:00
Eli Friedman
297015913a
PR9848: pandn is not commutative.
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No test because I can't think of any way to write one that won't break quickly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130932 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-05 17:45:31 +00:00
Bill Wendling
087aad44cb
Remove a flag that would set the ".eh" symbol as .globl. MachO was the only one
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who used this flag, and it now emits CFI and doesn't emit this anymore. All
other targets left this flag "false".
<rdar://problem/8486371>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130918 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-05 06:49:15 +00:00
Jakob Stoklund Olesen
4f5de9bb40
Fix X86RegisterInfo::getMatchingSuperRegClass for sub_8bit_hi.
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It is OK for B to be any GR8_ABCD_H superclass, the returned register class
doesn't have to map surjectively onto B.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130892 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-04 23:54:54 +00:00
Jakob Stoklund Olesen
21f7902a89
Implement SystemZRegisterInfo::getMatchingSuperRegClass to enable cross-class joins.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130857 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-04 19:02:04 +00:00
Devang Patel
64915dec28
Do not emit location expression size twice.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130854 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-04 19:00:57 +00:00
Rafael Espindola
6af0b762db
Fix cmake build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130850 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-04 18:46:56 +00:00
Akira Hatanaka
6b7588e6c4
Prevent instructions using $gp from being placed between a jalr and the instruction that restores the clobbered $gp.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130847 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-04 17:54:27 +00:00
Jakob Stoklund Olesen
b89383aeff
Implement MSP430RegisterInfo::getMatchingSuperRegClass to enable cross-class
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coalescing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130814 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-04 01:01:36 +00:00
Jakob Stoklund Olesen
2944b4fe05
Mark ultra-super-registers QQQQ as call-clobbered instead of the D sub-registers.
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LiveVariables doesn't understand that clobbering D0 and D1 completely overwrites
Q0, so if Q0 is live-in to a function, its live range will extend beyond a
function call that only clobbers D0 and D1. This shows up in the
ARM/2009-11-01-NeonMoves test case.
LiveVariables should probably implement the much stricter rules for physreg
liveness that RAFast imposes - a physreg is killed by the first use of any
alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130801 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 22:31:24 +00:00
Bill Wendling
9493a285d1
Replace the "movnt" intrinsics with a native store + nontemporal metadata bit.
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<rdar://problem/8460511>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130791 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 21:11:17 +00:00
Akira Hatanaka
9ff1b9b259
Fix function MipsRegisterInfo::getRegisterNumbering.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130774 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 18:41:54 +00:00
Bob Wilson
e1a56ae747
Temporarily disable use of divmod compiler-rt functions for iOS.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130766 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 17:33:22 +00:00
Bruno Cardoso Lopes
0a69ba309f
Fold ARM coprocessor intrinsics patterns into the instructions defs whenever
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it's possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130764 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 17:29:29 +00:00
Bruno Cardoso Lopes
54ad87ab78
Add a few ARM coprocessor intrinsics. Testcases included
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130763 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 17:29:22 +00:00
Benjamin Kramer
d2189bf12a
Remove unused variables caught by GCC's -Wunused-but-set-variable.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130755 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 16:00:27 +00:00
Michael J. Spencer
34868ee4de
Add pentium{3,4}m cpus. Patch by Alexander Best!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130749 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 03:42:50 +00:00
Eric Christopher
2fc496fcf5
xmm0 is an implicit parameter in this and so shouldn't be in the
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string template.
Fixes rdar://8493866
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130747 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 01:28:32 +00:00
Dan Gohman
cca82149ad
Add an unfolded offset field to LSR's Formula record. This is used to
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model constants which can be added to base registers via add-immediate
instructions which don't require an additional register to materialize
the immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130743 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 00:46:49 +00:00
Eric Christopher
52f6c03a45
Apparently the check for direct calls is unnecessary.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130716 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-02 20:16:33 +00:00
Rafael Espindola
2866edf120
Add 130690 back.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130693 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-02 15:58:16 +00:00
Rafael Espindola
b2d7336fde
Revert while I debug the tests that use march but not mtriple.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130691 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-02 15:42:31 +00:00
Rafael Espindola
433771c514
Move ppc OS X to cfi too. I am building it on an old ppc mini, but it will take some time.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130690 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-02 15:00:52 +00:00