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19228 Commits

Author SHA1 Message Date
Jim Grosbach
dd32ba337a ARM load shifted register pre-index fix shift value asm parser encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137367 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 22:05:09 +00:00
Owen Anderson
796d6b7602 Handle new register classes in Thumb2 mode. Should fix the ARM buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137364 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:52:38 +00:00
Owen Anderson
05b0c9f41e Making SEL decodings auto-generate-able. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137363 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:50:56 +00:00
Bruno Cardoso Lopes
ef8d6999f3 Add a dag combine to xform 256-bit shuffles into simple vector 
inserts and extracts. This simple combine makes us generate only 1
instruction instead of 11 in the v8 case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137362 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:50:44 +00:00
Jim Grosbach
89958d50c3 Tidy up comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137359 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:41:59 +00:00
Owen Anderson
cbfc044acd Fix decoding support for STREXD and LDREXD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137356 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:34:58 +00:00
Jim Grosbach
7b8f46cf9e ARM STRH assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137353 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:17:22 +00:00
Akira Hatanaka
1f8d822023 Add isIndirectBranch flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137351 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 21:05:37 +00:00
Owen Anderson
508e1d3db5 Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137347 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:47:56 +00:00
Jim Grosbach
45251b3707 Tidy up. Remove unused template parameter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137345 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:41:13 +00:00
Owen Anderson
9fe72bcd37 Improve operand validation for Thumb2 addressing modes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137344 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:40:40 +00:00
Jim Grosbach
14605d1a67 ARM STRD assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137342 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:28:23 +00:00
Owen Anderson
26d2f0ac91 Continue to tighten decoding by performing more operand validation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137340 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:21:46 +00:00
Jim Grosbach
ade7d00f5a Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137339 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:13:35 +00:00
Jim Grosbach
10348e70d5 ARM STRBT assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137337 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 20:04:56 +00:00
Jim Grosbach
548340c4bf ARM STR(immediate) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137331 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 19:22:40 +00:00
Owen Anderson
71156a6e00 Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137325 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 19:00:18 +00:00
Bruno Cardoso Lopes
59353b436a Fix PR10492 by teaching MOVHLPS and MOVLPS mask matching to be more strict. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137324 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 18:59:13 +00:00
Owen Anderson
2b7b238e84 Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137323 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 18:55:42 +00:00
Owen Anderson
3dac0bec7e Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137322 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 18:41:59 +00:00
Owen Anderson
ae0bc5deaa Improve error checking in the new ARM disassembler. Patch by James Molloy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137320 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 18:24:51 +00:00
Jim Grosbach
f6713916fb ARM push of a single register encodes as pre-indexed STR. 
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137318 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 18:07:11 +00:00
Jim Grosbach
f8fce711e8 ARM pop of a single register encodes as post-indexed LDR. 
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137316 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 17:35:48 +00:00
Nadav Rotem
6236f7f2b6 Add a comment, per Bruno's CR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137313 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 17:05:47 +00:00
Nadav Rotem
5e742a3e1b [AVX] If the data which is going to be saved is already in two XMM registers 
(for example, after integer operation), do not pack the registers into a YMM
before saving. Its better to save as two XMM registers.

Before:
                vinsertf128         $1, %xmm3, %ymm0, %ymm3
                vinsertf128         $0, %xmm1, %ymm3, %ymm1
                vmovaps              %ymm1, 416(%rsp)

After:
                vmovaps              %xmm3, 416+16(%rsp)
                vmovaps              %xmm1, 416(%rsp)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137308 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 16:41:21 +00:00
Bruno Cardoso Lopes
b02c0ace20 Cleanup: Remove Int_ CVTSS2SI* forms 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137297 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 02:52:36 +00:00
Bruno Cardoso Lopes
5f1d8abf75 Splats for v8i32/v8f32 can be handled by VPERMILPSY. This was causing 
infinite recursive calls in legalize. Fix PR10562

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137296 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 02:49:44 +00:00
Bruno Cardoso Lopes
a5134a0ea3 Use the splat index to generate the desired shuffle. Otherwise we 
could only get undefs and the vector shuffle becomes an undef,
generating wrong code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137295 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 02:49:41 +00:00
Eli Friedman
586272d67c Fix X86TargetLowering::LowerExternalSymbol so that it actually works in non-trivial cases. This hasn't been an issue before because the function isn't normally called (but apparently is used to generate a tail-call to sin() on ELF x86-32 with PIC and SSE2). 
Fixes PR9693.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137292 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-11 01:48:05 +00:00
Jim Grosbach
59999264e6 ARM LDRT assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137282 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 23:43:54 +00:00
Jim Grosbach
e15defc56c Tidy up. 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137277 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 23:23:47 +00:00
Jim Grosbach
623a454b0f ARM LDRH(immediate) assembly parsing and encoding support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137260 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 22:42:16 +00:00
Jim Grosbach
251bf25e7e ARM LDRD(register) assembly parsing and encoding. 
Add support for literal encoding of #-0 along the way.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137254 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 21:56:18 +00:00
Jim Grosbach
53642c5335 Fix typo. Not quite sure how that slipped in there. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137245 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 20:49:18 +00:00
Jim Grosbach
2fd2b87ded ARM LDRD(immediate) assembly parsing and encoding support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137244 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 20:29:19 +00:00
Nadav Rotem
614061bfb4 When performing a truncating store, it is sometimes possible to rearrange the 
data in-register prior to saving to memory.  When we reorder the data in memory
we prevent the need to save multiple scalars to memory, making a single regular
store.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137238 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 19:30:14 +00:00
Owen Anderson
8533ebad6f Add initial support for decoding NEON instructions in Thumb2 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137236 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 19:01:10 +00:00
Bruno Cardoso Lopes
6ad251358e The following X86 pattern is incorrect: 
def : Pat<(X86Movss VR128:$src1,
                   (bc_v4i32 (v2i64 (load addr:$src2)))),
          (MOVLPSrm VR128:$src1, addr:$src2)>;
This matches a MOVSS dag with a MOVLPS instruction. However, MOVSS will replace only the low 32 bits of the register, while the MOVLPS instruction will replace the low 64 bits. A testcase is added and illustrates the bug and also modified the one that was already present. Patch by Tanya Lattner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137227 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 17:45:17 +00:00
Owen Anderson
fd9085dca3 Tabs --> spaces. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137225 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 17:38:05 +00:00
Owen Anderson
10cbaab7b7 Cleanups based on Nick Lewycky's feedback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137224 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 17:36:48 +00:00
Owen Anderson
e66ef2d5f5 Rewrite some ARM InstrInfo functions to be most accepting of arbitrary register subclasses. Hopefully this fixes some buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137223 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 17:21:20 +00:00
Rafael Espindola
f5ade5d39a Add support for the R and Q constraints. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137217 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 16:26:42 +00:00
Bruno Cardoso Lopes
155a92a491 Fix a bug in vpermilps mask checking. Fix PR10560 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137194 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 01:54:17 +00:00
Owen Anderson
33e57515b1 Push GPRnopc through a large number of instruction definitions to tighten operand decoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-10 00:03:03 +00:00
Jakob Stoklund Olesen
c70c2cafe1 Promote VMOVS to VMOVD when possible. 
On Cortex-A8, we use the NEON v2f32 instructions for f32 arithmetic. For
better latency, we also send D-register copies down the NEON pipeline by
translating them to vorr instructions.

This patch promotes even S-register copies to D-register copies when
possible so they can also go down the NEON pipeline.  Example:

        vldr.32 s0, LCPI0_0
    loop:
        vorr    d1, d0, d0
    loop2:
        ...
        vadd.f32        d1, d1, d16

The vorr instruction looked like this after regalloc:

    %S2<def> = COPY %S0, %D1<imp-def>

Copies involving odd S-registers, and copies that don't define the full
D-register are left alone.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137182 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 23:41:44 +00:00
Owen Anderson
de317f40f7 Tighten operand checking of register-shifted-register operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137180 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 23:33:27 +00:00
Bruno Cardoso Lopes
d40aa24ebf Add 256-bit support for v8i32, v4i64 and v4f64 ISD::SELECT. Fix PR10556 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137179 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 23:27:13 +00:00
Owen Anderson
c36481c474 Tighten operand checking on memory barrier instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137176 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 23:25:42 +00:00
Owen Anderson
35008c2f8d Tighten operand checking on CPS instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137172 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 23:05:39 +00:00
Owen Anderson
51c9805c4b Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137168 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-09 22:48:45 +00:00