Kevin Enderby
044be39090
Fixed the SS42AI template for the SSE 4.2 instructions with TA prefix so it does
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not get an "Unknown immediate size" assert failure when used. All instructions
of this form have an 8-bit immediate. Also added a test case of an example
instruction that is of this form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 22:28:42 +00:00
Nate Begeman
1449f29100
Per chris's request, add some comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99434 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 22:19:06 +00:00
Johnny Chen
69631b1327
Trivial formating change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99428 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 21:25:07 +00:00
Nate Begeman
fdea31a463
BUILD_VECTOR was missing out on some prime opportunities to use SSE 4.1 inserts.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99423 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 20:49:50 +00:00
Johnny Chen
2fadd6b221
Reverted r99326 which added NVdVmVCVTFrm, and later renamed to NVCVTFrm.
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NVCVTFrm will later be used to describe "vcvt with fractional bits".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99415 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 19:47:14 +00:00
Johnny Chen
7d85ac09f8
Reverted r99376. The disassembler will deal with the 2-reg format of these two
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N3VX instructions using special case code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99409 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 18:46:34 +00:00
Jim Grosbach
35075a7e81
tweak the arm if conversion heuristic
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99402 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 16:15:14 +00:00
Johnny Chen
b7ba5781e6
Mark VMOVDneon and VMOVQ as having the N2RegFrm form to help the disassembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99376 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 01:29:25 +00:00
Chris Lattner
c54a2f150d
Switch INC8r to defining its pattern in terms of X86inc_flag
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and defining the add pattern with Pat<>, eliminating a use of
parallel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99375 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 01:02:12 +00:00
Johnny Chen
c5f413a74c
Renamed NVdVmImmFrm and NVdVmVCVTFrm to the more proper N2RegFrm and NVCVTFrm,
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respectively, and add some more comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99373 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:57:50 +00:00
Chris Lattner
1aec4d7596
switch SDTBinaryArithWithFlags to be a multiple-result node as well.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99370 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:49:29 +00:00
Chris Lattner
74c8d67af8
Switch SDTUnaryArithWithFlags to being modeled as a two-result
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ISD node. The only change in the generated isel code are comments
like:
< // Src: (X86dec_flag:i16 GR16:i16:$src)
---
> // Src: (X86dec_flag:i16:i32 GR16:i16:$src)
because now it knows that X86dec_flag returns both an i16 (for the result)
and an i32 (for EFLAGS) in this case. Wewt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99369 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:47:47 +00:00
Chris Lattner
7e504141e0
remove 64-bit or_is_add parallels.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:16:52 +00:00
Chris Lattner
a0f7017752
remove useless or_is_add parallel's.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99359 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:15:23 +00:00
Chris Lattner
fdac0b66f0
reduce nesting.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99358 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:12:57 +00:00
Jim Grosbach
fceabef52c
try being more permissive for if-conversion on ARM V7. see what the nightly
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test run permformance numbers say as to whether it helps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99355 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:03:13 +00:00
Jakob Stoklund Olesen
fe4b92baf1
Revert "Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings."
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This reverts commit 99345. It was breaking buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99352 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 23:48:51 +00:00
Chris Lattner
ae8f4c4f86
[llvm_void_ty] is no longer needed for result types,
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just use an empty result list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99346 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 23:46:07 +00:00
Jakob Stoklund Olesen
c75c5fa125
Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain crossings.
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This is work in progress. So far, SSE execution domain tables are added to
X86InstrInfo, and a skeleton pass is enabled with -sse-domain-fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99345 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 23:14:44 +00:00
Johnny Chen
a271174771
Renamed NVdImmFrm to N1RegModImmFrm.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99344 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 23:09:14 +00:00
Johnny Chen
841e828702
Fix typo in the comment for N3VX class.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99328 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 21:35:03 +00:00
Johnny Chen
be7849ee73
Add comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99327 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 21:30:12 +00:00
Johnny Chen
3ae9a57c74
Add New NEON Format NVdVmVCVTFrm.
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Converted some of the NEON vcvt instructions to this format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99326 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 21:25:38 +00:00
Johnny Chen
927b88f771
Add New NEON Format NVdVmImmFrm.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99322 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 20:40:44 +00:00
Evan Cheng
8d1f0dd983
Teach isSafeToClobberEFLAGS to ignore dbg_value's. We need a MachineBasicBlock::iterator that does this automatically?
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99320 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 20:35:45 +00:00
Bob Wilson
df9a4f0591
Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes.
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These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP. The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99309 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 18:54:46 +00:00
Bob Wilson
011355944b
Fix bad indentation, 80-column violations, and trailing whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99295 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 17:23:59 +00:00
Johnny Chen
785516adc5
Add New NEON Format NVdImmFrm.
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Ref: A7.4.6 One register and a modified immediate value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99288 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 16:43:47 +00:00
Bob Wilson
c289a0252b
Rename some instructions to match the corresponding NEON opcode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99266 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 06:26:18 +00:00
Bob Wilson
11d9899759
Change VST1 instructions for loading Q register values to operate on pairs
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of D registers. Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99265 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 06:20:33 +00:00
Bob Wilson
621f195243
Change VLD1 instructions for loading Q register values to operate on pairs
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of D registers. Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99261 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 05:25:43 +00:00
Daniel Dunbar
337055e62f
MC: Add TargetAsmBackend::MayNeedRelaxation, for checking whether a particular instruction + fixups might need relaxation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99249 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 03:13:05 +00:00
Daniel Dunbar
8f9b80e5df
MC: Add TargetAsmBackend::WriteNopData and use to eliminate some target dependencies in MCMachOStreamer and MCAssembler.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99248 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 02:36:58 +00:00
Daniel Dunbar
829680048c
MC: Add TargetAsmBackend::RelaxInstruction callback, and custom X86 implementation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99245 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23 01:39:09 +00:00
Bob Wilson
62ef3c8910
Rename one more NEON instruction that I missed earlier.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99201 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-22 20:31:39 +00:00
Bob Wilson
052ba45bf8
Regroup some instructions. No functional change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99192 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-22 18:22:06 +00:00
Bob Wilson
a6979754da
Rename some VLD1/VST1 instructions to match the implementation, i.e., the
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corresponding NEON instructions, instead of operation they are currently
used for.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99189 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-22 18:13:18 +00:00
Bob Wilson
58393bc3fd
Remove some redundant instruction classes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99187 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-22 18:02:38 +00:00
Bob Wilson
39842553e8
Refactor instruction encoding arguments for VLDnLN/VSTnLN classes to
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specify encoding bits in arguments instead of "let" expressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99185 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-22 16:43:10 +00:00
Jakob Stoklund Olesen
e5b8bfa0c5
Completely remove Blackfin patterns that thought JustCC was i1.
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Thanks, Chris!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99183 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-22 16:30:04 +00:00
Jeffrey Yasskin
fa72340ba0
Don't leak a MachineInstruction from Thumb1InstrInfo::restoreCalleeSavedRegisters.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99182 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-22 16:13:21 +00:00
Daniel Dunbar
f2de13f8d7
MC/X86: Fix an MCOperand link, when we parsing shrld $1,%eax and friends; I believe this fixes the last memory leaks under test/MC.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99102 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 22:36:38 +00:00
Daniel Dunbar
5d067fe158
TargetRegistry: Fix create{AsmInfo,MCDisassembler} to return non-const objects.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99097 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 22:36:22 +00:00
Bob Wilson
c88d072293
pr6652: Use LDM to restore PC to the return address on ARMv4.
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Patch by John Tytgat!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99096 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 22:20:40 +00:00
Bob Wilson
226036ee73
Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")
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with changes to add a separate optional register update argument. Change all
the NEON instructions with address register writeback to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99095 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 22:13:40 +00:00
Bob Wilson
d5fadaf56e
Add instruction variants for VST2, VST3, and VST4 "store-lane" operations with
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address register writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 21:57:36 +00:00
Bob Wilson
4f4f93f9d6
Add variants of VST2, VST3 and VST4 with address register writeback, and
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rewrite the existing VST3 and VST4 instructions to use the same classes as
the others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99093 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 21:45:18 +00:00
Bob Wilson
068b18be0d
Add instructions for double-spaced VST3 and VST4 without address register
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writeback, and refactor the existing double-spaced VST2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99090 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 21:15:48 +00:00
Bob Wilson
25eb5013d0
Add VST1 instructions with address register writeback.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99083 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 20:54:36 +00:00
Bob Wilson
a1023645f8
Add instruction variants for VLD2, VLD3, and VLD4 "load-lane" operations with
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address register writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99082 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 20:47:18 +00:00
Bob Wilson
41315282f9
Tidy some more comments and whitespace.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99081 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 20:39:53 +00:00
Bob Wilson
92cb9321a1
Add variants of VLD2, VLD3 and VLD4 with address register writeback, and
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rewrite the existing VLD3 and VLD4 instructions to use the same classes as
the others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99080 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 20:10:51 +00:00
Bob Wilson
667a13e1be
Tidy some comments and whitespace for consistency.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99078 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 19:57:03 +00:00
Bob Wilson
95ffecd4fe
Rename some instructions for consistency and sanity: use "_UPD" suffix for
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load/stores with address register writeback, and use "odd" suffix to distinguish
instructions to access odd numbered registers (instead of "a" and "b").
No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99066 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 18:35:24 +00:00
Bob Wilson
00bf1d93d7
Add instructions for double-spaced VLD3 and VLD4 without address register
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writeback, and refactor the existing double-spaced VLD2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99065 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 18:14:26 +00:00
Bob Wilson
99493b2b53
Add VLD1 instructions with address register writeback.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99062 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 17:59:03 +00:00
Benjamin Kramer
dd70cea00c
PIC16: Simplify code by using a std::set<std::string> instead of a sorted & uniqued std::list of leaked char*.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99061 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 17:41:18 +00:00
Bob Wilson
55c9cb5a22
Revert the rest of 98679.
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--- Reverse-merging r98679 into 'lib/Target/ARM/ARMInstrVFP.td':
U lib/Target/ARM/ARMInstrVFP.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99049 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 06:34:02 +00:00
Bob Wilson
98330ff8e3
Fix a very bad typo. Since the register number was off by one, the ARM
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load/store optimizer would incorrectly think that registers D26 and D28
were consecutive and would generate a VLDM instruction to load them.
The assembler was not convinced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99043 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 06:05:13 +00:00
Evan Cheng
f5b9d6cc82
If call result is in ST0 and it is not being passed to the caller's
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caller, then it is not safe to optimize the call into a sibcall since
the call result has to be popped off the x87 stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99032 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 02:58:15 +00:00
Johnny Chen
caa608e97c
Add NLdStFrm Format.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99014 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20 00:17:00 +00:00
Johnny Chen
e86425f224
Revert r98679. The disassembler will be updated to depend on the existence of
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IndexModeUpd and then populates the Inst{21}=1 while populating the instructions
for disassembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99013 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 23:50:27 +00:00
Bob Wilson
76a312b7d1
Revert this change, since it was causing ARM performance regressions.
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--- Reverse-merging r98889 into '.':
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMISelLowering.h
U lib/Target/ARM/ARMInstrInfo.td
U lib/Target/ARM/ARMInstrVFP.td
U lib/Target/ARM/ARMISelLowering.cpp
U lib/Target/ARM/ARMInstrFormats.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99010 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 22:51:32 +00:00
Chris Lattner
99521af212
remove the patterns that I commented out in r98930, Dan verified
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that they are dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99000 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 21:43:36 +00:00
Kevin Enderby
b46b03b36f
Fixed the encoding problems of the crc32 instructions. All had the Operand size
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override prefix and only the r/m16 forms should have had that. Also for variant
one, the AT&T syntax, added suffixes to all forms. Also added the missing
64-bit form for 'CRC32 r64, r/m8'. Plus added test cases for all forms and
tweaked one test case to add the needed suffixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98980 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 20:04:42 +00:00
Daniel Dunbar
0180daee02
MC/X86: Rename alternate spellings of {ADD64,CMP64} and mark as "code gen only" so they don't get selected by the asm matcher.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98972 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 18:07:48 +00:00
Johnny Chen
81f04d59f6
Renumber LdStExFrm from 28 to 11 and shift the existing format values to make
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room for it. This is in preparation for another patch which is adding NEON
subformats to facilitate disassembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98967 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 17:39:00 +00:00
Daniel Dunbar
1a9158c301
MC: Add TargetAsmBackend::createObjectWriter.
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- MCAssembler is now object-file independent, although we will surely need more work to fully support ELF/COFF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 10:43:26 +00:00
Daniel Dunbar
b36052f0e4
MCCodeEmitter: Add target independent fixup flag for is-pc-relative.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98954 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 10:43:23 +00:00
Daniel Dunbar
cc5b84c6fb
MC: Add TargetAsmBackend::isVirtualSection hook.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98950 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 09:29:03 +00:00
Daniel Dunbar
87190c473c
MCAssembler: Move ApplyFixup to the TargetAsmBackend, this is a target specific not object writer specific task.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98947 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 09:28:12 +00:00
Jeffrey Yasskin
509bcb134d
Remove a memory leak from the CBackend.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 07:06:46 +00:00
Chris Lattner
60e9eac357
set SDNPVariadic on nodes throughout the rest of the targets that
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need them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98937 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 05:33:51 +00:00
Jeffrey Yasskin
c3e45f1ee2
Remove a memory leak from ThumbTargetMachine.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98936 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 05:25:28 +00:00
Chris Lattner
e8cabf3c2e
add a new SDNPVariadic SDNP node flag, and use it in
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dag isel gen instead of instruction properties. This
allows the oh-so-useful behavior of matching a variadic
non-root node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98934 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 05:07:09 +00:00
Chris Lattner
e9eda0f85d
remove some damaged sign extend patterns that can never match.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98932 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 04:53:47 +00:00
Chris Lattner
2356ae9179
disable some illegal blackfin patterns. sext from i32 to i32 can never
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match. Jakob, please take a look when you get a chance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98931 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 04:53:21 +00:00
Chris Lattner
1d7dbd1716
comment out a bunch of parallel store patterns that apparently
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can't match or just have no testcases. Will remove after
confirmation from dan that they really are dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98930 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 04:14:21 +00:00
Daniel Dunbar
6b7c2cf5d4
Fix -Asserts warnings.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98928 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 03:18:23 +00:00
Daniel Dunbar
c28c7689fc
X86: Fix encoding for TEST64rr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98919 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 01:15:03 +00:00
Chris Lattner
e3486a4c9a
Now that tblgen can handle matching implicit defs of instructions
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to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking
two inputs (which have to be the same type) and *returning an i32*.
This is how the SDNodes get made in the graph, but we weren't able
to model it this way due to deficiencies in the pattern language.
Now we can change things like this:
def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
- [(X86cmp RFP80:$lhs, RFP80:$rhs),
- (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
+ [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;
and fix terrible crimes like this:
-def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
+def : Pat<(X86cmp GR8:$src1, 0),
(TEST8rr GR8:$src1, GR8:$src1)>;
This relies on matching the result of TEST8rr (which is EFLAGS, which is
an implicit def) to the result of X86cmp, an i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:01:11 +00:00
Bob Wilson
50622ce8cf
Update comment to refer to the right filename.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98902 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 23:57:57 +00:00
Chris Lattner
de3e05fe33
tidy up
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98901 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 23:57:57 +00:00
Anton Korobeynikov
341ab138fb
Get rid of target-specific fp <-> int nodes when still I'm here.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98889 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 22:35:45 +00:00
Anton Korobeynikov
f0d500768d
Get rid of target-specific nodes for fp16 <-> fp32 conversion.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98888 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 22:35:37 +00:00
Anton Korobeynikov
6755d97a62
Refactor Reg-Reg copy emission routine for ARM. This makes cross-regclass copies weirdness more straightforward. Also, add GPR <-> SPR copy support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98887 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 22:35:02 +00:00
Eric Christopher
88dee30a6e
Couple of changes that Dan mentioned for llvm.stackprotector fast-isel.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98881 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 21:58:33 +00:00
Daniel Dunbar
9fdac902d4
X86MCCodeEmitter: Fix two minor issues with reloc_riprel_4byte_movq_load, we
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were missing it on some movq instructions and were not including the appropriate
PCrel bias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98880 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 21:53:54 +00:00
Chris Lattner
b7d5226a4e
fix some buggy ops concatentation
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98869 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 21:06:54 +00:00
Chris Lattner
6784bdf863
use ins/outs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98866 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 20:55:18 +00:00
Chris Lattner
34b8a8857c
outs come before ins.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98864 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 20:50:06 +00:00
Eric Christopher
07754c2a1b
Make fast-isel understand llvm.stackprotector.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98862 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 20:27:26 +00:00
Bob Wilson
95808328b4
Refactor NEON ld/st instructions to hardcode class arguments that are constants.
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No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98860 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 20:18:39 +00:00
Daniel Dunbar
f98bc6320b
MC/X86/AsmMatcher: Use the new instruction cleanup routine to implement a
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temporary workaround for matching inc/dec on x86_64 to the correct instruction.
- This hack will eventually be replaced with a robust mechanism for handling
matching instructions based on the available target features.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98858 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 20:06:02 +00:00
Chris Lattner
618d0ed4bc
fix an x86-64 encoding bug Daniel found.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98855 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 20:04:36 +00:00
Chris Lattner
0f53cf2236
add a special relocation type for movq loads for object
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files that produce special relocation types where the
linker changes movq's into lea's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98839 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 18:10:56 +00:00
Chris Lattner
e10038e54e
callq is pcrelative
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98835 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 17:52:22 +00:00
Bob Wilson
35ee7d6e04
Check if function names start with "llvm." before trying to lookup them up as
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intrinsics. The intrinsic lookup code assumes that this check has been done
and assumes the names are at least 6 characters long. Valgrind complained
about this. pr6638.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98831 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 16:52:15 +00:00
Benjamin Kramer
7c97ed7d07
Try to fix a valgrind error on 32 bit platforms: use %zu instead of %llu to format a size_t.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98819 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 12:18:36 +00:00
Evan Cheng
bdc652bab8
Turning off post-ra scheduling for x86. It isn't a consistent win.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98810 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 06:55:42 +00:00