Jim Grosbach
24a541b79f
ARM assembly parsing and encoding tests for UQADD16 and UQADD8.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136279 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 22:08:14 +00:00
Jim Grosbach
49f2ceddd2
ARM assembly parsing and encoding for UMULL.
...
Fix parsing of the 's' suffix for the mnemonic. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136277 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 22:01:42 +00:00
Jim Grosbach
71725a099e
ARM assembly parsing and encoding for UMLAL.
...
Fix parsing of the 's' suffix for the mnemonic. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136274 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 21:58:11 +00:00
Jim Grosbach
2adba4156b
ARM assembly parsing and encoding tests for UMAAL.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136272 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 21:53:42 +00:00
Jim Grosbach
f36b0a2ee4
ARM assembly parsing and encoding tests for UHSUB16 and UHSUB8.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136267 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 21:21:59 +00:00
Jim Grosbach
66c8982244
ARM assembly parsing and encoding tests for UHADD16, UHADD8 and UHASX.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136266 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 21:20:45 +00:00
Jim Grosbach
fb8989e640
ARM parsing and encoding of SBFX and UBFX.
...
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136264 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 21:09:25 +00:00
Jim Grosbach
b6854ad2b1
ARM assembly parsing and encoding tests for UADD16, UADD8 and UASX.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136261 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 20:43:44 +00:00
Jim Grosbach
8b3fd56e0f
ARM assembly parsing and encoding tests for TST instruction.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136260 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 20:38:58 +00:00
Jim Grosbach
f1ae78af17
ARM assembly parsing and encoding tests for TEQ instruction.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136259 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 20:37:36 +00:00
Owen Anderson
06470311c5
Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136255 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 20:29:48 +00:00
Bill Wendling
772fe17a6d
Merge the contents from exception-handling-rewrite to the mainline.
...
This adds the new instructions 'landingpad' and 'resume'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136253 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 20:18:04 +00:00
Jim Grosbach
7e1547ebf7
ARM assembly parsing and encoding for extend instructions.
...
Assembly parser handling for extend instruction rotate operands. Add tests
for the sign extend instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136252 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 20:15:40 +00:00
Nick Lewycky
e511186183
Teach the ConstantMerge pass about alignment. Fixes PR10514!
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136250 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 19:47:34 +00:00
Bruno Cardoso Lopes
cea34e41fa
The vpermilps and vpermilpd have different behaviour regarding the
...
usage of the shuffle bitmask. Both work in 128-bit lanes without
crossing, but in the former the mask of the high part is the same
used by the low part while in the later both lanes have independent
masks. Handle this properly and and add support for vpermilpd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136200 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 00:56:34 +00:00
Devang Patel
26a92003cd
It is quiet possible that inlined function body is split into multiple chunks of consequtive instructions. But, there is not any way to describe this in .debug_inline accelerator table used by gdb. However, describe non contiguous ranges of inlined function body appropriately using AT_range of DW_TAG_inlined_subroutine debug info entry.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136196 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 00:34:13 +00:00
Eric Christopher
28176195a4
Remove these two directories. The tests can be ported to dragonegg if
...
they're still wanted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136193 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27 00:07:56 +00:00
Eric Christopher
e927dc654f
Remove test/FrontendC, almost all of the tests have been migrated
...
to clang now, the rest are in process (6) or have been deleted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136191 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 23:49:39 +00:00
Jakob Stoklund Olesen
e4709777e3
Eliminate copies of undefined values during coalescing.
...
These copies would coalesce easily, but the resulting value would be
defined by a deleted instruction. Now we also remove the undefined value
number from the destination register.
This fixes PR10503.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136174 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 23:00:24 +00:00
Benjamin Kramer
25ad783322
Update test.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136170 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 22:45:39 +00:00
Benjamin Kramer
162ee5c725
Add a neat little two's complement hack for x86.
...
On x86 we can't encode an immediate LHS of a sub directly. If the RHS comes from a XOR with a constant we can
fold the negation into the xor and add one to the immediate of the sub. Then we can turn the sub into an add,
which can be commuted and encoded efficiently.
This code is generated for __builtin_clz and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136167 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 22:42:13 +00:00
Bruno Cardoso Lopes
4ea496846a
Recognize unpckh* masks and match 256-bit versions. The new versions are
...
different from the previous 128-bit because they work in lanes.
Update a few comments and add testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136157 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 22:03:40 +00:00
Eli Friedman
61cc47e15d
Prevent x86-specific DAGCombine from creating nodes with illegal type (which could not be selected). Fixes a minor isel issue that was breaking the testcase from r136130.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136148 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 21:02:58 +00:00
Jim Grosbach
84c93d4bb0
FileCheck'ize test.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136135 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 20:49:44 +00:00
Eli Friedman
ce1986bd21
XFAIL this test while I investigate it; it's failing for an unexpected reason.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136131 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 20:41:03 +00:00
Eli Friedman
24f05334e6
Add obvious missing case to switch. PR10497.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136130 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 20:38:49 +00:00
Jim Grosbach
189610f946
ARM diagnostics for ldrexd/stredx out of order paired register operands.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136110 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 18:25:39 +00:00
Jim Grosbach
36711e4a3c
ARM parsing and encoding tests for load/store exclusive instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136105 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 18:07:21 +00:00
Jim Grosbach
4f6f13db1a
ARM assembly parsing and encoding for SWP[B] instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136098 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 17:15:11 +00:00
Jim Grosbach
ed8384806e
ARM parsing and encoding for SVC instruction.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136090 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 16:24:27 +00:00
Jim Grosbach
873db3eeba
ARM assembly parsing and encoding tests for SUB instruction.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136089 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 15:44:05 +00:00
Jim Grosbach
a46c658c66
Update ARM STM tests. Fix check: prefix for diagnostic tests.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136088 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 15:41:22 +00:00
Bruno Cardoso Lopes
5d348b4dc4
Add 256-bit isel for movsldup/movshdup
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136051 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 02:39:32 +00:00
Jim Grosbach
185f92e7d0
ARM assembly parsing and encoding for SSAX, SSUB16 and SSUB8.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136013 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 23:32:14 +00:00
Nick Lewycky
5a1cb644c9
Finish adding support for lifetime intrinsics to SROA. Fixes PR10121!
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136008 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 23:14:22 +00:00
Jim Grosbach
f49433523e
ARM assembly parsing and encoding for SSAT16 instruction.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136006 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 23:09:14 +00:00
Bruno Cardoso Lopes
863bd9d5cf
Codegen allonesvector better while using AVX: vpcmpeqd + vinsertf128
...
This also fixes PR10452
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 23:05:32 +00:00
Bruno Cardoso Lopes
6a32adc4e5
- Handle special scalar_to_vector case: splats. Using a native 128-bit
...
shuffle before inserting on a 256-bit vector.
- Add AVX versions of movd/movq instructions
- Introduce a few COPY patterns to match insert_subvector instructions.
This turns a trivial insert_subvector instruction into a register copy,
coalescing the xmm into a ymm and avoid emiting on more instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136002 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 23:05:25 +00:00
Eli Friedman
9eff19896e
Attempt to fix test failure reported on llvm-commits.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135995 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 22:28:51 +00:00
Eli Friedman
ed4b4272ba
Make sure this DAGCombine actually returns an UNDEF of the correct type; PR10476.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135993 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 22:25:42 +00:00
Jim Grosbach
580f4a9c1c
ARM assembly parsing and encoding for SSAT instruction.
...
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0 ').
Add tests for diagnostics and proper encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 22:20:28 +00:00
Eli Friedman
63f8dde482
Get rid of an incorrect optimization for shuffles with PALIGNR and simplify isPALIGNRMask.
...
Addresses PR10466, although the crash from that PR only triggers in cases where DAGCombine misses optimizing a shuffle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135980 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 21:36:45 +00:00
Jim Grosbach
f2a35fbd60
Move some ELF directives into ELF asm parser.
...
The .local, .hidden, .internal, and .protected are not legal for all supported
file formats (in particular, they're invalid for MachO). Move the parsing for
them into the ELF assembly parser since that's the format they're for.
Similarly, .weak is used by COFF and ELF, but not MachO, so move the parsing
to the COFF and ELF asm parsers. Previously, using any of these directives
on Darwin would result in an assertion failure in the parser; now we get
a diagnostic as we should.
rdar://9827089
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 17:55:35 +00:00
Jakob Stoklund Olesen
b09701db9e
Correctly handle <undef> tied uses when rewriting after a split.
...
This fixes PR10463. A two-address instruction with an <undef> use
operand was incorrectly rewritten so the def and use no longer used the
same register, violating the tie constraint.
Fix this by always rewriting <undef> operands with the register a def
operand would use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135885 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-24 20:23:50 +00:00
Dan Gohman
4428069f10
Move the last uses of RetainFunc etc. over to using getRetainCallee() etc.
...
so that a declaration for objc_retain is created when needed if it doesn't
already exist. rdar://9825114.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135821 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 22:29:21 +00:00
Jim Grosbach
6ab4e3dd23
Add FIXME
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135819 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 22:15:38 +00:00
Jim Grosbach
0e76edf8c0
ARM encoding and assembly parsing tests for SMULWB, SMULWT, SMUSD and SMUSDX.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135818 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 22:13:00 +00:00
Jim Grosbach
bf2845c0d8
ARM assembly parsing and encoding updates.
...
Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135817 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 22:06:05 +00:00
Jim Grosbach
6808f21757
ARM assembly parsing and encoding tests.
...
Add tests for SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR,
SMMUL, SMMULR, SMUAD and SMUADX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135810 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 21:34:56 +00:00
Bruno Cardoso Lopes
bb37dcd66f
Fix test check!
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135802 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 20:55:28 +00:00
Bruno Cardoso Lopes
dad38638e1
Fix PR10422 by adding the necessary AVX UCOMISD memory versions to
...
load folding logic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135801 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 20:53:20 +00:00
Jim Grosbach
44a456332f
ARM assembly parsing and encoding tests for SMLAWB/SMLAWT.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135800 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 20:51:24 +00:00
Jim Grosbach
ce501030d9
ARM assembly parsing and encoding tests.
...
Tests for SMLAL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD, and SMLALDX
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135798 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 20:30:40 +00:00
Jim Grosbach
b544f68b70
ARM assembly parsing and encoding of SMLAL instruction.
...
Fix parsing of carry-setting variant SMLALS and add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135797 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 20:18:21 +00:00
Jim Grosbach
b206daaec1
ARM encoding and assembly parsing of SMLAD{X} instructions.
...
Fix encoding of destination register. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135796 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 20:11:20 +00:00
Jim Grosbach
0ffd4a09df
ARM testcases for assembly parsing and encoding SMLA* instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135795 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 20:01:34 +00:00
Rafael Espindola
23e31011fb
Turn shuffles into unpacks for VT == MVT::v2i64 and MVT::v2f64
...
too. Patch by Jeff Muizelaar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135789 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 18:56:05 +00:00
Jim Grosbach
7c9fbc0340
ARM assembly parsing and encoding for SMC instruction.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135782 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 18:13:31 +00:00
Jim Grosbach
248e6c328c
ARM encoding and assembly parsing tests.
...
Add tests for SHADD8, SHADD16, SHASX, SHSUB8, and SHSUB16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135780 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 18:04:48 +00:00
Jim Grosbach
c27d4f9ea0
ARM assembly parsing and encoding for SETEND instruction.
...
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135776 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 17:44:50 +00:00
Jim Grosbach
9076b6e8f4
ARM assembly parsing and encoding tests for SEL instruction.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135772 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 16:59:33 +00:00
Bruno Cardoso Lopes
6683efb4cd
-Inspected a AVX code block added by someone in early Feb. This was never used
...
and was actually very wrong, fix it and make it simpler. Also remove the
ConcatVectors function, which is unused now.
- Fix a introduction of useless nodes in r126664 and r126264. The
VUNPCKL* should never be introduced cause we don't want duplicate
nodes for 128 AVX and non-AVX modes, the actual instruction
difference only exists during isel, but not for target specific DAG
nodes. We only introduce V* target nodes when there is no 128-bit
version already there.
- Fix a fragile test and make it more useful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135729 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 00:15:07 +00:00
Bruno Cardoso Lopes
08b076cc96
Although we already support this, add testcases for consistency
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135728 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 00:15:03 +00:00
Bruno Cardoso Lopes
74dad551d8
Add a DAGCombine for transforming 128->256 casts into a simple
...
vxorps + vinsertf128 pair of instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135727 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22 00:15:00 +00:00
Dan Gohman
856e13ddac
Fix MergeInVectorType to check for vector types with the same alloc
...
size but different element types, so that it filters out the cases
that CreateShuffleVectorCast doesn't handle. This fixes rdar://9786827.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135721 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 23:30:09 +00:00
Jim Grosbach
8409f04731
ARM parsing and encoding tests for SBC instruction.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135718 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 23:03:59 +00:00
Jim Grosbach
8ae45af794
ARM testcases for SADD/SASX parsing and encoding.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135715 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 23:00:49 +00:00
Jim Grosbach
f790193aec
ARM assembly parsing support for RSC instruction.
...
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135713 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 22:56:30 +00:00
Jim Grosbach
86fdff0fa7
ARM assembly parsing support for RSB instruction.
...
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135712 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 22:37:43 +00:00
Jim Grosbach
616fbdf987
ARM parsing and encoding tests for RBIT, REV, REV16 and REVSH.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135710 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 22:29:23 +00:00
Jim Grosbach
a4c34ab544
ARM parsing and encodings tests for saturating arithmetic insns.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135709 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 22:18:28 +00:00
Jim Grosbach
10c7d70a4e
ARM assembly parsing POP/PUSH mnemonics.
...
Aliases for LDM/STM. The single-register versions should encode to LDR/STR
with writeback, but we don't (yet) get that correct. Neither does Darwin's
system assembler, though, so that's not a deal-breaker of a limitation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135702 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 19:57:11 +00:00
Jim Grosbach
61b1b21e9a
Add tests for ARM PKH assembly parsing.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135696 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 19:02:03 +00:00
Bruno Cardoso Lopes
dbd4fe2b0a
- Register v16i16 as valid VR256 register class
...
- Add more bitcasts for v16i16
- Since 135661 and 135662 already added the splat logic,
just add one more splat test for v16i16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135663 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 02:24:08 +00:00
Bruno Cardoso Lopes
65b74e1d00
Add support for 256-bit versions of VPERMIL instruction. This is a new
...
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:
Instead of:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vextractf128 $1, %ymm0, %xmm1
shufps $1, %xmm1, %xmm1
movss %xmm1, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm1, 16(%rsp)
vextractf128 $0, %ymm0, %xmm0
shufps $1, %xmm0, %xmm0
movss %xmm0, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm0, 4(%rsp)
movss %xmm0, (%rsp)
vmovaps (%rsp), %ymm0
We get:
vextractf128 $0, %ymm0, %xmm0
punpcklbw %xmm0, %xmm0
punpckhbw %xmm0, %xmm0
vinsertf128 $0, %xmm0, %ymm0, %ymm1
vinsertf128 $1, %xmm0, %ymm1, %ymm0
vpermilps $85, %ymm0, %ymm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135662 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 01:55:47 +00:00
Andrew Trick
c205a094bd
LSR, correct fix for rdar://9786536. Silly casting bug.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135654 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 01:45:54 +00:00
Andrew Trick
c2c988e5e0
LSR must sometimes sign-extend before generating double constants.
...
rdar://9786536
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135650 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 01:05:01 +00:00
Andrew Trick
37eb38d3f8
LSR crashes on an empty IVUsers list.
...
rdar://9786536
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135644 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21 00:40:04 +00:00
Devang Patel
4ec14b0dee
While emitting constant value, look through derived type and use underlying basic type to determine size and signness of the constant value.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135627 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 21:57:04 +00:00
Eli Friedman
73bfa4aecf
Bring LICM into compliance with the new "Memory Model for Concurrent Operations" in LangRef.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135625 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 21:37:47 +00:00
Eli Friedman
a4d0bd84f7
Extend the hack for _GLOBAL_OFFSET_TABLE_ slightly; PR10389.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135607 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 19:36:11 +00:00
Jim Grosbach
88d1bc832c
Add parsing/encoding tests for ARM ORR instruction.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135602 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 18:48:53 +00:00
Jim Grosbach
a678514459
Consolidate ARM NOP encoding test.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135600 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 18:39:38 +00:00
Jim Grosbach
c3635c2e92
ARM parsing and encoding tests for MVN
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135599 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 18:37:08 +00:00
Jim Grosbach
ab40f4b737
ARM assembly parsing of MUL instruction.
...
Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135596 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 18:20:31 +00:00
Eli Friedman
0381c21d2d
PR10421: Fix a straightforward bug in the widening logic for CONCAT_VECTORS.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135595 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 18:14:33 +00:00
Evan Cheng
e76a33b956
Add MCObjectFileInfo and sink the MCSections initialization code from
...
TargetLoweringObjectFileImpl down to MCObjectFileInfo.
TargetAsmInfo is done to one last method. It's *almost* gone!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135569 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 05:58:47 +00:00
Andrew Trick
86c98145b2
indvars: Added getInsertPointForUses to find a valid place to truncate the IV.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135568 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 05:32:06 +00:00
Eric Christopher
03c45f60f3
New pointer rotate test.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135562 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 03:09:11 +00:00
Andrew Trick
9e92152f77
indvars test case for r135558.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135559 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 02:14:37 +00:00
Andrew Trick
f22d95749a
indvars -disable-iv-rewrite fix: derived GEP IVs
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135558 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 02:08:58 +00:00
Akira Hatanaka
db54826f20
Lower memory barriers to sync instructions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135537 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 23:30:50 +00:00
Evan Cheng
70955c2d12
Fix an obvious typo that's preventing x86 (32-bit) from using .literal16.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135535 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 23:14:32 +00:00
Eli Friedman
3610604086
PR10386: Don't try to split an edge from an indirectbr.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135534 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 22:59:41 +00:00
Jim Grosbach
b29b4dd988
Tweak ARM assembly parsing and printing of MSR instruction.
...
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135532 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 22:45:10 +00:00
Jim Grosbach
80d01dd3d1
ARM assembly parsing of MRS instruction.
...
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135527 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 21:59:29 +00:00
Jim Grosbach
ccfd9313d1
ARM assembly parsing for MRC/MRC2/MRRC/MRRC2.
...
Add range checking to the immediate operands. Update tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135521 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 20:35:35 +00:00
Akira Hatanaka
cc7ecc7290
Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or
...
ANDi, when the instruction does not have any immediate operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135520 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 20:34:00 +00:00
Jim Grosbach
2317fe1584
Move mr[r]c[2] ARM tests and tidy up a bit.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135517 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 20:28:56 +00:00
Jim Grosbach
1a2be4db5b
ARM testcases for MOVT.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135516 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 20:23:25 +00:00